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[66.90.144.107]) by smtp.gmail.com with ESMTPSA id p2-20020a4ab382000000b004d8c6815287sm4542966ooo.17.2023.01.09.11.26.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Jan 2023 11:26:35 -0800 (PST) Received: (nullmailer pid 1483614 invoked by uid 1000); Mon, 09 Jan 2023 19:26:31 -0000 From: Rob Herring Date: Mon, 09 Jan 2023 13:26:21 -0600 Subject: [PATCH v4 5/8] perf: arm_spe: Use new PMSIDR_EL1 register enums MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20220825-arm-spe-v8-7-v4-5-327f860daf28@kernel.org> References: <20220825-arm-spe-v8-7-v4-0-327f860daf28@kernel.org> In-Reply-To: <20220825-arm-spe-v8-7-v4-0-327f860daf28@kernel.org> To: Peter Zijlstra , Will Deacon , Mark Rutland , Catalin Marinas , Marc Zyngier , James Morse , Alexandru Elisei , Suzuki K Poulose , Oliver Upton , Ingo Molnar , Arnaldo Carvalho de Melo , Alexander Shishkin , Jiri Olsa , Namhyung Kim Cc: Mark Brown , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-perf-users@vger.kernel.org, James Clark X-Mailer: b4 0.12-dev Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Now that the SPE register definitions include enums for some PMSIDR_EL1 fields, use them in the driver in place of magic values. Signed-off-by: Rob Herring Reviewed-by: Anshuman Khandual --- v4: - Rebase on v6.2-rc1 v3: New patch --- drivers/perf/arm_spe_pmu.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/perf/arm_spe_pmu.c b/drivers/perf/arm_spe_pmu.c index 9b4bd72087ea..af6d3867c3e7 100644 --- a/drivers/perf/arm_spe_pmu.c +++ b/drivers/perf/arm_spe_pmu.c @@ -1006,32 +1006,32 @@ static void __arm_spe_pmu_dev_probe(void *info) /* This field has a spaced out encoding, so just use a look-up */ fld =3D FIELD_GET(PMSIDR_EL1_INTERVAL, reg); switch (fld) { - case 0: + case PMSIDR_EL1_INTERVAL_256: spe_pmu->min_period =3D 256; break; - case 2: + case PMSIDR_EL1_INTERVAL_512: spe_pmu->min_period =3D 512; break; - case 3: + case PMSIDR_EL1_INTERVAL_768: spe_pmu->min_period =3D 768; break; - case 4: + case PMSIDR_EL1_INTERVAL_1024: spe_pmu->min_period =3D 1024; break; - case 5: + case PMSIDR_EL1_INTERVAL_1536: spe_pmu->min_period =3D 1536; break; - case 6: + case PMSIDR_EL1_INTERVAL_2048: spe_pmu->min_period =3D 2048; break; - case 7: + case PMSIDR_EL1_INTERVAL_3072: spe_pmu->min_period =3D 3072; break; default: dev_warn(dev, "unknown PMSIDR_EL1.Interval [%d]; assuming 8\n", fld); fallthrough; - case 8: + case PMSIDR_EL1_INTERVAL_4096: spe_pmu->min_period =3D 4096; } =20 @@ -1050,10 +1050,10 @@ static void __arm_spe_pmu_dev_probe(void *info) dev_warn(dev, "unknown PMSIDR_EL1.CountSize [%d]; assuming 2\n", fld); fallthrough; - case 2: + case PMSIDR_EL1_COUNTSIZE_12_BIT_SAT: spe_pmu->counter_sz =3D 12; break; - case 3: + case PMSIDR_EL1_COUNTSIZE_16_BIT_SAT: spe_pmu->counter_sz =3D 16; } =20 --=20 2.39.0