From nobody Mon Sep 15 21:41:12 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 17F78C6379F for ; Mon, 9 Jan 2023 19:26:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236801AbjAIT0w (ORCPT ); Mon, 9 Jan 2023 14:26:52 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60076 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229643AbjAIT0i (ORCPT ); Mon, 9 Jan 2023 14:26:38 -0500 Received: from mail-oi1-f181.google.com (mail-oi1-f181.google.com [209.85.167.181]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0C70841664; Mon, 9 Jan 2023 11:26:38 -0800 (PST) Received: by mail-oi1-f181.google.com with SMTP id e205so8030312oif.11; Mon, 09 Jan 2023 11:26:38 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6qlUF9HNd4rhwHYMQ5xuQk0FhH5s2r6XHjIaKh5J7pM=; b=Y7ZeWBzfHVQB9ojmTyJ08dCvViHssmEGq7sHa5BUc4exp4/9lJ5/rHA6gLFWUpgnsO o+GjusTJEivniZ0q20zzoi8f8tI/IJPDCgqtIf3lQn0pHI8dApCoAb0dd6JLIZc5BrTV 0aRCQGW4APt80KAeoY8LikGLV0Q+32TdFt2K+F8ESdPU5nX0nNkFf1Q3mHtzUZpkSvfF M0xMQrA6Vz9LhHPpBIBCNxiJqbjz5AlIbP1wmnf7rFCEaZ/zMJ457vJMX9OsnJNu9Ld3 ZYPoBsigoAqviB6OKsVAwzKaANccXjxNHcy4LfhqEJwu8IKl3Ifqma2Qui+oWgHSTEby P0Jg== X-Gm-Message-State: AFqh2krmLVdtgnMe59cwMQQzmd4mvyXFbfaQ2x9l4G65RkZXAZDj8dtB ckVSEBxxGvWr/WJn1A0KQh+or/UV7w== X-Google-Smtp-Source: AMrXdXs5GwdD14a9+D9T5fmo0XFg0RejaVwU/Uj/3zWCM5OroBS74qT4+WmW1Th8L5E5KwxUfeiRRg== X-Received: by 2002:a05:6808:19a8:b0:363:1cc8:566e with SMTP id bj40-20020a05680819a800b003631cc8566emr35846673oib.3.1673292397060; Mon, 09 Jan 2023 11:26:37 -0800 (PST) Received: from robh_at_kernel.org (66-90-144-107.dyn.grandenetworks.net. [66.90.144.107]) by smtp.gmail.com with ESMTPSA id 21-20020aca2115000000b00354d8589a15sm4280594oiz.45.2023.01.09.11.26.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Jan 2023 11:26:36 -0800 (PST) Received: (nullmailer pid 1483606 invoked by uid 1000); Mon, 09 Jan 2023 19:26:31 -0000 From: Rob Herring Date: Mon, 09 Jan 2023 13:26:17 -0600 Subject: [PATCH v4 1/8] perf: arm_spe: Use feature numbering for PMSEVFR_EL1 defines MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20220825-arm-spe-v8-7-v4-1-327f860daf28@kernel.org> References: <20220825-arm-spe-v8-7-v4-0-327f860daf28@kernel.org> In-Reply-To: <20220825-arm-spe-v8-7-v4-0-327f860daf28@kernel.org> To: Peter Zijlstra , Will Deacon , Mark Rutland , Catalin Marinas , Marc Zyngier , James Morse , Alexandru Elisei , Suzuki K Poulose , Oliver Upton , Ingo Molnar , Arnaldo Carvalho de Melo , Alexander Shishkin , Jiri Olsa , Namhyung Kim Cc: Mark Brown , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-perf-users@vger.kernel.org, James Clark X-Mailer: b4 0.12-dev Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Similar to commit 121a8fc088f1 ("arm64/sysreg: Use feature numbering for PMU and SPE revisions") use feature numbering instead of architecture versions for the PMSEVFR_EL1 Res0 defines. Tested-by: James Clark Signed-off-by: Rob Herring Reviewed-by: Anshuman Khandual --- v4: - Rebase on v6.2-rc1 v3: - No change v2: - New patch --- arch/arm64/include/asm/sysreg.h | 6 +++--- drivers/perf/arm_spe_pmu.c | 4 ++-- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysre= g.h index 1312fb48f18b..c4ce16333750 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -273,11 +273,11 @@ #define SYS_PMSFCR_EL1_ST_SHIFT 18 =20 #define SYS_PMSEVFR_EL1 sys_reg(3, 0, 9, 9, 5) -#define SYS_PMSEVFR_EL1_RES0_8_2 \ +#define PMSEVFR_EL1_RES0_IMP \ (GENMASK_ULL(47, 32) | GENMASK_ULL(23, 16) | GENMASK_ULL(11, 8) |\ BIT_ULL(6) | BIT_ULL(4) | BIT_ULL(2) | BIT_ULL(0)) -#define SYS_PMSEVFR_EL1_RES0_8_3 \ - (SYS_PMSEVFR_EL1_RES0_8_2 & ~(BIT_ULL(18) | BIT_ULL(17) | BIT_ULL(11))) +#define PMSEVFR_EL1_RES0_V1P1 \ + (PMSEVFR_EL1_RES0_IMP & ~(BIT_ULL(18) | BIT_ULL(17) | BIT_ULL(11))) =20 #define SYS_PMSLATFR_EL1 sys_reg(3, 0, 9, 9, 6) #define SYS_PMSLATFR_EL1_MINLAT_SHIFT 0 diff --git a/drivers/perf/arm_spe_pmu.c b/drivers/perf/arm_spe_pmu.c index 00e3a637f7b6..65cf93dcc8ee 100644 --- a/drivers/perf/arm_spe_pmu.c +++ b/drivers/perf/arm_spe_pmu.c @@ -677,11 +677,11 @@ static u64 arm_spe_pmsevfr_res0(u16 pmsver) { switch (pmsver) { case ID_AA64DFR0_EL1_PMSVer_IMP: - return SYS_PMSEVFR_EL1_RES0_8_2; + return PMSEVFR_EL1_RES0_IMP; case ID_AA64DFR0_EL1_PMSVer_V1P1: /* Return the highest version we support in default */ default: - return SYS_PMSEVFR_EL1_RES0_8_3; + return PMSEVFR_EL1_RES0_V1P1; } } =20 --=20 2.39.0 From nobody Mon Sep 15 21:41:12 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 36E86C5479D for ; Mon, 9 Jan 2023 19:26:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237459AbjAIT0r (ORCPT ); Mon, 9 Jan 2023 14:26:47 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60064 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234953AbjAIT0g (ORCPT ); Mon, 9 Jan 2023 14:26:36 -0500 Received: from mail-ot1-f49.google.com (mail-ot1-f49.google.com [209.85.210.49]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 36F9B41664; Mon, 9 Jan 2023 11:26:35 -0800 (PST) Received: by mail-ot1-f49.google.com with SMTP id m7-20020a9d73c7000000b00683e2f36c18so5789820otk.0; Mon, 09 Jan 2023 11:26:35 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BcrTbyiXOqTd2Z8hAA/NR+Cyql1m++RO4yWjBmkFpb4=; b=f3EYB9VyiAyLJHMejUU/8gCWHC0ndPCLLLZdEwNGOIBpt0Cerpio/Hl4pXD3L0SEPB AylnHN1u7fcwwnefKyxZCm+MB0LNwEsQBVBHn/KLXWllacIAbPceQvHja/LOeLlOmNgo aZqI2LiXHwiVM2dUpAnbJ2RBlAmag6YR4k6hbv6zg/cMytOGxhDhP3zaL4eZ0S1GR0ZH u2rel9yvhfJymyTaBczD/CyRgO+2NhE9GFU3EOFQHF81MF2hV8vdaIu9Hp8RFpxLzoeB qP0SCzL07+Bd+XoElj8A6a0EAm5vEQE58r56J2TQf+2JiIBIq0k8UGKgcXyKPYlUpX3Q Ym7Q== X-Gm-Message-State: AFqh2kp+njYX1QK1nV4G8IMdCENvfGmHLAEjzq5x9H1DiPLigQKIWBNi 4YPutIxHDD7czihllihapw40a4RkRw== X-Google-Smtp-Source: AMrXdXs2pu4MQZ07GB6NVmce+RmrdmRvSxSQoxopyNk+yJuGZpKkSL1f47F7NpBTAmsMO8TyyMpNYA== X-Received: by 2002:a9d:4f0a:0:b0:670:61a6:bbb2 with SMTP id d10-20020a9d4f0a000000b0067061a6bbb2mr32264173otl.24.1673292394132; Mon, 09 Jan 2023 11:26:34 -0800 (PST) Received: from robh_at_kernel.org (66-90-144-107.dyn.grandenetworks.net. [66.90.144.107]) by smtp.gmail.com with ESMTPSA id cb2-20020a056830618200b0068460566f4bsm4995976otb.30.2023.01.09.11.26.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Jan 2023 11:26:33 -0800 (PST) Received: (nullmailer pid 1483608 invoked by uid 1000); Mon, 09 Jan 2023 19:26:31 -0000 From: Rob Herring Date: Mon, 09 Jan 2023 13:26:18 -0600 Subject: [PATCH v4 2/8] arm64: Drop SYS_ from SPE register defines MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20220825-arm-spe-v8-7-v4-2-327f860daf28@kernel.org> References: <20220825-arm-spe-v8-7-v4-0-327f860daf28@kernel.org> In-Reply-To: <20220825-arm-spe-v8-7-v4-0-327f860daf28@kernel.org> To: Peter Zijlstra , Will Deacon , Mark Rutland , Catalin Marinas , Marc Zyngier , James Morse , Alexandru Elisei , Suzuki K Poulose , Oliver Upton , Ingo Molnar , Arnaldo Carvalho de Melo , Alexander Shishkin , Jiri Olsa , Namhyung Kim Cc: Mark Brown , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-perf-users@vger.kernel.org, James Clark X-Mailer: b4 0.12-dev Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org We currently have a non-standard SYS_ prefix in the constants generated for the SPE register bitfields. Drop this in preparation for automatic register definition generation. The SPE mask defines were unshifted, and the SPE register field enumerations were shifted. The autogenerated defines are the opposite, so make the necessary adjustments. No functional changes. Tested-by: James Clark Signed-off-by: Rob Herring Reviewed-by: Anshuman Khandual --- v4: - Rebase on v6.2-rc1 v3: - No change v2: - New patch --- arch/arm64/include/asm/el2_setup.h | 6 +- arch/arm64/include/asm/sysreg.h | 112 ++++++++++++++++++---------------= ---- arch/arm64/kvm/debug.c | 2 +- arch/arm64/kvm/hyp/nvhe/debug-sr.c | 2 +- drivers/perf/arm_spe_pmu.c | 85 ++++++++++++++-------------- 5 files changed, 103 insertions(+), 104 deletions(-) diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el= 2_setup.h index 668569adf4d3..f9da43e53cdb 100644 --- a/arch/arm64/include/asm/el2_setup.h +++ b/arch/arm64/include/asm/el2_setup.h @@ -53,10 +53,10 @@ cbz x0, .Lskip_spe_\@ // Skip if SPE not present =20 mrs_s x0, SYS_PMBIDR_EL1 // If SPE available at EL2, - and x0, x0, #(1 << SYS_PMBIDR_EL1_P_SHIFT) + and x0, x0, #(1 << PMBIDR_EL1_P_SHIFT) cbnz x0, .Lskip_spe_el2_\@ // then permit sampling of physical - mov x0, #(1 << SYS_PMSCR_EL2_PCT_SHIFT | \ - 1 << SYS_PMSCR_EL2_PA_SHIFT) + mov x0, #(1 << PMSCR_EL2_PCT_SHIFT | \ + 1 << PMSCR_EL2_PA_SHIFT) msr_s SYS_PMSCR_EL2, x0 // addresses and physical counter .Lskip_spe_el2_\@: mov x0, #(MDCR_EL2_E2PB_MASK << MDCR_EL2_E2PB_SHIFT) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysre= g.h index c4ce16333750..dbb0e8e22cf4 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -218,59 +218,59 @@ /*** Statistical Profiling Extension ***/ /* ID registers */ #define SYS_PMSIDR_EL1 sys_reg(3, 0, 9, 9, 7) -#define SYS_PMSIDR_EL1_FE_SHIFT 0 -#define SYS_PMSIDR_EL1_FT_SHIFT 1 -#define SYS_PMSIDR_EL1_FL_SHIFT 2 -#define SYS_PMSIDR_EL1_ARCHINST_SHIFT 3 -#define SYS_PMSIDR_EL1_LDS_SHIFT 4 -#define SYS_PMSIDR_EL1_ERND_SHIFT 5 -#define SYS_PMSIDR_EL1_INTERVAL_SHIFT 8 -#define SYS_PMSIDR_EL1_INTERVAL_MASK 0xfUL -#define SYS_PMSIDR_EL1_MAXSIZE_SHIFT 12 -#define SYS_PMSIDR_EL1_MAXSIZE_MASK 0xfUL -#define SYS_PMSIDR_EL1_COUNTSIZE_SHIFT 16 -#define SYS_PMSIDR_EL1_COUNTSIZE_MASK 0xfUL +#define PMSIDR_EL1_FE_SHIFT 0 +#define PMSIDR_EL1_FT_SHIFT 1 +#define PMSIDR_EL1_FL_SHIFT 2 +#define PMSIDR_EL1_ARCHINST_SHIFT 3 +#define PMSIDR_EL1_LDS_SHIFT 4 +#define PMSIDR_EL1_ERND_SHIFT 5 +#define PMSIDR_EL1_INTERVAL_SHIFT 8 +#define PMSIDR_EL1_INTERVAL_MASK GENMASK_ULL(11, 8) +#define PMSIDR_EL1_MAXSIZE_SHIFT 12 +#define PMSIDR_EL1_MAXSIZE_MASK GENMASK_ULL(15, 12) +#define PMSIDR_EL1_COUNTSIZE_SHIFT 16 +#define PMSIDR_EL1_COUNTSIZE_MASK GENMASK_ULL(19, 16) =20 #define SYS_PMBIDR_EL1 sys_reg(3, 0, 9, 10, 7) -#define SYS_PMBIDR_EL1_ALIGN_SHIFT 0 -#define SYS_PMBIDR_EL1_ALIGN_MASK 0xfU -#define SYS_PMBIDR_EL1_P_SHIFT 4 -#define SYS_PMBIDR_EL1_F_SHIFT 5 +#define PMBIDR_EL1_ALIGN_SHIFT 0 +#define PMBIDR_EL1_ALIGN_MASK 0xfU +#define PMBIDR_EL1_P_SHIFT 4 +#define PMBIDR_EL1_F_SHIFT 5 =20 /* Sampling controls */ #define SYS_PMSCR_EL1 sys_reg(3, 0, 9, 9, 0) -#define SYS_PMSCR_EL1_E0SPE_SHIFT 0 -#define SYS_PMSCR_EL1_E1SPE_SHIFT 1 -#define SYS_PMSCR_EL1_CX_SHIFT 3 -#define SYS_PMSCR_EL1_PA_SHIFT 4 -#define SYS_PMSCR_EL1_TS_SHIFT 5 -#define SYS_PMSCR_EL1_PCT_SHIFT 6 +#define PMSCR_EL1_E0SPE_SHIFT 0 +#define PMSCR_EL1_E1SPE_SHIFT 1 +#define PMSCR_EL1_CX_SHIFT 3 +#define PMSCR_EL1_PA_SHIFT 4 +#define PMSCR_EL1_TS_SHIFT 5 +#define PMSCR_EL1_PCT_SHIFT 6 =20 #define SYS_PMSCR_EL2 sys_reg(3, 4, 9, 9, 0) -#define SYS_PMSCR_EL2_E0HSPE_SHIFT 0 -#define SYS_PMSCR_EL2_E2SPE_SHIFT 1 -#define SYS_PMSCR_EL2_CX_SHIFT 3 -#define SYS_PMSCR_EL2_PA_SHIFT 4 -#define SYS_PMSCR_EL2_TS_SHIFT 5 -#define SYS_PMSCR_EL2_PCT_SHIFT 6 +#define PMSCR_EL2_E0HSPE_SHIFT 0 +#define PMSCR_EL2_E2SPE_SHIFT 1 +#define PMSCR_EL2_CX_SHIFT 3 +#define PMSCR_EL2_PA_SHIFT 4 +#define PMSCR_EL2_TS_SHIFT 5 +#define PMSCR_EL2_PCT_SHIFT 6 =20 #define SYS_PMSICR_EL1 sys_reg(3, 0, 9, 9, 2) =20 #define SYS_PMSIRR_EL1 sys_reg(3, 0, 9, 9, 3) -#define SYS_PMSIRR_EL1_RND_SHIFT 0 -#define SYS_PMSIRR_EL1_INTERVAL_SHIFT 8 -#define SYS_PMSIRR_EL1_INTERVAL_MASK 0xffffffUL +#define PMSIRR_EL1_RND_SHIFT 0 +#define PMSIRR_EL1_INTERVAL_SHIFT 8 +#define PMSIRR_EL1_INTERVAL_MASK GENMASK_ULL(31, 8) =20 /* Filtering controls */ #define SYS_PMSNEVFR_EL1 sys_reg(3, 0, 9, 9, 1) =20 #define SYS_PMSFCR_EL1 sys_reg(3, 0, 9, 9, 4) -#define SYS_PMSFCR_EL1_FE_SHIFT 0 -#define SYS_PMSFCR_EL1_FT_SHIFT 1 -#define SYS_PMSFCR_EL1_FL_SHIFT 2 -#define SYS_PMSFCR_EL1_B_SHIFT 16 -#define SYS_PMSFCR_EL1_LD_SHIFT 17 -#define SYS_PMSFCR_EL1_ST_SHIFT 18 +#define PMSFCR_EL1_FE_SHIFT 0 +#define PMSFCR_EL1_FT_SHIFT 1 +#define PMSFCR_EL1_FL_SHIFT 2 +#define PMSFCR_EL1_B_SHIFT 16 +#define PMSFCR_EL1_LD_SHIFT 17 +#define PMSFCR_EL1_ST_SHIFT 18 =20 #define SYS_PMSEVFR_EL1 sys_reg(3, 0, 9, 9, 5) #define PMSEVFR_EL1_RES0_IMP \ @@ -280,37 +280,37 @@ (PMSEVFR_EL1_RES0_IMP & ~(BIT_ULL(18) | BIT_ULL(17) | BIT_ULL(11))) =20 #define SYS_PMSLATFR_EL1 sys_reg(3, 0, 9, 9, 6) -#define SYS_PMSLATFR_EL1_MINLAT_SHIFT 0 +#define PMSLATFR_EL1_MINLAT_SHIFT 0 =20 /* Buffer controls */ #define SYS_PMBLIMITR_EL1 sys_reg(3, 0, 9, 10, 0) -#define SYS_PMBLIMITR_EL1_E_SHIFT 0 -#define SYS_PMBLIMITR_EL1_FM_SHIFT 1 -#define SYS_PMBLIMITR_EL1_FM_MASK 0x3UL -#define SYS_PMBLIMITR_EL1_FM_STOP_IRQ (0 << SYS_PMBLIMITR_EL1_FM_SHIFT) +#define PMBLIMITR_EL1_E_SHIFT 0 +#define PMBLIMITR_EL1_FM_SHIFT 1 +#define PMBLIMITR_EL1_FM_MASK GENMASK_ULL(2, 1) +#define PMBLIMITR_EL1_FM_STOP_IRQ 0 =20 #define SYS_PMBPTR_EL1 sys_reg(3, 0, 9, 10, 1) =20 /* Buffer error reporting */ #define SYS_PMBSR_EL1 sys_reg(3, 0, 9, 10, 3) -#define SYS_PMBSR_EL1_COLL_SHIFT 16 -#define SYS_PMBSR_EL1_S_SHIFT 17 -#define SYS_PMBSR_EL1_EA_SHIFT 18 -#define SYS_PMBSR_EL1_DL_SHIFT 19 -#define SYS_PMBSR_EL1_EC_SHIFT 26 -#define SYS_PMBSR_EL1_EC_MASK 0x3fUL +#define PMBSR_EL1_COLL_SHIFT 16 +#define PMBSR_EL1_S_SHIFT 17 +#define PMBSR_EL1_EA_SHIFT 18 +#define PMBSR_EL1_DL_SHIFT 19 +#define PMBSR_EL1_EC_SHIFT 26 +#define PMBSR_EL1_EC_MASK GENMASK_ULL(31, 26) =20 -#define SYS_PMBSR_EL1_EC_BUF (0x0UL << SYS_PMBSR_EL1_EC_SHIFT) -#define SYS_PMBSR_EL1_EC_FAULT_S1 (0x24UL << SYS_PMBSR_EL1_EC_SHIFT) -#define SYS_PMBSR_EL1_EC_FAULT_S2 (0x25UL << SYS_PMBSR_EL1_EC_SHIFT) +#define PMBSR_EL1_EC_BUF 0x0UL +#define PMBSR_EL1_EC_FAULT_S1 0x24UL +#define PMBSR_EL1_EC_FAULT_S2 0x25UL =20 -#define SYS_PMBSR_EL1_FAULT_FSC_SHIFT 0 -#define SYS_PMBSR_EL1_FAULT_FSC_MASK 0x3fUL +#define PMBSR_EL1_FAULT_FSC_SHIFT 0 +#define PMBSR_EL1_FAULT_FSC_MASK 0x3fUL =20 -#define SYS_PMBSR_EL1_BUF_BSC_SHIFT 0 -#define SYS_PMBSR_EL1_BUF_BSC_MASK 0x3fUL +#define PMBSR_EL1_BUF_BSC_SHIFT 0 +#define PMBSR_EL1_BUF_BSC_MASK 0x3fUL =20 -#define SYS_PMBSR_EL1_BUF_BSC_FULL (0x1UL << SYS_PMBSR_EL1_BUF_BSC_SHIFT) +#define PMBSR_EL1_BUF_BSC_FULL 0x1UL =20 /*** End of Statistical Profiling Extension ***/ =20 diff --git a/arch/arm64/kvm/debug.c b/arch/arm64/kvm/debug.c index fccf9ec01813..55f80fb93925 100644 --- a/arch/arm64/kvm/debug.c +++ b/arch/arm64/kvm/debug.c @@ -328,7 +328,7 @@ void kvm_arch_vcpu_load_debug_state_flags(struct kvm_vc= pu *vcpu) * we may need to check if the host state needs to be saved. */ if (cpuid_feature_extract_unsigned_field(dfr0, ID_AA64DFR0_EL1_PMSVer_SHI= FT) && - !(read_sysreg_s(SYS_PMBIDR_EL1) & BIT(SYS_PMBIDR_EL1_P_SHIFT))) + !(read_sysreg_s(SYS_PMBIDR_EL1) & BIT(PMBIDR_EL1_P_SHIFT))) vcpu_set_flag(vcpu, DEBUG_STATE_SAVE_SPE); =20 /* Check if we have TRBE implemented and available at the host */ diff --git a/arch/arm64/kvm/hyp/nvhe/debug-sr.c b/arch/arm64/kvm/hyp/nvhe/d= ebug-sr.c index e17455773b98..2673bde62fad 100644 --- a/arch/arm64/kvm/hyp/nvhe/debug-sr.c +++ b/arch/arm64/kvm/hyp/nvhe/debug-sr.c @@ -27,7 +27,7 @@ static void __debug_save_spe(u64 *pmscr_el1) * Check if the host is actually using it ? */ reg =3D read_sysreg_s(SYS_PMBLIMITR_EL1); - if (!(reg & BIT(SYS_PMBLIMITR_EL1_E_SHIFT))) + if (!(reg & BIT(PMBLIMITR_EL1_E_SHIFT))) return; =20 /* Yes; save the control register and disable data generation */ diff --git a/drivers/perf/arm_spe_pmu.c b/drivers/perf/arm_spe_pmu.c index 65cf93dcc8ee..814ed18346b6 100644 --- a/drivers/perf/arm_spe_pmu.c +++ b/drivers/perf/arm_spe_pmu.c @@ -12,6 +12,7 @@ #define DRVNAME PMUNAME "_pmu" #define pr_fmt(fmt) DRVNAME ": " fmt =20 +#include #include #include #include @@ -282,18 +283,18 @@ static u64 arm_spe_event_to_pmscr(struct perf_event *= event) struct perf_event_attr *attr =3D &event->attr; u64 reg =3D 0; =20 - reg |=3D ATTR_CFG_GET_FLD(attr, ts_enable) << SYS_PMSCR_EL1_TS_SHIFT; - reg |=3D ATTR_CFG_GET_FLD(attr, pa_enable) << SYS_PMSCR_EL1_PA_SHIFT; - reg |=3D ATTR_CFG_GET_FLD(attr, pct_enable) << SYS_PMSCR_EL1_PCT_SHIFT; + reg |=3D ATTR_CFG_GET_FLD(attr, ts_enable) << PMSCR_EL1_TS_SHIFT; + reg |=3D ATTR_CFG_GET_FLD(attr, pa_enable) << PMSCR_EL1_PA_SHIFT; + reg |=3D ATTR_CFG_GET_FLD(attr, pct_enable) << PMSCR_EL1_PCT_SHIFT; =20 if (!attr->exclude_user) - reg |=3D BIT(SYS_PMSCR_EL1_E0SPE_SHIFT); + reg |=3D BIT(PMSCR_EL1_E0SPE_SHIFT); =20 if (!attr->exclude_kernel) - reg |=3D BIT(SYS_PMSCR_EL1_E1SPE_SHIFT); + reg |=3D BIT(PMSCR_EL1_E1SPE_SHIFT); =20 if (get_spe_event_has_cx(event)) - reg |=3D BIT(SYS_PMSCR_EL1_CX_SHIFT); + reg |=3D BIT(PMSCR_EL1_CX_SHIFT); =20 return reg; } @@ -302,8 +303,7 @@ static void arm_spe_event_sanitise_period(struct perf_e= vent *event) { struct arm_spe_pmu *spe_pmu =3D to_spe_pmu(event->pmu); u64 period =3D event->hw.sample_period; - u64 max_period =3D SYS_PMSIRR_EL1_INTERVAL_MASK - << SYS_PMSIRR_EL1_INTERVAL_SHIFT; + u64 max_period =3D PMSIRR_EL1_INTERVAL_MASK; =20 if (period < spe_pmu->min_period) period =3D spe_pmu->min_period; @@ -322,7 +322,7 @@ static u64 arm_spe_event_to_pmsirr(struct perf_event *e= vent) =20 arm_spe_event_sanitise_period(event); =20 - reg |=3D ATTR_CFG_GET_FLD(attr, jitter) << SYS_PMSIRR_EL1_RND_SHIFT; + reg |=3D ATTR_CFG_GET_FLD(attr, jitter) << PMSIRR_EL1_RND_SHIFT; reg |=3D event->hw.sample_period; =20 return reg; @@ -333,18 +333,18 @@ static u64 arm_spe_event_to_pmsfcr(struct perf_event = *event) struct perf_event_attr *attr =3D &event->attr; u64 reg =3D 0; =20 - reg |=3D ATTR_CFG_GET_FLD(attr, load_filter) << SYS_PMSFCR_EL1_LD_SHIFT; - reg |=3D ATTR_CFG_GET_FLD(attr, store_filter) << SYS_PMSFCR_EL1_ST_SHIFT; - reg |=3D ATTR_CFG_GET_FLD(attr, branch_filter) << SYS_PMSFCR_EL1_B_SHIFT; + reg |=3D ATTR_CFG_GET_FLD(attr, load_filter) << PMSFCR_EL1_LD_SHIFT; + reg |=3D ATTR_CFG_GET_FLD(attr, store_filter) << PMSFCR_EL1_ST_SHIFT; + reg |=3D ATTR_CFG_GET_FLD(attr, branch_filter) << PMSFCR_EL1_B_SHIFT; =20 if (reg) - reg |=3D BIT(SYS_PMSFCR_EL1_FT_SHIFT); + reg |=3D BIT(PMSFCR_EL1_FT_SHIFT); =20 if (ATTR_CFG_GET_FLD(attr, event_filter)) - reg |=3D BIT(SYS_PMSFCR_EL1_FE_SHIFT); + reg |=3D BIT(PMSFCR_EL1_FE_SHIFT); =20 if (ATTR_CFG_GET_FLD(attr, min_latency)) - reg |=3D BIT(SYS_PMSFCR_EL1_FL_SHIFT); + reg |=3D BIT(PMSFCR_EL1_FL_SHIFT); =20 return reg; } @@ -359,7 +359,7 @@ static u64 arm_spe_event_to_pmslatfr(struct perf_event = *event) { struct perf_event_attr *attr =3D &event->attr; return ATTR_CFG_GET_FLD(attr, min_latency) - << SYS_PMSLATFR_EL1_MINLAT_SHIFT; + << PMSLATFR_EL1_MINLAT_SHIFT; } =20 static void arm_spe_pmu_pad_buf(struct perf_output_handle *handle, int len) @@ -511,7 +511,7 @@ static void arm_spe_perf_aux_output_begin(struct perf_o= utput_handle *handle, limit =3D buf->snapshot ? arm_spe_pmu_next_snapshot_off(handle) : arm_spe_pmu_next_off(handle); if (limit) - limit |=3D BIT(SYS_PMBLIMITR_EL1_E_SHIFT); + limit |=3D BIT(PMBLIMITR_EL1_E_SHIFT); =20 limit +=3D (u64)buf->base; base =3D (u64)buf->base + PERF_IDX2OFF(handle->head, buf); @@ -570,28 +570,28 @@ arm_spe_pmu_buf_get_fault_act(struct perf_output_hand= le *handle) =20 /* Service required? */ pmbsr =3D read_sysreg_s(SYS_PMBSR_EL1); - if (!(pmbsr & BIT(SYS_PMBSR_EL1_S_SHIFT))) + if (!(pmbsr & BIT(PMBSR_EL1_S_SHIFT))) return SPE_PMU_BUF_FAULT_ACT_SPURIOUS; =20 /* * If we've lost data, disable profiling and also set the PARTIAL * flag to indicate that the last record is corrupted. */ - if (pmbsr & BIT(SYS_PMBSR_EL1_DL_SHIFT)) + if (pmbsr & BIT(PMBSR_EL1_DL_SHIFT)) perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED | PERF_AUX_FLAG_PARTIAL); =20 /* Report collisions to userspace so that it can up the period */ - if (pmbsr & BIT(SYS_PMBSR_EL1_COLL_SHIFT)) + if (pmbsr & BIT(PMBSR_EL1_COLL_SHIFT)) perf_aux_output_flag(handle, PERF_AUX_FLAG_COLLISION); =20 /* We only expect buffer management events */ - switch (pmbsr & (SYS_PMBSR_EL1_EC_MASK << SYS_PMBSR_EL1_EC_SHIFT)) { - case SYS_PMBSR_EL1_EC_BUF: + switch (FIELD_GET(PMBSR_EL1_EC_MASK, pmbsr)) { + case PMBSR_EL1_EC_BUF: /* Handled below */ break; - case SYS_PMBSR_EL1_EC_FAULT_S1: - case SYS_PMBSR_EL1_EC_FAULT_S2: + case PMBSR_EL1_EC_FAULT_S1: + case PMBSR_EL1_EC_FAULT_S2: err_str =3D "Unexpected buffer fault"; goto out_err; default: @@ -600,9 +600,8 @@ arm_spe_pmu_buf_get_fault_act(struct perf_output_handle= *handle) } =20 /* Buffer management event */ - switch (pmbsr & - (SYS_PMBSR_EL1_BUF_BSC_MASK << SYS_PMBSR_EL1_BUF_BSC_SHIFT)) { - case SYS_PMBSR_EL1_BUF_BSC_FULL: + switch (FIELD_GET(PMBSR_EL1_BUF_BSC_MASK, pmbsr)) { + case PMBSR_EL1_BUF_BSC_FULL: ret =3D SPE_PMU_BUF_FAULT_ACT_OK; goto out_stop; default: @@ -717,23 +716,23 @@ static int arm_spe_pmu_event_init(struct perf_event *= event) return -EINVAL; =20 reg =3D arm_spe_event_to_pmsfcr(event); - if ((reg & BIT(SYS_PMSFCR_EL1_FE_SHIFT)) && + if ((reg & BIT(PMSFCR_EL1_FE_SHIFT)) && !(spe_pmu->features & SPE_PMU_FEAT_FILT_EVT)) return -EOPNOTSUPP; =20 - if ((reg & BIT(SYS_PMSFCR_EL1_FT_SHIFT)) && + if ((reg & BIT(PMSFCR_EL1_FT_SHIFT)) && !(spe_pmu->features & SPE_PMU_FEAT_FILT_TYP)) return -EOPNOTSUPP; =20 - if ((reg & BIT(SYS_PMSFCR_EL1_FL_SHIFT)) && + if ((reg & BIT(PMSFCR_EL1_FL_SHIFT)) && !(spe_pmu->features & SPE_PMU_FEAT_FILT_LAT)) return -EOPNOTSUPP; =20 set_spe_event_has_cx(event); reg =3D arm_spe_event_to_pmscr(event); if (!perfmon_capable() && - (reg & (BIT(SYS_PMSCR_EL1_PA_SHIFT) | - BIT(SYS_PMSCR_EL1_PCT_SHIFT)))) + (reg & (BIT(PMSCR_EL1_PA_SHIFT) | + BIT(PMSCR_EL1_PCT_SHIFT)))) return -EACCES; =20 return 0; @@ -971,14 +970,14 @@ static void __arm_spe_pmu_dev_probe(void *info) =20 /* Read PMBIDR first to determine whether or not we have access */ reg =3D read_sysreg_s(SYS_PMBIDR_EL1); - if (reg & BIT(SYS_PMBIDR_EL1_P_SHIFT)) { + if (reg & BIT(PMBIDR_EL1_P_SHIFT)) { dev_err(dev, "profiling buffer owned by higher exception level\n"); return; } =20 /* Minimum alignment. If it's out-of-range, then fail the probe */ - fld =3D reg >> SYS_PMBIDR_EL1_ALIGN_SHIFT & SYS_PMBIDR_EL1_ALIGN_MASK; + fld =3D (reg & PMBIDR_EL1_ALIGN_MASK) >> PMBIDR_EL1_ALIGN_SHIFT; spe_pmu->align =3D 1 << fld; if (spe_pmu->align > SZ_2K) { dev_err(dev, "unsupported PMBIDR.Align [%d] on CPU %d\n", @@ -988,26 +987,26 @@ static void __arm_spe_pmu_dev_probe(void *info) =20 /* It's now safe to read PMSIDR and figure out what we've got */ reg =3D read_sysreg_s(SYS_PMSIDR_EL1); - if (reg & BIT(SYS_PMSIDR_EL1_FE_SHIFT)) + if (reg & BIT(PMSIDR_EL1_FE_SHIFT)) spe_pmu->features |=3D SPE_PMU_FEAT_FILT_EVT; =20 - if (reg & BIT(SYS_PMSIDR_EL1_FT_SHIFT)) + if (reg & BIT(PMSIDR_EL1_FT_SHIFT)) spe_pmu->features |=3D SPE_PMU_FEAT_FILT_TYP; =20 - if (reg & BIT(SYS_PMSIDR_EL1_FL_SHIFT)) + if (reg & BIT(PMSIDR_EL1_FL_SHIFT)) spe_pmu->features |=3D SPE_PMU_FEAT_FILT_LAT; =20 - if (reg & BIT(SYS_PMSIDR_EL1_ARCHINST_SHIFT)) + if (reg & BIT(PMSIDR_EL1_ARCHINST_SHIFT)) spe_pmu->features |=3D SPE_PMU_FEAT_ARCH_INST; =20 - if (reg & BIT(SYS_PMSIDR_EL1_LDS_SHIFT)) + if (reg & BIT(PMSIDR_EL1_LDS_SHIFT)) spe_pmu->features |=3D SPE_PMU_FEAT_LDS; =20 - if (reg & BIT(SYS_PMSIDR_EL1_ERND_SHIFT)) + if (reg & BIT(PMSIDR_EL1_ERND_SHIFT)) spe_pmu->features |=3D SPE_PMU_FEAT_ERND; =20 /* This field has a spaced out encoding, so just use a look-up */ - fld =3D reg >> SYS_PMSIDR_EL1_INTERVAL_SHIFT & SYS_PMSIDR_EL1_INTERVAL_MA= SK; + fld =3D (reg & PMSIDR_EL1_INTERVAL_MASK) >> PMSIDR_EL1_INTERVAL_SHIFT; switch (fld) { case 0: spe_pmu->min_period =3D 256; @@ -1039,7 +1038,7 @@ static void __arm_spe_pmu_dev_probe(void *info) } =20 /* Maximum record size. If it's out-of-range, then fail the probe */ - fld =3D reg >> SYS_PMSIDR_EL1_MAXSIZE_SHIFT & SYS_PMSIDR_EL1_MAXSIZE_MASK; + fld =3D (reg & PMSIDR_EL1_MAXSIZE_MASK) >> PMSIDR_EL1_MAXSIZE_SHIFT; spe_pmu->max_record_sz =3D 1 << fld; if (spe_pmu->max_record_sz > SZ_2K || spe_pmu->max_record_sz < 16) { dev_err(dev, "unsupported PMSIDR_EL1.MaxSize [%d] on CPU %d\n", @@ -1047,7 +1046,7 @@ static void __arm_spe_pmu_dev_probe(void *info) return; } =20 - fld =3D reg >> SYS_PMSIDR_EL1_COUNTSIZE_SHIFT & SYS_PMSIDR_EL1_COUNTSIZE_= MASK; + fld =3D (reg & PMSIDR_EL1_COUNTSIZE_MASK) >> PMSIDR_EL1_COUNTSIZE_SHIFT; switch (fld) { default: dev_warn(dev, "unknown PMSIDR_EL1.CountSize [%d]; assuming 2\n", --=20 2.39.0 From nobody Mon Sep 15 21:41:12 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 42369C54EBD for ; Mon, 9 Jan 2023 19:27:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234972AbjAIT1B (ORCPT ); Mon, 9 Jan 2023 14:27:01 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60126 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237404AbjAIT0m (ORCPT ); Mon, 9 Jan 2023 14:26:42 -0500 Received: from mail-ot1-f48.google.com (mail-ot1-f48.google.com [209.85.210.48]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2A5B341664; Mon, 9 Jan 2023 11:26:41 -0800 (PST) Received: by mail-ot1-f48.google.com with SMTP id x25-20020a056830115900b00670932eff32so5729553otq.3; Mon, 09 Jan 2023 11:26:41 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rz2iRPDu/kU47mL2nLBk7PH3KxdS0ijqRPpZ+NAWlPg=; b=d9NMnN2z9LHDzZZsmfdFA8/zHe+mfl21OPxvtCl+FF+aEDqeJVIj8yI/leFWPatk0o wnmZZroOytm/asCczxjpp1+NzYa05XEkl01S7ZP91Ng7KlWV2QzziLDZty0yj3aRGCfy YlMQwVtr6v9SgPvTLUAl3bSFm4UlDfxfy1WBIyTd6Q7gYU0fFLmt8u+IL7F073r+V85m tVgWq+1zIHdTdfUWikLBdhYxsoY1MhFFGutWhOpuKKJTDoFMotFdy4hMT2DMA4IgOEQH R8g14hVuESWZg0OrX7ZEx0Ras1AsiGO1vrtfY87wEDsTAE+nPJWGIBahXaiY8ChrvZM3 wlXw== X-Gm-Message-State: AFqh2koWY/91LM6ILDTwTo1KSs+ZVAGcvmMwp/8NFdpPujJWl8Y/lkCL hxc+QRzp4Df9SkSch3s4OC8u883bpw== X-Google-Smtp-Source: AMrXdXt4N7Ek74CSUz+QdNJ6wzP3Y+qPWTWggKjMsGeJbMO9BW55S1U852857myfgsKuKnTaNqEb5g== X-Received: by 2002:a05:6830:1e2f:b0:67a:1598:de18 with SMTP id t15-20020a0568301e2f00b0067a1598de18mr30855508otr.6.1673292400179; Mon, 09 Jan 2023 11:26:40 -0800 (PST) Received: from robh_at_kernel.org (66-90-144-107.dyn.grandenetworks.net. [66.90.144.107]) by smtp.gmail.com with ESMTPSA id s14-20020a05683004ce00b0066c34486aa7sm4940362otd.73.2023.01.09.11.26.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Jan 2023 11:26:39 -0800 (PST) Received: (nullmailer pid 1483610 invoked by uid 1000); Mon, 09 Jan 2023 19:26:31 -0000 From: Rob Herring Date: Mon, 09 Jan 2023 13:26:19 -0600 Subject: [PATCH v4 3/8] arm64/sysreg: Convert SPE registers to automatic generation MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20220825-arm-spe-v8-7-v4-3-327f860daf28@kernel.org> References: <20220825-arm-spe-v8-7-v4-0-327f860daf28@kernel.org> In-Reply-To: <20220825-arm-spe-v8-7-v4-0-327f860daf28@kernel.org> To: Peter Zijlstra , Will Deacon , Mark Rutland , Catalin Marinas , Marc Zyngier , James Morse , Alexandru Elisei , Suzuki K Poulose , Oliver Upton , Ingo Molnar , Arnaldo Carvalho de Melo , Alexander Shishkin , Jiri Olsa , Namhyung Kim Cc: Mark Brown , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-perf-users@vger.kernel.org, James Clark X-Mailer: b4 0.12-dev Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Convert all the SPE register defines to automatic generation. No functional changes. New registers and fields for SPEv1.2 are added with the conversion. Some of the PMBSR MSS field defines are kept as the automatic generation has no way to create multiple names for the same register bits. The meaning of the MSS field depends on other bits. Tested-by: James Clark Signed-off-by: Rob Herring Reviewed-by: Anshuman Khandual Reviewed-by: Mark Brown --- v4: - Rebase on v6.2-rc1 v3: - Make some fields enums and add some missing fields v2: - New patch --- arch/arm64/include/asm/sysreg.h | 91 ++------------------------ arch/arm64/tools/sysreg | 139 ++++++++++++++++++++++++++++++++++++= ++++ 2 files changed, 144 insertions(+), 86 deletions(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysre= g.h index dbb0e8e22cf4..db269eda7c1c 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -216,99 +216,18 @@ #define SYS_PAR_EL1_FST GENMASK(6, 1) =20 /*** Statistical Profiling Extension ***/ -/* ID registers */ -#define SYS_PMSIDR_EL1 sys_reg(3, 0, 9, 9, 7) -#define PMSIDR_EL1_FE_SHIFT 0 -#define PMSIDR_EL1_FT_SHIFT 1 -#define PMSIDR_EL1_FL_SHIFT 2 -#define PMSIDR_EL1_ARCHINST_SHIFT 3 -#define PMSIDR_EL1_LDS_SHIFT 4 -#define PMSIDR_EL1_ERND_SHIFT 5 -#define PMSIDR_EL1_INTERVAL_SHIFT 8 -#define PMSIDR_EL1_INTERVAL_MASK GENMASK_ULL(11, 8) -#define PMSIDR_EL1_MAXSIZE_SHIFT 12 -#define PMSIDR_EL1_MAXSIZE_MASK GENMASK_ULL(15, 12) -#define PMSIDR_EL1_COUNTSIZE_SHIFT 16 -#define PMSIDR_EL1_COUNTSIZE_MASK GENMASK_ULL(19, 16) - -#define SYS_PMBIDR_EL1 sys_reg(3, 0, 9, 10, 7) -#define PMBIDR_EL1_ALIGN_SHIFT 0 -#define PMBIDR_EL1_ALIGN_MASK 0xfU -#define PMBIDR_EL1_P_SHIFT 4 -#define PMBIDR_EL1_F_SHIFT 5 - -/* Sampling controls */ -#define SYS_PMSCR_EL1 sys_reg(3, 0, 9, 9, 0) -#define PMSCR_EL1_E0SPE_SHIFT 0 -#define PMSCR_EL1_E1SPE_SHIFT 1 -#define PMSCR_EL1_CX_SHIFT 3 -#define PMSCR_EL1_PA_SHIFT 4 -#define PMSCR_EL1_TS_SHIFT 5 -#define PMSCR_EL1_PCT_SHIFT 6 - -#define SYS_PMSCR_EL2 sys_reg(3, 4, 9, 9, 0) -#define PMSCR_EL2_E0HSPE_SHIFT 0 -#define PMSCR_EL2_E2SPE_SHIFT 1 -#define PMSCR_EL2_CX_SHIFT 3 -#define PMSCR_EL2_PA_SHIFT 4 -#define PMSCR_EL2_TS_SHIFT 5 -#define PMSCR_EL2_PCT_SHIFT 6 - -#define SYS_PMSICR_EL1 sys_reg(3, 0, 9, 9, 2) - -#define SYS_PMSIRR_EL1 sys_reg(3, 0, 9, 9, 3) -#define PMSIRR_EL1_RND_SHIFT 0 -#define PMSIRR_EL1_INTERVAL_SHIFT 8 -#define PMSIRR_EL1_INTERVAL_MASK GENMASK_ULL(31, 8) - -/* Filtering controls */ -#define SYS_PMSNEVFR_EL1 sys_reg(3, 0, 9, 9, 1) - -#define SYS_PMSFCR_EL1 sys_reg(3, 0, 9, 9, 4) -#define PMSFCR_EL1_FE_SHIFT 0 -#define PMSFCR_EL1_FT_SHIFT 1 -#define PMSFCR_EL1_FL_SHIFT 2 -#define PMSFCR_EL1_B_SHIFT 16 -#define PMSFCR_EL1_LD_SHIFT 17 -#define PMSFCR_EL1_ST_SHIFT 18 - -#define SYS_PMSEVFR_EL1 sys_reg(3, 0, 9, 9, 5) #define PMSEVFR_EL1_RES0_IMP \ (GENMASK_ULL(47, 32) | GENMASK_ULL(23, 16) | GENMASK_ULL(11, 8) |\ BIT_ULL(6) | BIT_ULL(4) | BIT_ULL(2) | BIT_ULL(0)) #define PMSEVFR_EL1_RES0_V1P1 \ (PMSEVFR_EL1_RES0_IMP & ~(BIT_ULL(18) | BIT_ULL(17) | BIT_ULL(11))) =20 -#define SYS_PMSLATFR_EL1 sys_reg(3, 0, 9, 9, 6) -#define PMSLATFR_EL1_MINLAT_SHIFT 0 - -/* Buffer controls */ -#define SYS_PMBLIMITR_EL1 sys_reg(3, 0, 9, 10, 0) -#define PMBLIMITR_EL1_E_SHIFT 0 -#define PMBLIMITR_EL1_FM_SHIFT 1 -#define PMBLIMITR_EL1_FM_MASK GENMASK_ULL(2, 1) -#define PMBLIMITR_EL1_FM_STOP_IRQ 0 - -#define SYS_PMBPTR_EL1 sys_reg(3, 0, 9, 10, 1) - /* Buffer error reporting */ -#define SYS_PMBSR_EL1 sys_reg(3, 0, 9, 10, 3) -#define PMBSR_EL1_COLL_SHIFT 16 -#define PMBSR_EL1_S_SHIFT 17 -#define PMBSR_EL1_EA_SHIFT 18 -#define PMBSR_EL1_DL_SHIFT 19 -#define PMBSR_EL1_EC_SHIFT 26 -#define PMBSR_EL1_EC_MASK GENMASK_ULL(31, 26) - -#define PMBSR_EL1_EC_BUF 0x0UL -#define PMBSR_EL1_EC_FAULT_S1 0x24UL -#define PMBSR_EL1_EC_FAULT_S2 0x25UL - -#define PMBSR_EL1_FAULT_FSC_SHIFT 0 -#define PMBSR_EL1_FAULT_FSC_MASK 0x3fUL - -#define PMBSR_EL1_BUF_BSC_SHIFT 0 -#define PMBSR_EL1_BUF_BSC_MASK 0x3fUL +#define PMBSR_EL1_FAULT_FSC_SHIFT PMBSR_EL1_MSS_SHIFT +#define PMBSR_EL1_FAULT_FSC_MASK PMBSR_EL1_MSS_MASK + +#define PMBSR_EL1_BUF_BSC_SHIFT PMBSR_EL1_MSS_SHIFT +#define PMBSR_EL1_BUF_BSC_MASK PMBSR_EL1_MSS_MASK =20 #define PMBSR_EL1_BUF_BSC_FULL 0x1UL =20 diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 184e58fd5631..c323833cf235 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -1618,6 +1618,130 @@ Sysreg FAR_EL1 3 0 6 0 0 Field 63:0 ADDR EndSysreg =20 +Sysreg PMSCR_EL1 3 0 9 9 0 +Res0 63:8 +Field 7:6 PCT +Field 5 TS +Field 4 PA +Field 3 CX +Res0 2 +Field 1 E1SPE +Field 0 E0SPE +EndSysreg + +Sysreg PMSNEVFR_EL1 3 0 9 9 1 +Field 63:0 E +EndSysreg + +Sysreg PMSICR_EL1 3 0 9 9 2 +Field 63:56 ECOUNT +Res0 55:32 +Field 31:0 COUNT +EndSysreg + +Sysreg PMSIRR_EL1 3 0 9 9 3 +Res0 63:32 +Field 31:8 INTERVAL +Res0 7:1 +Field 0 RND +EndSysreg + +Sysreg PMSFCR_EL1 3 0 9 9 4 +Res0 63:19 +Field 18 ST +Field 17 LD +Field 16 B +Res0 15:4 +Field 3 FnE +Field 2 FL +Field 1 FT +Field 0 FE +EndSysreg + +Sysreg PMSEVFR_EL1 3 0 9 9 5 +Field 63:0 E +EndSysreg + +Sysreg PMSLATFR_EL1 3 0 9 9 6 +Res0 63:16 +Field 15:0 MINLAT +EndSysreg + +Sysreg PMSIDR_EL1 3 0 9 9 7 +Res0 63:25 +Field 24 PBT +Field 23:20 FORMAT +Enum 19:16 COUNTSIZE + 0b0010 12_BIT_SAT + 0b0011 16_BIT_SAT +EndEnum +Field 15:12 MAXSIZE +Enum 11:8 INTERVAL + 0b0000 256 + 0b0010 512 + 0b0011 768 + 0b0100 1024 + 0b0101 1536 + 0b0110 2048 + 0b0111 3072 + 0b1000 4096 +EndEnum +Res0 7 +Field 6 FnE +Field 5 ERND +Field 4 LDS +Field 3 ARCHINST +Field 2 FL +Field 1 FT +Field 0 FE +EndSysreg + +Sysreg PMBLIMITR_EL1 3 0 9 10 0 +Field 63:12 LIMIT +Res0 11:6 +Field 5 PMFZ +Res0 4:3 +Enum 2:1 FM + 0b00 FILL + 0b10 DISCARD +EndEnum +Field 0 E +EndSysreg + +Sysreg PMBPTR_EL1 3 0 9 10 1 +Field 63:0 PTR +EndSysreg + +Sysreg PMBSR_EL1 3 0 9 10 3 +Res0 63:32 +Enum 31:26 EC + 0b000000 BUF + 0b100100 FAULT_S1 + 0b100101 FAULT_S2 + 0b011110 FAULT_GPC + 0b011111 IMP_DEF +EndEnum +Res0 25:20 +Field 19 DL +Field 18 EA +Field 17 S +Field 16 COLL +Field 15:0 MSS +EndSysreg + +Sysreg PMBIDR_EL1 3 0 9 10 7 +Res0 63:12 +Enum 11:8 EA + 0b0000 NotDescribed + 0b0001 Ignored + 0b0010 SError +EndEnum +Res0 7:6 +Field 5 F +Field 4 P +Field 3:0 ALIGN +EndSysreg + SysregFields CONTEXTIDR_ELx Res0 63:32 Field 31:0 PROCID @@ -1772,6 +1896,21 @@ Sysreg FAR_EL2 3 4 6 0 0 Field 63:0 ADDR EndSysreg =20 +Sysreg PMSCR_EL2 3 4 9 9 0 +Res0 63:8 +Enum 7:6 PCT + 0b00 VIRT + 0b01 PHYS + 0b11 GUEST +EndEnum +Field 5 TS +Field 4 PA +Field 3 CX +Res0 2 +Field 1 E2SPE +Field 0 E0HSPE +EndSysreg + Sysreg CONTEXTIDR_EL2 3 4 13 0 1 Fields CONTEXTIDR_ELx EndSysreg --=20 2.39.0 From nobody Mon Sep 15 21:41:12 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 44267C6379F for ; Mon, 9 Jan 2023 19:27:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237560AbjAIT1L (ORCPT ); Mon, 9 Jan 2023 14:27:11 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60204 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236723AbjAIT0t (ORCPT ); Mon, 9 Jan 2023 14:26:49 -0500 Received: from mail-oa1-f54.google.com (mail-oa1-f54.google.com [209.85.160.54]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ECD6168CBC; Mon, 9 Jan 2023 11:26:42 -0800 (PST) Received: by mail-oa1-f54.google.com with SMTP id 586e51a60fabf-1442977d77dso9766470fac.6; Mon, 09 Jan 2023 11:26:42 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=nIEFLVDkrRSYz/D85RzV0VQ4yGgXLXTVgjseKcKrqDE=; b=MW/6eo3LvbQ788XZHqjeozxIGlVG5oAGM5heNWRjoAEkan7GviNhJDpHq/l5GUAwQz r+Q+hpG9A1KZrJi0fIJTCUpFmevx1oThm8/k9N1E6qHidRRRq9d93m2/xG8P8qdQYN1h 8N307SswBMuG7Xs1CsD+x8tA8qDsNJ+40C22aPuac6SUog1OTN6Pn+IqfYIOgO+oKReW CSkDCLAAeuvosZe3bEHOeGRzWg48eBLB9fUsGsjGrLvtI43Cj7yA5LLMQiI/7UsTnVLT ttEugmsn8J0UtSJ42qos0q0TUgxZNspJhZIE/ClIQhMJXbnxzj6H0Wh3qyLgk3tADUMp RH/w== X-Gm-Message-State: AFqh2krtN3tP6znskjivnC10KNXAQ5n66MOlpYjBe9jmX3k8crSqdNLm K3BlBPAswKZVlmV2xyoygjwSUcHVDg== X-Google-Smtp-Source: AMrXdXsuhb3EkL3xw2//KhrxC3sW3AKGR5a41SfejUUBvA7igUzQ4ra+3iLCyUyxbsBdXNCWzdRh6g== X-Received: by 2002:a05:6870:ac1f:b0:148:429:227d with SMTP id kw31-20020a056870ac1f00b001480429227dmr35616324oab.40.1673292401714; Mon, 09 Jan 2023 11:26:41 -0800 (PST) Received: from robh_at_kernel.org (66-90-144-107.dyn.grandenetworks.net. [66.90.144.107]) by smtp.gmail.com with ESMTPSA id bd13-20020a056870d78d00b0014fe4867dc7sm4544364oab.56.2023.01.09.11.26.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Jan 2023 11:26:41 -0800 (PST) Received: (nullmailer pid 1483612 invoked by uid 1000); Mon, 09 Jan 2023 19:26:31 -0000 From: Rob Herring Date: Mon, 09 Jan 2023 13:26:20 -0600 Subject: [PATCH v4 4/8] perf: arm_spe: Drop BIT() and use FIELD_GET/PREP accessors MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20220825-arm-spe-v8-7-v4-4-327f860daf28@kernel.org> References: <20220825-arm-spe-v8-7-v4-0-327f860daf28@kernel.org> In-Reply-To: <20220825-arm-spe-v8-7-v4-0-327f860daf28@kernel.org> To: Peter Zijlstra , Will Deacon , Mark Rutland , Catalin Marinas , Marc Zyngier , James Morse , Alexandru Elisei , Suzuki K Poulose , Oliver Upton , Ingo Molnar , Arnaldo Carvalho de Melo , Alexander Shishkin , Jiri Olsa , Namhyung Kim Cc: Mark Brown , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-perf-users@vger.kernel.org, James Clark X-Mailer: b4 0.12-dev Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Now that generated sysregs are in place, update the register field accesses. The use of BIT() is no longer needed with the new defines. Use FIELD_GET and FIELD_PREP instead of open coding masking and shifting. No functional change. Tested-by: James Clark Signed-off-by: Rob Herring Reviewed-by: Anshuman Khandual --- v4: - Rebase on v6.2-rc1 v3: - no change --- drivers/perf/arm_spe_pmu.c | 70 ++++++++++++++++++++++--------------------= ---- 1 file changed, 34 insertions(+), 36 deletions(-) diff --git a/drivers/perf/arm_spe_pmu.c b/drivers/perf/arm_spe_pmu.c index 814ed18346b6..9b4bd72087ea 100644 --- a/drivers/perf/arm_spe_pmu.c +++ b/drivers/perf/arm_spe_pmu.c @@ -283,18 +283,18 @@ static u64 arm_spe_event_to_pmscr(struct perf_event *= event) struct perf_event_attr *attr =3D &event->attr; u64 reg =3D 0; =20 - reg |=3D ATTR_CFG_GET_FLD(attr, ts_enable) << PMSCR_EL1_TS_SHIFT; - reg |=3D ATTR_CFG_GET_FLD(attr, pa_enable) << PMSCR_EL1_PA_SHIFT; - reg |=3D ATTR_CFG_GET_FLD(attr, pct_enable) << PMSCR_EL1_PCT_SHIFT; + reg |=3D FIELD_PREP(PMSCR_EL1_TS, ATTR_CFG_GET_FLD(attr, ts_enable)); + reg |=3D FIELD_PREP(PMSCR_EL1_PA, ATTR_CFG_GET_FLD(attr, pa_enable)); + reg |=3D FIELD_PREP(PMSCR_EL1_PCT, ATTR_CFG_GET_FLD(attr, pct_enable)); =20 if (!attr->exclude_user) - reg |=3D BIT(PMSCR_EL1_E0SPE_SHIFT); + reg |=3D PMSCR_EL1_E0SPE; =20 if (!attr->exclude_kernel) - reg |=3D BIT(PMSCR_EL1_E1SPE_SHIFT); + reg |=3D PMSCR_EL1_E1SPE; =20 if (get_spe_event_has_cx(event)) - reg |=3D BIT(PMSCR_EL1_CX_SHIFT); + reg |=3D PMSCR_EL1_CX; =20 return reg; } @@ -322,7 +322,7 @@ static u64 arm_spe_event_to_pmsirr(struct perf_event *e= vent) =20 arm_spe_event_sanitise_period(event); =20 - reg |=3D ATTR_CFG_GET_FLD(attr, jitter) << PMSIRR_EL1_RND_SHIFT; + reg |=3D FIELD_PREP(PMSIRR_EL1_RND, ATTR_CFG_GET_FLD(attr, jitter)); reg |=3D event->hw.sample_period; =20 return reg; @@ -333,18 +333,18 @@ static u64 arm_spe_event_to_pmsfcr(struct perf_event = *event) struct perf_event_attr *attr =3D &event->attr; u64 reg =3D 0; =20 - reg |=3D ATTR_CFG_GET_FLD(attr, load_filter) << PMSFCR_EL1_LD_SHIFT; - reg |=3D ATTR_CFG_GET_FLD(attr, store_filter) << PMSFCR_EL1_ST_SHIFT; - reg |=3D ATTR_CFG_GET_FLD(attr, branch_filter) << PMSFCR_EL1_B_SHIFT; + reg |=3D FIELD_PREP(PMSFCR_EL1_LD, ATTR_CFG_GET_FLD(attr, load_filter)); + reg |=3D FIELD_PREP(PMSFCR_EL1_ST, ATTR_CFG_GET_FLD(attr, store_filter)); + reg |=3D FIELD_PREP(PMSFCR_EL1_B, ATTR_CFG_GET_FLD(attr, branch_filter)); =20 if (reg) - reg |=3D BIT(PMSFCR_EL1_FT_SHIFT); + reg |=3D PMSFCR_EL1_FT; =20 if (ATTR_CFG_GET_FLD(attr, event_filter)) - reg |=3D BIT(PMSFCR_EL1_FE_SHIFT); + reg |=3D PMSFCR_EL1_FE; =20 if (ATTR_CFG_GET_FLD(attr, min_latency)) - reg |=3D BIT(PMSFCR_EL1_FL_SHIFT); + reg |=3D PMSFCR_EL1_FL; =20 return reg; } @@ -358,8 +358,7 @@ static u64 arm_spe_event_to_pmsevfr(struct perf_event *= event) static u64 arm_spe_event_to_pmslatfr(struct perf_event *event) { struct perf_event_attr *attr =3D &event->attr; - return ATTR_CFG_GET_FLD(attr, min_latency) - << PMSLATFR_EL1_MINLAT_SHIFT; + return FIELD_PREP(PMSLATFR_EL1_MINLAT, ATTR_CFG_GET_FLD(attr, min_latency= )); } =20 static void arm_spe_pmu_pad_buf(struct perf_output_handle *handle, int len) @@ -511,7 +510,7 @@ static void arm_spe_perf_aux_output_begin(struct perf_o= utput_handle *handle, limit =3D buf->snapshot ? arm_spe_pmu_next_snapshot_off(handle) : arm_spe_pmu_next_off(handle); if (limit) - limit |=3D BIT(PMBLIMITR_EL1_E_SHIFT); + limit |=3D PMBLIMITR_EL1_E; =20 limit +=3D (u64)buf->base; base =3D (u64)buf->base + PERF_IDX2OFF(handle->head, buf); @@ -570,23 +569,23 @@ arm_spe_pmu_buf_get_fault_act(struct perf_output_hand= le *handle) =20 /* Service required? */ pmbsr =3D read_sysreg_s(SYS_PMBSR_EL1); - if (!(pmbsr & BIT(PMBSR_EL1_S_SHIFT))) + if (!FIELD_GET(PMBSR_EL1_S, pmbsr)) return SPE_PMU_BUF_FAULT_ACT_SPURIOUS; =20 /* * If we've lost data, disable profiling and also set the PARTIAL * flag to indicate that the last record is corrupted. */ - if (pmbsr & BIT(PMBSR_EL1_DL_SHIFT)) + if (FIELD_GET(PMBSR_EL1_DL, pmbsr)) perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED | PERF_AUX_FLAG_PARTIAL); =20 /* Report collisions to userspace so that it can up the period */ - if (pmbsr & BIT(PMBSR_EL1_COLL_SHIFT)) + if (FIELD_GET(PMBSR_EL1_COLL, pmbsr)) perf_aux_output_flag(handle, PERF_AUX_FLAG_COLLISION); =20 /* We only expect buffer management events */ - switch (FIELD_GET(PMBSR_EL1_EC_MASK, pmbsr)) { + switch (FIELD_GET(PMBSR_EL1_EC, pmbsr)) { case PMBSR_EL1_EC_BUF: /* Handled below */ break; @@ -716,23 +715,22 @@ static int arm_spe_pmu_event_init(struct perf_event *= event) return -EINVAL; =20 reg =3D arm_spe_event_to_pmsfcr(event); - if ((reg & BIT(PMSFCR_EL1_FE_SHIFT)) && + if ((FIELD_GET(PMSFCR_EL1_FE, reg)) && !(spe_pmu->features & SPE_PMU_FEAT_FILT_EVT)) return -EOPNOTSUPP; =20 - if ((reg & BIT(PMSFCR_EL1_FT_SHIFT)) && + if ((FIELD_GET(PMSFCR_EL1_FT, reg)) && !(spe_pmu->features & SPE_PMU_FEAT_FILT_TYP)) return -EOPNOTSUPP; =20 - if ((reg & BIT(PMSFCR_EL1_FL_SHIFT)) && + if ((FIELD_GET(PMSFCR_EL1_FL, reg)) && !(spe_pmu->features & SPE_PMU_FEAT_FILT_LAT)) return -EOPNOTSUPP; =20 set_spe_event_has_cx(event); reg =3D arm_spe_event_to_pmscr(event); if (!perfmon_capable() && - (reg & (BIT(PMSCR_EL1_PA_SHIFT) | - BIT(PMSCR_EL1_PCT_SHIFT)))) + (reg & (PMSCR_EL1_PA | PMSCR_EL1_PCT))) return -EACCES; =20 return 0; @@ -970,14 +968,14 @@ static void __arm_spe_pmu_dev_probe(void *info) =20 /* Read PMBIDR first to determine whether or not we have access */ reg =3D read_sysreg_s(SYS_PMBIDR_EL1); - if (reg & BIT(PMBIDR_EL1_P_SHIFT)) { + if (FIELD_GET(PMBIDR_EL1_P, reg)) { dev_err(dev, "profiling buffer owned by higher exception level\n"); return; } =20 /* Minimum alignment. If it's out-of-range, then fail the probe */ - fld =3D (reg & PMBIDR_EL1_ALIGN_MASK) >> PMBIDR_EL1_ALIGN_SHIFT; + fld =3D FIELD_GET(PMBIDR_EL1_ALIGN, reg); spe_pmu->align =3D 1 << fld; if (spe_pmu->align > SZ_2K) { dev_err(dev, "unsupported PMBIDR.Align [%d] on CPU %d\n", @@ -987,26 +985,26 @@ static void __arm_spe_pmu_dev_probe(void *info) =20 /* It's now safe to read PMSIDR and figure out what we've got */ reg =3D read_sysreg_s(SYS_PMSIDR_EL1); - if (reg & BIT(PMSIDR_EL1_FE_SHIFT)) + if (FIELD_GET(PMSIDR_EL1_FE, reg)) spe_pmu->features |=3D SPE_PMU_FEAT_FILT_EVT; =20 - if (reg & BIT(PMSIDR_EL1_FT_SHIFT)) + if (FIELD_GET(PMSIDR_EL1_FT, reg)) spe_pmu->features |=3D SPE_PMU_FEAT_FILT_TYP; =20 - if (reg & BIT(PMSIDR_EL1_FL_SHIFT)) + if (FIELD_GET(PMSIDR_EL1_FL, reg)) spe_pmu->features |=3D SPE_PMU_FEAT_FILT_LAT; =20 - if (reg & BIT(PMSIDR_EL1_ARCHINST_SHIFT)) + if (FIELD_GET(PMSIDR_EL1_ARCHINST, reg)) spe_pmu->features |=3D SPE_PMU_FEAT_ARCH_INST; =20 - if (reg & BIT(PMSIDR_EL1_LDS_SHIFT)) + if (FIELD_GET(PMSIDR_EL1_LDS, reg)) spe_pmu->features |=3D SPE_PMU_FEAT_LDS; =20 - if (reg & BIT(PMSIDR_EL1_ERND_SHIFT)) + if (FIELD_GET(PMSIDR_EL1_ERND, reg)) spe_pmu->features |=3D SPE_PMU_FEAT_ERND; =20 /* This field has a spaced out encoding, so just use a look-up */ - fld =3D (reg & PMSIDR_EL1_INTERVAL_MASK) >> PMSIDR_EL1_INTERVAL_SHIFT; + fld =3D FIELD_GET(PMSIDR_EL1_INTERVAL, reg); switch (fld) { case 0: spe_pmu->min_period =3D 256; @@ -1038,7 +1036,7 @@ static void __arm_spe_pmu_dev_probe(void *info) } =20 /* Maximum record size. If it's out-of-range, then fail the probe */ - fld =3D (reg & PMSIDR_EL1_MAXSIZE_MASK) >> PMSIDR_EL1_MAXSIZE_SHIFT; + fld =3D FIELD_GET(PMSIDR_EL1_MAXSIZE, reg); spe_pmu->max_record_sz =3D 1 << fld; if (spe_pmu->max_record_sz > SZ_2K || spe_pmu->max_record_sz < 16) { dev_err(dev, "unsupported PMSIDR_EL1.MaxSize [%d] on CPU %d\n", @@ -1046,7 +1044,7 @@ static void __arm_spe_pmu_dev_probe(void *info) return; } =20 - fld =3D (reg & PMSIDR_EL1_COUNTSIZE_MASK) >> PMSIDR_EL1_COUNTSIZE_SHIFT; + fld =3D FIELD_GET(PMSIDR_EL1_COUNTSIZE, reg); switch (fld) { default: dev_warn(dev, "unknown PMSIDR_EL1.CountSize [%d]; assuming 2\n", --=20 2.39.0 From nobody Mon Sep 15 21:41:12 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 15B2AC54EBD for ; Mon, 9 Jan 2023 19:26:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237386AbjAIT0l (ORCPT ); Mon, 9 Jan 2023 14:26:41 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60070 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235149AbjAIT0h (ORCPT ); Mon, 9 Jan 2023 14:26:37 -0500 Received: from mail-oo1-f53.google.com (mail-oo1-f53.google.com [209.85.161.53]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8996B41677; Mon, 9 Jan 2023 11:26:36 -0800 (PST) Received: by mail-oo1-f53.google.com with SMTP id d2-20020a4ab202000000b004ae3035538bso2670723ooo.12; Mon, 09 Jan 2023 11:26:36 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ZHSlQOy0DTb5kpZ2VrRAyIMZfdxCwZTHcJtASnW13Hw=; b=Asn68QyM6lYSWAJb5xdbEAYQQi13DwUKGN8RhkUntZt3sWNwuj9HjCWG6QqKaOgxsg 5JCa/x9IQxgCDFiJgX5qbzlXNVXmJFYB1et/YZktEdbHrvE6BSZpWVhPOFjwO2TPQh2E tSTsTPpHL/VNH/Uvd/8TLGHr2i1/lSgDWGNCTqzvUr7mFCikiZKElV8XUXCK2Kdbb5hy oAdg203S+DCo9AqsNDs6JEEtMaw5zkNAziJbAevkJwldvOmVSXxlqjjvHtYUwjhf96Nj QQc2AeKvzS0mV3/isKtkHPds7oLNeb1ArHLVWcKXMlnj2kuWyVpZyDS8OUjznf03DIqR ARvw== X-Gm-Message-State: AFqh2kqtp8UU4q8L+KQxBXB2Ug2ilyHNqZ9Rb4rY+W64DLKruvMN8Dqh WceqL8UXcB+qRZYp0pUDsnsAK7WumQ== X-Google-Smtp-Source: AMrXdXslv2cqi91atU/B1PN1NvgkNq9E8RL7xl+DfP3jhUzhvSFMQFy52Ps3fK8W50Elu43MF7MA+A== X-Received: by 2002:a4a:e383:0:b0:4f1:e731:3ee3 with SMTP id l3-20020a4ae383000000b004f1e7313ee3mr4328955oov.2.1673292395567; Mon, 09 Jan 2023 11:26:35 -0800 (PST) Received: from robh_at_kernel.org (66-90-144-107.dyn.grandenetworks.net. [66.90.144.107]) by smtp.gmail.com with ESMTPSA id p2-20020a4ab382000000b004d8c6815287sm4542966ooo.17.2023.01.09.11.26.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Jan 2023 11:26:35 -0800 (PST) Received: (nullmailer pid 1483614 invoked by uid 1000); Mon, 09 Jan 2023 19:26:31 -0000 From: Rob Herring Date: Mon, 09 Jan 2023 13:26:21 -0600 Subject: [PATCH v4 5/8] perf: arm_spe: Use new PMSIDR_EL1 register enums MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20220825-arm-spe-v8-7-v4-5-327f860daf28@kernel.org> References: <20220825-arm-spe-v8-7-v4-0-327f860daf28@kernel.org> In-Reply-To: <20220825-arm-spe-v8-7-v4-0-327f860daf28@kernel.org> To: Peter Zijlstra , Will Deacon , Mark Rutland , Catalin Marinas , Marc Zyngier , James Morse , Alexandru Elisei , Suzuki K Poulose , Oliver Upton , Ingo Molnar , Arnaldo Carvalho de Melo , Alexander Shishkin , Jiri Olsa , Namhyung Kim Cc: Mark Brown , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-perf-users@vger.kernel.org, James Clark X-Mailer: b4 0.12-dev Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Now that the SPE register definitions include enums for some PMSIDR_EL1 fields, use them in the driver in place of magic values. Signed-off-by: Rob Herring Reviewed-by: Anshuman Khandual --- v4: - Rebase on v6.2-rc1 v3: New patch --- drivers/perf/arm_spe_pmu.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/perf/arm_spe_pmu.c b/drivers/perf/arm_spe_pmu.c index 9b4bd72087ea..af6d3867c3e7 100644 --- a/drivers/perf/arm_spe_pmu.c +++ b/drivers/perf/arm_spe_pmu.c @@ -1006,32 +1006,32 @@ static void __arm_spe_pmu_dev_probe(void *info) /* This field has a spaced out encoding, so just use a look-up */ fld =3D FIELD_GET(PMSIDR_EL1_INTERVAL, reg); switch (fld) { - case 0: + case PMSIDR_EL1_INTERVAL_256: spe_pmu->min_period =3D 256; break; - case 2: + case PMSIDR_EL1_INTERVAL_512: spe_pmu->min_period =3D 512; break; - case 3: + case PMSIDR_EL1_INTERVAL_768: spe_pmu->min_period =3D 768; break; - case 4: + case PMSIDR_EL1_INTERVAL_1024: spe_pmu->min_period =3D 1024; break; - case 5: + case PMSIDR_EL1_INTERVAL_1536: spe_pmu->min_period =3D 1536; break; - case 6: + case PMSIDR_EL1_INTERVAL_2048: spe_pmu->min_period =3D 2048; break; - case 7: + case PMSIDR_EL1_INTERVAL_3072: spe_pmu->min_period =3D 3072; break; default: dev_warn(dev, "unknown PMSIDR_EL1.Interval [%d]; assuming 8\n", fld); fallthrough; - case 8: + case PMSIDR_EL1_INTERVAL_4096: spe_pmu->min_period =3D 4096; } =20 @@ -1050,10 +1050,10 @@ static void __arm_spe_pmu_dev_probe(void *info) dev_warn(dev, "unknown PMSIDR_EL1.CountSize [%d]; assuming 2\n", fld); fallthrough; - case 2: + case PMSIDR_EL1_COUNTSIZE_12_BIT_SAT: spe_pmu->counter_sz =3D 12; break; - case 3: + case PMSIDR_EL1_COUNTSIZE_16_BIT_SAT: spe_pmu->counter_sz =3D 16; } =20 --=20 2.39.0 From nobody Mon Sep 15 21:41:12 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 80C31C54EBD for ; Mon, 9 Jan 2023 19:27:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237513AbjAIT1W (ORCPT ); Mon, 9 Jan 2023 14:27:22 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60140 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237260AbjAIT1B (ORCPT ); Mon, 9 Jan 2023 14:27:01 -0500 Received: from mail-oi1-f171.google.com (mail-oi1-f171.google.com [209.85.167.171]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1151F63389; Mon, 9 Jan 2023 11:26:46 -0800 (PST) Received: by mail-oi1-f171.google.com with SMTP id s66so7408095oib.7; Mon, 09 Jan 2023 11:26:46 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jYXNYZPoEZW+cpasaK2qS1x4BldwPdfg2ohHEnkw8tk=; b=kQGO3iEdLoOWs1SkqSU9Cp/VYjVBTvd+VIr8HmRaTSUPZCW5GqMXqKJZUPQJubbR34 jv1L743ZNUo0h61t6euXLvC8+Y6/wrMCthMfZzKBirZ6x/9yK3AOQpsBC8zyORUXVGCU oazwsjOvJCGHhKgKtEMBloVVYj49Ur7ZMmGbQVjrX7G8iTzrHfHl+gtvaEBGgHUj64Vg eL0ItaEvQiSJmJ0zvSTcQvvo1inOqX5INbKbgqBojb6Z6FJw4ghLwdWnICzFzkPFpZO/ pnKLmXlI20mM1bryGAz8whINnJBj/dz5mg96FgHO7KaKFWP9/mGYuDZdluh9NxFjm+z6 LHIg== X-Gm-Message-State: AFqh2kp4p6LtxSWvNI+ktJtLFPVGf9kp9gXLGJTZuTDz91ZMdyWd7Gqf 4aNuFry6JlG5vhBVdDsYSWCRgoF3Yg== X-Google-Smtp-Source: AMrXdXuWN6s2Ip6alGnEK9Y77CLyDy7KYWq7dZYuDLZi9RmEcarrAkz9gBXHZpKxv9AwTjYuASRn7g== X-Received: by 2002:a05:6808:190e:b0:35c:b79:8cf8 with SMTP id bf14-20020a056808190e00b0035c0b798cf8mr38989203oib.6.1673292405102; Mon, 09 Jan 2023 11:26:45 -0800 (PST) Received: from robh_at_kernel.org (66-90-144-107.dyn.grandenetworks.net. [66.90.144.107]) by smtp.gmail.com with ESMTPSA id bg31-20020a056808179f00b00363b5a6bc9esm4343635oib.12.2023.01.09.11.26.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Jan 2023 11:26:44 -0800 (PST) Received: (nullmailer pid 1483616 invoked by uid 1000); Mon, 09 Jan 2023 19:26:31 -0000 From: Rob Herring Date: Mon, 09 Jan 2023 13:26:22 -0600 Subject: [PATCH v4 6/8] perf: arm_spe: Support new SPEv1.2/v8.7 'not taken' event MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20220825-arm-spe-v8-7-v4-6-327f860daf28@kernel.org> References: <20220825-arm-spe-v8-7-v4-0-327f860daf28@kernel.org> In-Reply-To: <20220825-arm-spe-v8-7-v4-0-327f860daf28@kernel.org> To: Peter Zijlstra , Will Deacon , Mark Rutland , Catalin Marinas , Marc Zyngier , James Morse , Alexandru Elisei , Suzuki K Poulose , Oliver Upton , Ingo Molnar , Arnaldo Carvalho de Melo , Alexander Shishkin , Jiri Olsa , Namhyung Kim Cc: Mark Brown , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-perf-users@vger.kernel.org, James Clark X-Mailer: b4 0.12-dev Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Arm SPEv1.2 (Armv8.7/v9.2) adds a new event, 'not taken', in bit 6 of the PMSEVFR_EL1 register. Update arm_spe_pmsevfr_res0() to support the additional event. Tested-by: James Clark Signed-off-by: Rob Herring Reviewed-by: Anshuman Khandual --- v4: - Rebase on v6.2-rc1 v3: - No change v2: - Update for v6.1 sysreg generated header changes --- arch/arm64/include/asm/sysreg.h | 2 ++ drivers/perf/arm_spe_pmu.c | 4 +++- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysre= g.h index db269eda7c1c..fc8787727792 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -221,6 +221,8 @@ BIT_ULL(6) | BIT_ULL(4) | BIT_ULL(2) | BIT_ULL(0)) #define PMSEVFR_EL1_RES0_V1P1 \ (PMSEVFR_EL1_RES0_IMP & ~(BIT_ULL(18) | BIT_ULL(17) | BIT_ULL(11))) +#define PMSEVFR_EL1_RES0_V1P2 \ + (PMSEVFR_EL1_RES0_V1P1 & ~BIT_ULL(6)) =20 /* Buffer error reporting */ #define PMBSR_EL1_FAULT_FSC_SHIFT PMBSR_EL1_MSS_SHIFT diff --git a/drivers/perf/arm_spe_pmu.c b/drivers/perf/arm_spe_pmu.c index af6d3867c3e7..82f67e941bc4 100644 --- a/drivers/perf/arm_spe_pmu.c +++ b/drivers/perf/arm_spe_pmu.c @@ -677,9 +677,11 @@ static u64 arm_spe_pmsevfr_res0(u16 pmsver) case ID_AA64DFR0_EL1_PMSVer_IMP: return PMSEVFR_EL1_RES0_IMP; case ID_AA64DFR0_EL1_PMSVer_V1P1: + return PMSEVFR_EL1_RES0_V1P1; + case ID_AA64DFR0_EL1_PMSVer_V1P2: /* Return the highest version we support in default */ default: - return PMSEVFR_EL1_RES0_V1P1; + return PMSEVFR_EL1_RES0_V1P2; } } =20 --=20 2.39.0 From nobody Mon Sep 15 21:41:12 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D0EACC54EBD for ; Mon, 9 Jan 2023 19:26:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235269AbjAIT0z (ORCPT ); Mon, 9 Jan 2023 14:26:55 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60090 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237306AbjAIT0k (ORCPT ); Mon, 9 Jan 2023 14:26:40 -0500 Received: from mail-ot1-f41.google.com (mail-ot1-f41.google.com [209.85.210.41]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 92CCB61463; Mon, 9 Jan 2023 11:26:39 -0800 (PST) Received: by mail-ot1-f41.google.com with SMTP id k7-20020a056830168700b0067832816190so5742960otr.1; Mon, 09 Jan 2023 11:26:39 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=PhyORF2P/3DyAeuNip+D3UZxHZqFcutPSwK+nSe9q5A=; b=JxKB8FpTCFEXBi12kepmWUjaIOrxOeOBEI4eiQFAWaVc9zGOjGoH1oI/bPc1UR/dSb xqxP73KEZ/RIhLJejWHCh/L80KVc39se93LissDlGwIeDfFmOHo9vFzxBmqH7a9JCtem xdtJNfKFNUfGZgLsDNOwzMyaGXl4+oq9tvqfISliI7fRoesmlGTqALtjQuuq7EfiOF/o F2aBzgGMuPFR36OEmQjH6WXkJSS6N7OTRRivdEFV6bBWb76ZhDWQr3VLYVZ6u/L4ztAy 7BbF4ygElQAQh/V+/FuWdUxnfNAYg97PRuaikIiVddh7DDXczmmIfNo5zOoSRoJKYUdb XV2w== X-Gm-Message-State: AFqh2kp3JRzY+3uPmt/P9oUXqrV/WamoBJLIvei6UTk39sm+l6gwZ4cw mNKQ30lAWkrqj0q4ol4mWvfABl3pIw== X-Google-Smtp-Source: AMrXdXtQakXq+GiEhNJNrTLT/Kt4j9QDhHq5mQPoYNysZKYYdW2im1ldV7iPGFymXGTMKxSydH+yWw== X-Received: by 2002:a9d:68c1:0:b0:66b:cae2:3a3f with SMTP id i1-20020a9d68c1000000b0066bcae23a3fmr32983649oto.17.1673292398563; Mon, 09 Jan 2023 11:26:38 -0800 (PST) Received: from robh_at_kernel.org (66-90-144-107.dyn.grandenetworks.net. [66.90.144.107]) by smtp.gmail.com with ESMTPSA id b19-20020a9d6b93000000b0066ca61230casm4989496otq.8.2023.01.09.11.26.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Jan 2023 11:26:38 -0800 (PST) Received: (nullmailer pid 1483618 invoked by uid 1000); Mon, 09 Jan 2023 19:26:31 -0000 From: Rob Herring Date: Mon, 09 Jan 2023 13:26:23 -0600 Subject: [PATCH v4 7/8] perf: Add perf_event_attr::config3 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20220825-arm-spe-v8-7-v4-7-327f860daf28@kernel.org> References: <20220825-arm-spe-v8-7-v4-0-327f860daf28@kernel.org> In-Reply-To: <20220825-arm-spe-v8-7-v4-0-327f860daf28@kernel.org> To: Peter Zijlstra , Will Deacon , Mark Rutland , Catalin Marinas , Marc Zyngier , James Morse , Alexandru Elisei , Suzuki K Poulose , Oliver Upton , Ingo Molnar , Arnaldo Carvalho de Melo , Alexander Shishkin , Jiri Olsa , Namhyung Kim Cc: Mark Brown , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-perf-users@vger.kernel.org, James Clark X-Mailer: b4 0.12-dev Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Arm SPEv1.2 adds another 64-bits of event filtering control. As the existing perf_event_attr::configN fields are all used up for SPE PMU, an additional field is needed. Add a new 'config3' field. Tested-by: James Clark Signed-off-by: Rob Herring Acked-by: Peter Zijlstra (Intel) --- There's still an unresolved discussion about validating 'config3' with the options laid out here[1]. v4: - Rebase on v6.2-rc1 v3: - No change v2: - Drop tools/ side update [1] https://lore.kernel.org/all/Y49ttrv6W5k3ZNYw@FVFF77S0Q05N.cambridge.arm= .com/ --- include/uapi/linux/perf_event.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/uapi/linux/perf_event.h b/include/uapi/linux/perf_even= t.h index ccb7f5dad59b..37675437b768 100644 --- a/include/uapi/linux/perf_event.h +++ b/include/uapi/linux/perf_event.h @@ -374,6 +374,7 @@ enum perf_event_read_format { #define PERF_ATTR_SIZE_VER5 112 /* add: aux_watermark */ #define PERF_ATTR_SIZE_VER6 120 /* add: aux_sample_size */ #define PERF_ATTR_SIZE_VER7 128 /* add: sig_data */ +#define PERF_ATTR_SIZE_VER8 136 /* add: config3 */ =20 /* * Hardware event_id to monitor via a performance monitoring event: @@ -515,6 +516,8 @@ struct perf_event_attr { * truncated accordingly on 32 bit architectures. */ __u64 sig_data; + + __u64 config3; /* extension of config2 */ }; =20 /* --=20 2.39.0 From nobody Mon Sep 15 21:41:12 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 070C8C61DB3 for ; Mon, 9 Jan 2023 19:27:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237161AbjAIT1S (ORCPT ); Mon, 9 Jan 2023 14:27:18 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60440 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236276AbjAIT1B (ORCPT ); Mon, 9 Jan 2023 14:27:01 -0500 Received: from mail-ot1-f53.google.com (mail-ot1-f53.google.com [209.85.210.53]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 415426C7D6; Mon, 9 Jan 2023 11:26:44 -0800 (PST) Received: by mail-ot1-f53.google.com with SMTP id r6-20020a056830448600b006848a91d910so2179018otv.12; Mon, 09 Jan 2023 11:26:44 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7oliBM7HAbSU/6yu1ELp+aWn2HSSg5QtCBvcjUEG2Hg=; b=hh5RvFTZ9NpKSjfTPVHfgSkC2inLwrgTOxQyaoQxwHUTaeLGrbqUAwTNdH4xyoNt7X HTG8/pLxufdmkRbCYAx9ThNcmmou0Oswzmgw5CqE8fzsiBsadIH1/4j8ti9kTGxP+EuD vfT6Qj2zSuV6gZXxgkjnuzNleFRtEgoECEfMDBaV/SESrpIzQz2755okDNaF9RPB6lwA ZTqkJe5N4cjb+w1jlyq0mJYlI15zQU8fsnUatdy9FyiWGXhqAsiwj5YpFi2uiYi3x2KN hOSEoZVPJJplYw44LXbfKsSPJkqNep3HVx/phVACEdBnh543GRs9mDxTNUQs0jlETdi6 6WsQ== X-Gm-Message-State: AFqh2ko2J3BwDSpGR4DhaRkctpzdf17O9Hl1M/+Vt3XFQyTAvFonvmva VwcGatC5LBZtIheAJdpq0s/3eKwBNA== X-Google-Smtp-Source: AMrXdXsyBANJdogfWegtIJfmOxYF3poHRdanayfI8mR4zu99kaRSXZW5RYFEltFYM0S4UWdISTKdeQ== X-Received: by 2002:a05:6830:55:b0:670:61f7:6457 with SMTP id d21-20020a056830005500b0067061f76457mr33724747otp.29.1673292403307; Mon, 09 Jan 2023 11:26:43 -0800 (PST) Received: from robh_at_kernel.org (66-90-144-107.dyn.grandenetworks.net. [66.90.144.107]) by smtp.gmail.com with ESMTPSA id g99-20020a9d12ec000000b00666a5b5d20fsm4924411otg.32.2023.01.09.11.26.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Jan 2023 11:26:42 -0800 (PST) Received: (nullmailer pid 1483620 invoked by uid 1000); Mon, 09 Jan 2023 19:26:31 -0000 From: Rob Herring Date: Mon, 09 Jan 2023 13:26:24 -0600 Subject: [PATCH v4 8/8] perf: arm_spe: Add support for SPEv1.2 inverted event filtering MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20220825-arm-spe-v8-7-v4-8-327f860daf28@kernel.org> References: <20220825-arm-spe-v8-7-v4-0-327f860daf28@kernel.org> In-Reply-To: <20220825-arm-spe-v8-7-v4-0-327f860daf28@kernel.org> To: Peter Zijlstra , Will Deacon , Mark Rutland , Catalin Marinas , Marc Zyngier , James Morse , Alexandru Elisei , Suzuki K Poulose , Oliver Upton , Ingo Molnar , Arnaldo Carvalho de Melo , Alexander Shishkin , Jiri Olsa , Namhyung Kim Cc: Mark Brown , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-perf-users@vger.kernel.org, James Clark X-Mailer: b4 0.12-dev Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Arm SPEv1.2 (Arm v8.7/v9.2) adds a new feature called Inverted Event Filter which excludes samples matching the event filter. The feature mirrors the existing event filter in PMSEVFR_EL1 adding a new register, PMSNEVFR_EL1, which has the same event bit assignments. Tested-by: James Clark Signed-off-by: Rob Herring --- v4: - Rebase on v6.2-rc1 v3: - No change v2: - Update for auto generated register defines - Avoid accessing SYS_PMSNEVFR_EL1 on < v8.7 --- drivers/perf/arm_spe_pmu.c | 45 ++++++++++++++++++++++++++++++++++++++++++= +++ 1 file changed, 45 insertions(+) diff --git a/drivers/perf/arm_spe_pmu.c b/drivers/perf/arm_spe_pmu.c index 82f67e941bc4..573db4211acd 100644 --- a/drivers/perf/arm_spe_pmu.c +++ b/drivers/perf/arm_spe_pmu.c @@ -85,6 +85,7 @@ struct arm_spe_pmu { #define SPE_PMU_FEAT_ARCH_INST (1UL << 3) #define SPE_PMU_FEAT_LDS (1UL << 4) #define SPE_PMU_FEAT_ERND (1UL << 5) +#define SPE_PMU_FEAT_INV_FILT_EVT (1UL << 6) #define SPE_PMU_FEAT_DEV_PROBED (1UL << 63) u64 features; =20 @@ -202,6 +203,10 @@ static const struct attribute_group arm_spe_pmu_cap_gr= oup =3D { #define ATTR_CFG_FLD_min_latency_LO 0 #define ATTR_CFG_FLD_min_latency_HI 11 =20 +#define ATTR_CFG_FLD_inv_event_filter_CFG config3 /* PMSNEVFR_EL1 */ +#define ATTR_CFG_FLD_inv_event_filter_LO 0 +#define ATTR_CFG_FLD_inv_event_filter_HI 63 + /* Why does everything I do descend into this? */ #define __GEN_PMU_FORMAT_ATTR(cfg, lo, hi) \ (lo) =3D=3D (hi) ? #cfg ":" #lo "\n" : #cfg ":" #lo "-" #hi @@ -232,6 +237,7 @@ GEN_PMU_FORMAT_ATTR(branch_filter); GEN_PMU_FORMAT_ATTR(load_filter); GEN_PMU_FORMAT_ATTR(store_filter); GEN_PMU_FORMAT_ATTR(event_filter); +GEN_PMU_FORMAT_ATTR(inv_event_filter); GEN_PMU_FORMAT_ATTR(min_latency); =20 static struct attribute *arm_spe_pmu_formats_attr[] =3D { @@ -243,12 +249,27 @@ static struct attribute *arm_spe_pmu_formats_attr[] = =3D { &format_attr_load_filter.attr, &format_attr_store_filter.attr, &format_attr_event_filter.attr, + &format_attr_inv_event_filter.attr, &format_attr_min_latency.attr, NULL, }; =20 +static umode_t arm_spe_pmu_format_attr_is_visible(struct kobject *kobj, + struct attribute *attr, + int unused) + { + struct device *dev =3D kobj_to_dev(kobj); + struct arm_spe_pmu *spe_pmu =3D dev_get_drvdata(dev); + + if (attr =3D=3D &format_attr_inv_event_filter.attr && !(spe_pmu->features= & SPE_PMU_FEAT_INV_FILT_EVT)) + return 0; + + return attr->mode; +} + static const struct attribute_group arm_spe_pmu_format_group =3D { .name =3D "format", + .is_visible =3D arm_spe_pmu_format_attr_is_visible, .attrs =3D arm_spe_pmu_formats_attr, }; =20 @@ -343,6 +364,9 @@ static u64 arm_spe_event_to_pmsfcr(struct perf_event *e= vent) if (ATTR_CFG_GET_FLD(attr, event_filter)) reg |=3D PMSFCR_EL1_FE; =20 + if (ATTR_CFG_GET_FLD(attr, inv_event_filter)) + reg |=3D PMSFCR_EL1_FnE; + if (ATTR_CFG_GET_FLD(attr, min_latency)) reg |=3D PMSFCR_EL1_FL; =20 @@ -355,6 +379,12 @@ static u64 arm_spe_event_to_pmsevfr(struct perf_event = *event) return ATTR_CFG_GET_FLD(attr, event_filter); } =20 +static u64 arm_spe_event_to_pmsnevfr(struct perf_event *event) +{ + struct perf_event_attr *attr =3D &event->attr; + return ATTR_CFG_GET_FLD(attr, inv_event_filter); +} + static u64 arm_spe_event_to_pmslatfr(struct perf_event *event) { struct perf_event_attr *attr =3D &event->attr; @@ -703,6 +733,9 @@ static int arm_spe_pmu_event_init(struct perf_event *ev= ent) if (arm_spe_event_to_pmsevfr(event) & arm_spe_pmsevfr_res0(spe_pmu->pmsve= r)) return -EOPNOTSUPP; =20 + if (arm_spe_event_to_pmsnevfr(event) & arm_spe_pmsevfr_res0(spe_pmu->pmsv= er)) + return -EOPNOTSUPP; + if (attr->exclude_idle) return -EOPNOTSUPP; =20 @@ -721,6 +754,10 @@ static int arm_spe_pmu_event_init(struct perf_event *e= vent) !(spe_pmu->features & SPE_PMU_FEAT_FILT_EVT)) return -EOPNOTSUPP; =20 + if ((FIELD_GET(PMSFCR_EL1_FnE, reg)) && + !(spe_pmu->features & SPE_PMU_FEAT_INV_FILT_EVT)) + return -EOPNOTSUPP; + if ((FIELD_GET(PMSFCR_EL1_FT, reg)) && !(spe_pmu->features & SPE_PMU_FEAT_FILT_TYP)) return -EOPNOTSUPP; @@ -756,6 +793,11 @@ static void arm_spe_pmu_start(struct perf_event *event= , int flags) reg =3D arm_spe_event_to_pmsevfr(event); write_sysreg_s(reg, SYS_PMSEVFR_EL1); =20 + if (spe_pmu->features & SPE_PMU_FEAT_INV_FILT_EVT) { + reg =3D arm_spe_event_to_pmsnevfr(event); + write_sysreg_s(reg, SYS_PMSNEVFR_EL1); + } + reg =3D arm_spe_event_to_pmslatfr(event); write_sysreg_s(reg, SYS_PMSLATFR_EL1); =20 @@ -990,6 +1032,9 @@ static void __arm_spe_pmu_dev_probe(void *info) if (FIELD_GET(PMSIDR_EL1_FE, reg)) spe_pmu->features |=3D SPE_PMU_FEAT_FILT_EVT; =20 + if (FIELD_GET(PMSIDR_EL1_FnE, reg)) + spe_pmu->features |=3D SPE_PMU_FEAT_INV_FILT_EVT; + if (FIELD_GET(PMSIDR_EL1_FT, reg)) spe_pmu->features |=3D SPE_PMU_FEAT_FILT_TYP; =20 --=20 2.39.0