From nobody Tue Apr 7 20:29:07 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A391CC433FE for ; Wed, 19 Oct 2022 19:12:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230432AbiJSTMA (ORCPT ); Wed, 19 Oct 2022 15:12:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50196 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230441AbiJSTLh (ORCPT ); Wed, 19 Oct 2022 15:11:37 -0400 Received: from mail-ot1-f50.google.com (mail-ot1-f50.google.com [209.85.210.50]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3BAB11C2F20; Wed, 19 Oct 2022 12:11:34 -0700 (PDT) Received: by mail-ot1-f50.google.com with SMTP id d18-20020a05683025d200b00661c6f1b6a4so10070618otu.1; Wed, 19 Oct 2022 12:11:34 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JxlkIVs552Ejp+aX9wrJgo7YCeTd9sG0ZHnn6ZfglP4=; b=uWT3wBwWtuLmr4ZFpImtSCFfr1YxpJey1dB3KFW3NOUuly34N42oSSmh1I7UNcCj39 laiWiBt2t4prnwhmhwAdEXkq9LgQKviX/1lNX0II98mBkFzE1r8zkHQjRhxGv/l5S+QZ UXcEdFaftsd7nrN+n+cpo4PTlmYPHPJQXNQ8TbuCWWvs5+RAmmPHf1eXn9xyt5vAgBAF EFc6jpOYJlTyHZyIf9ajHMqQJDYtTKE8sKH4ZrntllecgkKe7YfkiDv3pqESVMIAGF6Q gYAeWH4b8vADJ+eHTcc+Kj8zMZ4w100p5PgwF+8nCpsWi8Ln0Bo8fsgAw4AOzbtewADb XQBQ== X-Gm-Message-State: ACrzQf2qyPswqBV2SuoZzSHKNcUSTO5KiNRdWAkw53/Dc/MB8+fmc5h0 AXLjna2eRJcckxBAqK4SFQ== X-Google-Smtp-Source: AMsMyM4c6mVzFUrkq81v9/CA7Mnv6GIXWQ7zeNYDSSDTWnk1r6iqqax4wHful0HevpS2dD/tJHkWSg== X-Received: by 2002:a05:6830:25c3:b0:661:c7e4:e785 with SMTP id d3-20020a05683025c300b00661c7e4e785mr4817162otu.134.1666206692965; Wed, 19 Oct 2022 12:11:32 -0700 (PDT) Received: from robh_at_kernel.org (66-90-144-107.dyn.grandenetworks.net. [66.90.144.107]) by smtp.gmail.com with ESMTPSA id f17-20020a4ae611000000b00480b7efd5d9sm5922591oot.6.2022.10.19.12.11.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Oct 2022 12:11:32 -0700 (PDT) Received: (nullmailer pid 3420898 invoked by uid 1000); Wed, 19 Oct 2022 19:11:25 -0000 From: Rob Herring Date: Wed, 19 Oct 2022 14:11:24 -0500 Subject: [PATCH v2 1/7] perf: arm_spe: Use feature numbering for PMSEVFR_EL1 defines MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20220825-arm-spe-v8-7-v2-1-e37322d68ac0@kernel.org> References: <20220825-arm-spe-v8-7-v2-0-e37322d68ac0@kernel.org> In-Reply-To: <20220825-arm-spe-v8-7-v2-0-e37322d68ac0@kernel.org> To: Namhyung Kim , James Morse , Ingo Molnar , Mark Rutland , Marc Zyngier , Suzuki K Poulose , Will Deacon , Alexandru Elisei , Catalin Marinas , Arnaldo Carvalho de Melo , Peter Zijlstra , Alexander Shishkin , Oliver Upton , Jiri Olsa Cc: kvmarm@lists.cs.columbia.edu, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Brown X-Mailer: b4 0.11.0-dev Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Similar to commit 121a8fc088f1 ("arm64/sysreg: Use feature numbering for PMU and SPE revisions") use feature numbering instead of architecture versions for the PMSEVFR_EL1 Res0 defines. Signed-off-by: Rob Herring --- v2: - New patch --- arch/arm64/include/asm/sysreg.h | 6 +++--- drivers/perf/arm_spe_pmu.c | 4 ++-- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysre= g.h index 7d301700d1a9..9a4cf12e3e16 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -294,11 +294,11 @@ #define SYS_PMSFCR_EL1_ST_SHIFT 18 =20 #define SYS_PMSEVFR_EL1 sys_reg(3, 0, 9, 9, 5) -#define SYS_PMSEVFR_EL1_RES0_8_2 \ +#define PMSEVFR_EL1_RES0_IMP \ (GENMASK_ULL(47, 32) | GENMASK_ULL(23, 16) | GENMASK_ULL(11, 8) |\ BIT_ULL(6) | BIT_ULL(4) | BIT_ULL(2) | BIT_ULL(0)) -#define SYS_PMSEVFR_EL1_RES0_8_3 \ - (SYS_PMSEVFR_EL1_RES0_8_2 & ~(BIT_ULL(18) | BIT_ULL(17) | BIT_ULL(11))) +#define PMSEVFR_EL1_RES0_V1P1 \ + (PMSEVFR_EL1_RES0_IMP & ~(BIT_ULL(18) | BIT_ULL(17) | BIT_ULL(11))) =20 #define SYS_PMSLATFR_EL1 sys_reg(3, 0, 9, 9, 6) #define SYS_PMSLATFR_EL1_MINLAT_SHIFT 0 diff --git a/drivers/perf/arm_spe_pmu.c b/drivers/perf/arm_spe_pmu.c index 00e3a637f7b6..65cf93dcc8ee 100644 --- a/drivers/perf/arm_spe_pmu.c +++ b/drivers/perf/arm_spe_pmu.c @@ -677,11 +677,11 @@ static u64 arm_spe_pmsevfr_res0(u16 pmsver) { switch (pmsver) { case ID_AA64DFR0_EL1_PMSVer_IMP: - return SYS_PMSEVFR_EL1_RES0_8_2; + return PMSEVFR_EL1_RES0_IMP; case ID_AA64DFR0_EL1_PMSVer_V1P1: /* Return the highest version we support in default */ default: - return SYS_PMSEVFR_EL1_RES0_8_3; + return PMSEVFR_EL1_RES0_V1P1; } } =20 --=20 b4 0.11.0-dev From nobody Tue Apr 7 20:29:07 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8061FC433FE for ; Wed, 19 Oct 2022 19:11:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231176AbiJSTLt (ORCPT ); Wed, 19 Oct 2022 15:11:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50088 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229822AbiJSTLd (ORCPT ); Wed, 19 Oct 2022 15:11:33 -0400 Received: from mail-oi1-f181.google.com (mail-oi1-f181.google.com [209.85.167.181]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D71EC1C3E40; Wed, 19 Oct 2022 12:11:27 -0700 (PDT) Received: by mail-oi1-f181.google.com with SMTP id n83so20327483oif.11; Wed, 19 Oct 2022 12:11:27 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=k24AQgKpVvc1442j/biKSQfKpOyhAXCqlqrMvI7oSIc=; b=lSdTBUNcP4HfH6tCPtsLiOlEJVM+2N1F3XCdG1X33lSrWnz1XWRWCQnZ5yRQbYlCiL T14Sa66AW34K1dxLXTVliy8lABDhf95bpE15OXePqtn8jX2OqvmoxUXHq5hF5wmXX0zS atIQSVqLXz2KDH1Pvq4Nehu6+l10XIu3aWGWhOe+7VWZw3ncldJZ0aA9na48hucf5Ndp HYz2rE2lYc9MRh0PEXIw3IHBsuH6+SgGAxtAjdxqMaM7EJ1iWqpaZV3G6PIISDpIZYmv 67DpykUFwn0gKcac+8hsjbbJW1tvA9/nMiZk6jffozhVV+fJkKT8Pefoc16VNbIY7yJA QUWA== X-Gm-Message-State: ACrzQf3yExD/he0arWbHyMPGj5FjD8OD1BMVwhtj+wi+oSUQKXNfGFmo +8XUak1XbrDiZua5AdU1dg== X-Google-Smtp-Source: AMsMyM5iEQk9W6NDNnrbHJ4mHkKH64rMIeE62RrjYLpUDQWfYlXoRtOpZwMbCi9bVuQDgb6WeDIWlA== X-Received: by 2002:a05:6808:14cf:b0:355:5204:dd81 with SMTP id f15-20020a05680814cf00b003555204dd81mr4661375oiw.112.1666206685999; Wed, 19 Oct 2022 12:11:25 -0700 (PDT) Received: from robh_at_kernel.org (66-90-144-107.dyn.grandenetworks.net. [66.90.144.107]) by smtp.gmail.com with ESMTPSA id i9-20020aca2b09000000b00354b1edb60fsm6945231oik.32.2022.10.19.12.11.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Oct 2022 12:11:25 -0700 (PDT) Received: (nullmailer pid 3420900 invoked by uid 1000); Wed, 19 Oct 2022 19:11:25 -0000 From: Rob Herring Date: Wed, 19 Oct 2022 14:11:25 -0500 Subject: [PATCH v2 2/7] arm64: Drop SYS_ from SPE register defines MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20220825-arm-spe-v8-7-v2-2-e37322d68ac0@kernel.org> References: <20220825-arm-spe-v8-7-v2-0-e37322d68ac0@kernel.org> In-Reply-To: <20220825-arm-spe-v8-7-v2-0-e37322d68ac0@kernel.org> To: Namhyung Kim , James Morse , Ingo Molnar , Mark Rutland , Marc Zyngier , Suzuki K Poulose , Will Deacon , Alexandru Elisei , Catalin Marinas , Arnaldo Carvalho de Melo , Peter Zijlstra , Alexander Shishkin , Oliver Upton , Jiri Olsa Cc: kvmarm@lists.cs.columbia.edu, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Brown X-Mailer: b4 0.11.0-dev Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org We currently have a non-standard SYS_ prefix in the constants generated for the SPE register bitfields. Drop this in preparation for automatic register definition generation. The SPE mask defines were unshifted, and the SPE register field enumerations were shifted. The autogenerated defines are the opposite, so make the necessary adjustments. No functional changes. Signed-off-by: Rob Herring --- v2: - New patch --- arch/arm64/include/asm/el2_setup.h | 6 +- arch/arm64/include/asm/sysreg.h | 112 ++++++++++++++++++---------------= ---- arch/arm64/kvm/debug.c | 2 +- arch/arm64/kvm/hyp/nvhe/debug-sr.c | 2 +- drivers/perf/arm_spe_pmu.c | 85 ++++++++++++++-------------- 5 files changed, 103 insertions(+), 104 deletions(-) diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el= 2_setup.h index 668569adf4d3..f9da43e53cdb 100644 --- a/arch/arm64/include/asm/el2_setup.h +++ b/arch/arm64/include/asm/el2_setup.h @@ -53,10 +53,10 @@ cbz x0, .Lskip_spe_\@ // Skip if SPE not present =20 mrs_s x0, SYS_PMBIDR_EL1 // If SPE available at EL2, - and x0, x0, #(1 << SYS_PMBIDR_EL1_P_SHIFT) + and x0, x0, #(1 << PMBIDR_EL1_P_SHIFT) cbnz x0, .Lskip_spe_el2_\@ // then permit sampling of physical - mov x0, #(1 << SYS_PMSCR_EL2_PCT_SHIFT | \ - 1 << SYS_PMSCR_EL2_PA_SHIFT) + mov x0, #(1 << PMSCR_EL2_PCT_SHIFT | \ + 1 << PMSCR_EL2_PA_SHIFT) msr_s SYS_PMSCR_EL2, x0 // addresses and physical counter .Lskip_spe_el2_\@: mov x0, #(MDCR_EL2_E2PB_MASK << MDCR_EL2_E2PB_SHIFT) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysre= g.h index 9a4cf12e3e16..8df8a0a51273 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -239,59 +239,59 @@ /*** Statistical Profiling Extension ***/ /* ID registers */ #define SYS_PMSIDR_EL1 sys_reg(3, 0, 9, 9, 7) -#define SYS_PMSIDR_EL1_FE_SHIFT 0 -#define SYS_PMSIDR_EL1_FT_SHIFT 1 -#define SYS_PMSIDR_EL1_FL_SHIFT 2 -#define SYS_PMSIDR_EL1_ARCHINST_SHIFT 3 -#define SYS_PMSIDR_EL1_LDS_SHIFT 4 -#define SYS_PMSIDR_EL1_ERND_SHIFT 5 -#define SYS_PMSIDR_EL1_INTERVAL_SHIFT 8 -#define SYS_PMSIDR_EL1_INTERVAL_MASK 0xfUL -#define SYS_PMSIDR_EL1_MAXSIZE_SHIFT 12 -#define SYS_PMSIDR_EL1_MAXSIZE_MASK 0xfUL -#define SYS_PMSIDR_EL1_COUNTSIZE_SHIFT 16 -#define SYS_PMSIDR_EL1_COUNTSIZE_MASK 0xfUL +#define PMSIDR_EL1_FE_SHIFT 0 +#define PMSIDR_EL1_FT_SHIFT 1 +#define PMSIDR_EL1_FL_SHIFT 2 +#define PMSIDR_EL1_ARCHINST_SHIFT 3 +#define PMSIDR_EL1_LDS_SHIFT 4 +#define PMSIDR_EL1_ERND_SHIFT 5 +#define PMSIDR_EL1_INTERVAL_SHIFT 8 +#define PMSIDR_EL1_INTERVAL_MASK GENMASK_ULL(11, 8) +#define PMSIDR_EL1_MAXSIZE_SHIFT 12 +#define PMSIDR_EL1_MAXSIZE_MASK GENMASK_ULL(15, 12) +#define PMSIDR_EL1_COUNTSIZE_SHIFT 16 +#define PMSIDR_EL1_COUNTSIZE_MASK GENMASK_ULL(19, 16) =20 #define SYS_PMBIDR_EL1 sys_reg(3, 0, 9, 10, 7) -#define SYS_PMBIDR_EL1_ALIGN_SHIFT 0 -#define SYS_PMBIDR_EL1_ALIGN_MASK 0xfU -#define SYS_PMBIDR_EL1_P_SHIFT 4 -#define SYS_PMBIDR_EL1_F_SHIFT 5 +#define PMBIDR_EL1_ALIGN_SHIFT 0 +#define PMBIDR_EL1_ALIGN_MASK 0xfU +#define PMBIDR_EL1_P_SHIFT 4 +#define PMBIDR_EL1_F_SHIFT 5 =20 /* Sampling controls */ #define SYS_PMSCR_EL1 sys_reg(3, 0, 9, 9, 0) -#define SYS_PMSCR_EL1_E0SPE_SHIFT 0 -#define SYS_PMSCR_EL1_E1SPE_SHIFT 1 -#define SYS_PMSCR_EL1_CX_SHIFT 3 -#define SYS_PMSCR_EL1_PA_SHIFT 4 -#define SYS_PMSCR_EL1_TS_SHIFT 5 -#define SYS_PMSCR_EL1_PCT_SHIFT 6 +#define PMSCR_EL1_E0SPE_SHIFT 0 +#define PMSCR_EL1_E1SPE_SHIFT 1 +#define PMSCR_EL1_CX_SHIFT 3 +#define PMSCR_EL1_PA_SHIFT 4 +#define PMSCR_EL1_TS_SHIFT 5 +#define PMSCR_EL1_PCT_SHIFT 6 =20 #define SYS_PMSCR_EL2 sys_reg(3, 4, 9, 9, 0) -#define SYS_PMSCR_EL2_E0HSPE_SHIFT 0 -#define SYS_PMSCR_EL2_E2SPE_SHIFT 1 -#define SYS_PMSCR_EL2_CX_SHIFT 3 -#define SYS_PMSCR_EL2_PA_SHIFT 4 -#define SYS_PMSCR_EL2_TS_SHIFT 5 -#define SYS_PMSCR_EL2_PCT_SHIFT 6 +#define PMSCR_EL2_E0HSPE_SHIFT 0 +#define PMSCR_EL2_E2SPE_SHIFT 1 +#define PMSCR_EL2_CX_SHIFT 3 +#define PMSCR_EL2_PA_SHIFT 4 +#define PMSCR_EL2_TS_SHIFT 5 +#define PMSCR_EL2_PCT_SHIFT 6 =20 #define SYS_PMSICR_EL1 sys_reg(3, 0, 9, 9, 2) =20 #define SYS_PMSIRR_EL1 sys_reg(3, 0, 9, 9, 3) -#define SYS_PMSIRR_EL1_RND_SHIFT 0 -#define SYS_PMSIRR_EL1_INTERVAL_SHIFT 8 -#define SYS_PMSIRR_EL1_INTERVAL_MASK 0xffffffUL +#define PMSIRR_EL1_RND_SHIFT 0 +#define PMSIRR_EL1_INTERVAL_SHIFT 8 +#define PMSIRR_EL1_INTERVAL_MASK GENMASK_ULL(31, 8) =20 /* Filtering controls */ #define SYS_PMSNEVFR_EL1 sys_reg(3, 0, 9, 9, 1) =20 #define SYS_PMSFCR_EL1 sys_reg(3, 0, 9, 9, 4) -#define SYS_PMSFCR_EL1_FE_SHIFT 0 -#define SYS_PMSFCR_EL1_FT_SHIFT 1 -#define SYS_PMSFCR_EL1_FL_SHIFT 2 -#define SYS_PMSFCR_EL1_B_SHIFT 16 -#define SYS_PMSFCR_EL1_LD_SHIFT 17 -#define SYS_PMSFCR_EL1_ST_SHIFT 18 +#define PMSFCR_EL1_FE_SHIFT 0 +#define PMSFCR_EL1_FT_SHIFT 1 +#define PMSFCR_EL1_FL_SHIFT 2 +#define PMSFCR_EL1_B_SHIFT 16 +#define PMSFCR_EL1_LD_SHIFT 17 +#define PMSFCR_EL1_ST_SHIFT 18 =20 #define SYS_PMSEVFR_EL1 sys_reg(3, 0, 9, 9, 5) #define PMSEVFR_EL1_RES0_IMP \ @@ -301,37 +301,37 @@ (PMSEVFR_EL1_RES0_IMP & ~(BIT_ULL(18) | BIT_ULL(17) | BIT_ULL(11))) =20 #define SYS_PMSLATFR_EL1 sys_reg(3, 0, 9, 9, 6) -#define SYS_PMSLATFR_EL1_MINLAT_SHIFT 0 +#define PMSLATFR_EL1_MINLAT_SHIFT 0 =20 /* Buffer controls */ #define SYS_PMBLIMITR_EL1 sys_reg(3, 0, 9, 10, 0) -#define SYS_PMBLIMITR_EL1_E_SHIFT 0 -#define SYS_PMBLIMITR_EL1_FM_SHIFT 1 -#define SYS_PMBLIMITR_EL1_FM_MASK 0x3UL -#define SYS_PMBLIMITR_EL1_FM_STOP_IRQ (0 << SYS_PMBLIMITR_EL1_FM_SHIFT) +#define PMBLIMITR_EL1_E_SHIFT 0 +#define PMBLIMITR_EL1_FM_SHIFT 1 +#define PMBLIMITR_EL1_FM_MASK GENMASK_ULL(2, 1) +#define PMBLIMITR_EL1_FM_STOP_IRQ 0 =20 #define SYS_PMBPTR_EL1 sys_reg(3, 0, 9, 10, 1) =20 /* Buffer error reporting */ #define SYS_PMBSR_EL1 sys_reg(3, 0, 9, 10, 3) -#define SYS_PMBSR_EL1_COLL_SHIFT 16 -#define SYS_PMBSR_EL1_S_SHIFT 17 -#define SYS_PMBSR_EL1_EA_SHIFT 18 -#define SYS_PMBSR_EL1_DL_SHIFT 19 -#define SYS_PMBSR_EL1_EC_SHIFT 26 -#define SYS_PMBSR_EL1_EC_MASK 0x3fUL +#define PMBSR_EL1_COLL_SHIFT 16 +#define PMBSR_EL1_S_SHIFT 17 +#define PMBSR_EL1_EA_SHIFT 18 +#define PMBSR_EL1_DL_SHIFT 19 +#define PMBSR_EL1_EC_SHIFT 26 +#define PMBSR_EL1_EC_MASK GENMASK_ULL(31, 26) =20 -#define SYS_PMBSR_EL1_EC_BUF (0x0UL << SYS_PMBSR_EL1_EC_SHIFT) -#define SYS_PMBSR_EL1_EC_FAULT_S1 (0x24UL << SYS_PMBSR_EL1_EC_SHIFT) -#define SYS_PMBSR_EL1_EC_FAULT_S2 (0x25UL << SYS_PMBSR_EL1_EC_SHIFT) +#define PMBSR_EL1_EC_BUF 0x0UL +#define PMBSR_EL1_EC_FAULT_S1 0x24UL +#define PMBSR_EL1_EC_FAULT_S2 0x25UL =20 -#define SYS_PMBSR_EL1_FAULT_FSC_SHIFT 0 -#define SYS_PMBSR_EL1_FAULT_FSC_MASK 0x3fUL +#define PMBSR_EL1_FAULT_FSC_SHIFT 0 +#define PMBSR_EL1_FAULT_FSC_MASK 0x3fUL =20 -#define SYS_PMBSR_EL1_BUF_BSC_SHIFT 0 -#define SYS_PMBSR_EL1_BUF_BSC_MASK 0x3fUL +#define PMBSR_EL1_BUF_BSC_SHIFT 0 +#define PMBSR_EL1_BUF_BSC_MASK 0x3fUL =20 -#define SYS_PMBSR_EL1_BUF_BSC_FULL (0x1UL << SYS_PMBSR_EL1_BUF_BSC_SHIFT) +#define PMBSR_EL1_BUF_BSC_FULL 0x1UL =20 /*** End of Statistical Profiling Extension ***/ =20 diff --git a/arch/arm64/kvm/debug.c b/arch/arm64/kvm/debug.c index fccf9ec01813..55f80fb93925 100644 --- a/arch/arm64/kvm/debug.c +++ b/arch/arm64/kvm/debug.c @@ -328,7 +328,7 @@ void kvm_arch_vcpu_load_debug_state_flags(struct kvm_vc= pu *vcpu) * we may need to check if the host state needs to be saved. */ if (cpuid_feature_extract_unsigned_field(dfr0, ID_AA64DFR0_EL1_PMSVer_SHI= FT) && - !(read_sysreg_s(SYS_PMBIDR_EL1) & BIT(SYS_PMBIDR_EL1_P_SHIFT))) + !(read_sysreg_s(SYS_PMBIDR_EL1) & BIT(PMBIDR_EL1_P_SHIFT))) vcpu_set_flag(vcpu, DEBUG_STATE_SAVE_SPE); =20 /* Check if we have TRBE implemented and available at the host */ diff --git a/arch/arm64/kvm/hyp/nvhe/debug-sr.c b/arch/arm64/kvm/hyp/nvhe/d= ebug-sr.c index e17455773b98..2673bde62fad 100644 --- a/arch/arm64/kvm/hyp/nvhe/debug-sr.c +++ b/arch/arm64/kvm/hyp/nvhe/debug-sr.c @@ -27,7 +27,7 @@ static void __debug_save_spe(u64 *pmscr_el1) * Check if the host is actually using it ? */ reg =3D read_sysreg_s(SYS_PMBLIMITR_EL1); - if (!(reg & BIT(SYS_PMBLIMITR_EL1_E_SHIFT))) + if (!(reg & BIT(PMBLIMITR_EL1_E_SHIFT))) return; =20 /* Yes; save the control register and disable data generation */ diff --git a/drivers/perf/arm_spe_pmu.c b/drivers/perf/arm_spe_pmu.c index 65cf93dcc8ee..814ed18346b6 100644 --- a/drivers/perf/arm_spe_pmu.c +++ b/drivers/perf/arm_spe_pmu.c @@ -12,6 +12,7 @@ #define DRVNAME PMUNAME "_pmu" #define pr_fmt(fmt) DRVNAME ": " fmt =20 +#include #include #include #include @@ -282,18 +283,18 @@ static u64 arm_spe_event_to_pmscr(struct perf_event *= event) struct perf_event_attr *attr =3D &event->attr; u64 reg =3D 0; =20 - reg |=3D ATTR_CFG_GET_FLD(attr, ts_enable) << SYS_PMSCR_EL1_TS_SHIFT; - reg |=3D ATTR_CFG_GET_FLD(attr, pa_enable) << SYS_PMSCR_EL1_PA_SHIFT; - reg |=3D ATTR_CFG_GET_FLD(attr, pct_enable) << SYS_PMSCR_EL1_PCT_SHIFT; + reg |=3D ATTR_CFG_GET_FLD(attr, ts_enable) << PMSCR_EL1_TS_SHIFT; + reg |=3D ATTR_CFG_GET_FLD(attr, pa_enable) << PMSCR_EL1_PA_SHIFT; + reg |=3D ATTR_CFG_GET_FLD(attr, pct_enable) << PMSCR_EL1_PCT_SHIFT; =20 if (!attr->exclude_user) - reg |=3D BIT(SYS_PMSCR_EL1_E0SPE_SHIFT); + reg |=3D BIT(PMSCR_EL1_E0SPE_SHIFT); =20 if (!attr->exclude_kernel) - reg |=3D BIT(SYS_PMSCR_EL1_E1SPE_SHIFT); + reg |=3D BIT(PMSCR_EL1_E1SPE_SHIFT); =20 if (get_spe_event_has_cx(event)) - reg |=3D BIT(SYS_PMSCR_EL1_CX_SHIFT); + reg |=3D BIT(PMSCR_EL1_CX_SHIFT); =20 return reg; } @@ -302,8 +303,7 @@ static void arm_spe_event_sanitise_period(struct perf_e= vent *event) { struct arm_spe_pmu *spe_pmu =3D to_spe_pmu(event->pmu); u64 period =3D event->hw.sample_period; - u64 max_period =3D SYS_PMSIRR_EL1_INTERVAL_MASK - << SYS_PMSIRR_EL1_INTERVAL_SHIFT; + u64 max_period =3D PMSIRR_EL1_INTERVAL_MASK; =20 if (period < spe_pmu->min_period) period =3D spe_pmu->min_period; @@ -322,7 +322,7 @@ static u64 arm_spe_event_to_pmsirr(struct perf_event *e= vent) =20 arm_spe_event_sanitise_period(event); =20 - reg |=3D ATTR_CFG_GET_FLD(attr, jitter) << SYS_PMSIRR_EL1_RND_SHIFT; + reg |=3D ATTR_CFG_GET_FLD(attr, jitter) << PMSIRR_EL1_RND_SHIFT; reg |=3D event->hw.sample_period; =20 return reg; @@ -333,18 +333,18 @@ static u64 arm_spe_event_to_pmsfcr(struct perf_event = *event) struct perf_event_attr *attr =3D &event->attr; u64 reg =3D 0; =20 - reg |=3D ATTR_CFG_GET_FLD(attr, load_filter) << SYS_PMSFCR_EL1_LD_SHIFT; - reg |=3D ATTR_CFG_GET_FLD(attr, store_filter) << SYS_PMSFCR_EL1_ST_SHIFT; - reg |=3D ATTR_CFG_GET_FLD(attr, branch_filter) << SYS_PMSFCR_EL1_B_SHIFT; + reg |=3D ATTR_CFG_GET_FLD(attr, load_filter) << PMSFCR_EL1_LD_SHIFT; + reg |=3D ATTR_CFG_GET_FLD(attr, store_filter) << PMSFCR_EL1_ST_SHIFT; + reg |=3D ATTR_CFG_GET_FLD(attr, branch_filter) << PMSFCR_EL1_B_SHIFT; =20 if (reg) - reg |=3D BIT(SYS_PMSFCR_EL1_FT_SHIFT); + reg |=3D BIT(PMSFCR_EL1_FT_SHIFT); =20 if (ATTR_CFG_GET_FLD(attr, event_filter)) - reg |=3D BIT(SYS_PMSFCR_EL1_FE_SHIFT); + reg |=3D BIT(PMSFCR_EL1_FE_SHIFT); =20 if (ATTR_CFG_GET_FLD(attr, min_latency)) - reg |=3D BIT(SYS_PMSFCR_EL1_FL_SHIFT); + reg |=3D BIT(PMSFCR_EL1_FL_SHIFT); =20 return reg; } @@ -359,7 +359,7 @@ static u64 arm_spe_event_to_pmslatfr(struct perf_event = *event) { struct perf_event_attr *attr =3D &event->attr; return ATTR_CFG_GET_FLD(attr, min_latency) - << SYS_PMSLATFR_EL1_MINLAT_SHIFT; + << PMSLATFR_EL1_MINLAT_SHIFT; } =20 static void arm_spe_pmu_pad_buf(struct perf_output_handle *handle, int len) @@ -511,7 +511,7 @@ static void arm_spe_perf_aux_output_begin(struct perf_o= utput_handle *handle, limit =3D buf->snapshot ? arm_spe_pmu_next_snapshot_off(handle) : arm_spe_pmu_next_off(handle); if (limit) - limit |=3D BIT(SYS_PMBLIMITR_EL1_E_SHIFT); + limit |=3D BIT(PMBLIMITR_EL1_E_SHIFT); =20 limit +=3D (u64)buf->base; base =3D (u64)buf->base + PERF_IDX2OFF(handle->head, buf); @@ -570,28 +570,28 @@ arm_spe_pmu_buf_get_fault_act(struct perf_output_hand= le *handle) =20 /* Service required? */ pmbsr =3D read_sysreg_s(SYS_PMBSR_EL1); - if (!(pmbsr & BIT(SYS_PMBSR_EL1_S_SHIFT))) + if (!(pmbsr & BIT(PMBSR_EL1_S_SHIFT))) return SPE_PMU_BUF_FAULT_ACT_SPURIOUS; =20 /* * If we've lost data, disable profiling and also set the PARTIAL * flag to indicate that the last record is corrupted. */ - if (pmbsr & BIT(SYS_PMBSR_EL1_DL_SHIFT)) + if (pmbsr & BIT(PMBSR_EL1_DL_SHIFT)) perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED | PERF_AUX_FLAG_PARTIAL); =20 /* Report collisions to userspace so that it can up the period */ - if (pmbsr & BIT(SYS_PMBSR_EL1_COLL_SHIFT)) + if (pmbsr & BIT(PMBSR_EL1_COLL_SHIFT)) perf_aux_output_flag(handle, PERF_AUX_FLAG_COLLISION); =20 /* We only expect buffer management events */ - switch (pmbsr & (SYS_PMBSR_EL1_EC_MASK << SYS_PMBSR_EL1_EC_SHIFT)) { - case SYS_PMBSR_EL1_EC_BUF: + switch (FIELD_GET(PMBSR_EL1_EC_MASK, pmbsr)) { + case PMBSR_EL1_EC_BUF: /* Handled below */ break; - case SYS_PMBSR_EL1_EC_FAULT_S1: - case SYS_PMBSR_EL1_EC_FAULT_S2: + case PMBSR_EL1_EC_FAULT_S1: + case PMBSR_EL1_EC_FAULT_S2: err_str =3D "Unexpected buffer fault"; goto out_err; default: @@ -600,9 +600,8 @@ arm_spe_pmu_buf_get_fault_act(struct perf_output_handle= *handle) } =20 /* Buffer management event */ - switch (pmbsr & - (SYS_PMBSR_EL1_BUF_BSC_MASK << SYS_PMBSR_EL1_BUF_BSC_SHIFT)) { - case SYS_PMBSR_EL1_BUF_BSC_FULL: + switch (FIELD_GET(PMBSR_EL1_BUF_BSC_MASK, pmbsr)) { + case PMBSR_EL1_BUF_BSC_FULL: ret =3D SPE_PMU_BUF_FAULT_ACT_OK; goto out_stop; default: @@ -717,23 +716,23 @@ static int arm_spe_pmu_event_init(struct perf_event *= event) return -EINVAL; =20 reg =3D arm_spe_event_to_pmsfcr(event); - if ((reg & BIT(SYS_PMSFCR_EL1_FE_SHIFT)) && + if ((reg & BIT(PMSFCR_EL1_FE_SHIFT)) && !(spe_pmu->features & SPE_PMU_FEAT_FILT_EVT)) return -EOPNOTSUPP; =20 - if ((reg & BIT(SYS_PMSFCR_EL1_FT_SHIFT)) && + if ((reg & BIT(PMSFCR_EL1_FT_SHIFT)) && !(spe_pmu->features & SPE_PMU_FEAT_FILT_TYP)) return -EOPNOTSUPP; =20 - if ((reg & BIT(SYS_PMSFCR_EL1_FL_SHIFT)) && + if ((reg & BIT(PMSFCR_EL1_FL_SHIFT)) && !(spe_pmu->features & SPE_PMU_FEAT_FILT_LAT)) return -EOPNOTSUPP; =20 set_spe_event_has_cx(event); reg =3D arm_spe_event_to_pmscr(event); if (!perfmon_capable() && - (reg & (BIT(SYS_PMSCR_EL1_PA_SHIFT) | - BIT(SYS_PMSCR_EL1_PCT_SHIFT)))) + (reg & (BIT(PMSCR_EL1_PA_SHIFT) | + BIT(PMSCR_EL1_PCT_SHIFT)))) return -EACCES; =20 return 0; @@ -971,14 +970,14 @@ static void __arm_spe_pmu_dev_probe(void *info) =20 /* Read PMBIDR first to determine whether or not we have access */ reg =3D read_sysreg_s(SYS_PMBIDR_EL1); - if (reg & BIT(SYS_PMBIDR_EL1_P_SHIFT)) { + if (reg & BIT(PMBIDR_EL1_P_SHIFT)) { dev_err(dev, "profiling buffer owned by higher exception level\n"); return; } =20 /* Minimum alignment. If it's out-of-range, then fail the probe */ - fld =3D reg >> SYS_PMBIDR_EL1_ALIGN_SHIFT & SYS_PMBIDR_EL1_ALIGN_MASK; + fld =3D (reg & PMBIDR_EL1_ALIGN_MASK) >> PMBIDR_EL1_ALIGN_SHIFT; spe_pmu->align =3D 1 << fld; if (spe_pmu->align > SZ_2K) { dev_err(dev, "unsupported PMBIDR.Align [%d] on CPU %d\n", @@ -988,26 +987,26 @@ static void __arm_spe_pmu_dev_probe(void *info) =20 /* It's now safe to read PMSIDR and figure out what we've got */ reg =3D read_sysreg_s(SYS_PMSIDR_EL1); - if (reg & BIT(SYS_PMSIDR_EL1_FE_SHIFT)) + if (reg & BIT(PMSIDR_EL1_FE_SHIFT)) spe_pmu->features |=3D SPE_PMU_FEAT_FILT_EVT; =20 - if (reg & BIT(SYS_PMSIDR_EL1_FT_SHIFT)) + if (reg & BIT(PMSIDR_EL1_FT_SHIFT)) spe_pmu->features |=3D SPE_PMU_FEAT_FILT_TYP; =20 - if (reg & BIT(SYS_PMSIDR_EL1_FL_SHIFT)) + if (reg & BIT(PMSIDR_EL1_FL_SHIFT)) spe_pmu->features |=3D SPE_PMU_FEAT_FILT_LAT; =20 - if (reg & BIT(SYS_PMSIDR_EL1_ARCHINST_SHIFT)) + if (reg & BIT(PMSIDR_EL1_ARCHINST_SHIFT)) spe_pmu->features |=3D SPE_PMU_FEAT_ARCH_INST; =20 - if (reg & BIT(SYS_PMSIDR_EL1_LDS_SHIFT)) + if (reg & BIT(PMSIDR_EL1_LDS_SHIFT)) spe_pmu->features |=3D SPE_PMU_FEAT_LDS; =20 - if (reg & BIT(SYS_PMSIDR_EL1_ERND_SHIFT)) + if (reg & BIT(PMSIDR_EL1_ERND_SHIFT)) spe_pmu->features |=3D SPE_PMU_FEAT_ERND; =20 /* This field has a spaced out encoding, so just use a look-up */ - fld =3D reg >> SYS_PMSIDR_EL1_INTERVAL_SHIFT & SYS_PMSIDR_EL1_INTERVAL_MA= SK; + fld =3D (reg & PMSIDR_EL1_INTERVAL_MASK) >> PMSIDR_EL1_INTERVAL_SHIFT; switch (fld) { case 0: spe_pmu->min_period =3D 256; @@ -1039,7 +1038,7 @@ static void __arm_spe_pmu_dev_probe(void *info) } =20 /* Maximum record size. If it's out-of-range, then fail the probe */ - fld =3D reg >> SYS_PMSIDR_EL1_MAXSIZE_SHIFT & SYS_PMSIDR_EL1_MAXSIZE_MASK; + fld =3D (reg & PMSIDR_EL1_MAXSIZE_MASK) >> PMSIDR_EL1_MAXSIZE_SHIFT; spe_pmu->max_record_sz =3D 1 << fld; if (spe_pmu->max_record_sz > SZ_2K || spe_pmu->max_record_sz < 16) { dev_err(dev, "unsupported PMSIDR_EL1.MaxSize [%d] on CPU %d\n", @@ -1047,7 +1046,7 @@ static void __arm_spe_pmu_dev_probe(void *info) return; } =20 - fld =3D reg >> SYS_PMSIDR_EL1_COUNTSIZE_SHIFT & SYS_PMSIDR_EL1_COUNTSIZE_= MASK; + fld =3D (reg & PMSIDR_EL1_COUNTSIZE_MASK) >> PMSIDR_EL1_COUNTSIZE_SHIFT; switch (fld) { default: dev_warn(dev, "unknown PMSIDR_EL1.CountSize [%d]; assuming 2\n", --=20 b4 0.11.0-dev From nobody Tue Apr 7 20:29:07 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 84D98C43219 for ; Wed, 19 Oct 2022 19:11:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230080AbiJSTLp (ORCPT ); Wed, 19 Oct 2022 15:11:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50090 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229852AbiJSTLd (ORCPT ); Wed, 19 Oct 2022 15:11:33 -0400 Received: from mail-oo1-f49.google.com (mail-oo1-f49.google.com [209.85.161.49]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 386F01C39D2; Wed, 19 Oct 2022 12:11:28 -0700 (PDT) Received: by mail-oo1-f49.google.com with SMTP id x6-20020a4ac586000000b0047f8cc6dbe4so3670624oop.3; Wed, 19 Oct 2022 12:11:28 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mQp/SgU2k3oDYw9yCnKZ2Ab4A7I/j7N7D9SRUWxHwOE=; b=m6tRY5bN9xEgke2id+zYXRtIyB5BWFgoVhDEWvGkGj4dI8A+IsWNa08Q+ThSaxHoL7 /V2zY0FtjQZelhSt/FyvDW+NYrCe7xWwetrmbxsvfMSksixsNTkfDg0/cuFKN3lCe1qb sPNv72NMGtjGfdU7F+PbnA6ZV3JkHQQYLIZb52Tj4oUD4vTaushozJPdoRaZRxdwtlVJ 9JQhKCULqNq2qnpW9cuWiqKTwwv0a4YUaPv8HbELUz93oZf59lUL8OTw3cPy9F1kdpKy IZNlWEWyf9qMVYdhigOOPZWjlLDvgydBIuc7Im/SKoUBLZRi1L61GcdeonyIy/KLFxpg gIPA== X-Gm-Message-State: ACrzQf3NssuR8WyNYluJqUkWuHTEt7GFz8KcUW9QfqC+jgwlzoQioiDD ek0dY1z9rYe0INcldOeybw== X-Google-Smtp-Source: AMsMyM7xeAxAQDKquPXRoYWcYdaVemGqSxwr1fGt4SxvyE1uvAcCzVc/l/1vUquX+d6B00OgXjqHPA== X-Received: by 2002:a4a:ee0f:0:b0:47f:649d:52da with SMTP id bd15-20020a4aee0f000000b0047f649d52damr4365517oob.18.1666206687393; Wed, 19 Oct 2022 12:11:27 -0700 (PDT) Received: from robh_at_kernel.org (66-90-144-107.dyn.grandenetworks.net. [66.90.144.107]) by smtp.gmail.com with ESMTPSA id h7-20020a9d61c7000000b00661c3846b4csm7429899otk.27.2022.10.19.12.11.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Oct 2022 12:11:26 -0700 (PDT) Received: (nullmailer pid 3420902 invoked by uid 1000); Wed, 19 Oct 2022 19:11:25 -0000 From: Rob Herring Date: Wed, 19 Oct 2022 14:11:26 -0500 Subject: [PATCH v2 3/7] arm64/sysreg: Convert SPE registers to automatic generation MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20220825-arm-spe-v8-7-v2-3-e37322d68ac0@kernel.org> References: <20220825-arm-spe-v8-7-v2-0-e37322d68ac0@kernel.org> In-Reply-To: <20220825-arm-spe-v8-7-v2-0-e37322d68ac0@kernel.org> To: Namhyung Kim , James Morse , Ingo Molnar , Mark Rutland , Marc Zyngier , Suzuki K Poulose , Will Deacon , Alexandru Elisei , Catalin Marinas , Arnaldo Carvalho de Melo , Peter Zijlstra , Alexander Shishkin , Oliver Upton , Jiri Olsa Cc: kvmarm@lists.cs.columbia.edu, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Brown X-Mailer: b4 0.11.0-dev Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Convert all the SPE register defines to automatic generation. No functional changes. New registers and fields for SPEv1.2 are added with the conversion. Some of the PMBSR MSS field defines are kept as the automatic generation has no way to create multiple names for the same register bits. The meaning of the MSS field depends on other bits. Signed-off-by: Rob Herring --- v2: - New patch --- arch/arm64/include/asm/sysreg.h | 91 ++----------------------------- arch/arm64/tools/sysreg | 116 ++++++++++++++++++++++++++++++++++++= ++++ 2 files changed, 121 insertions(+), 86 deletions(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysre= g.h index 8df8a0a51273..d002dd00e53e 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -237,99 +237,18 @@ #define SYS_PAR_EL1_FST GENMASK(6, 1) =20 /*** Statistical Profiling Extension ***/ -/* ID registers */ -#define SYS_PMSIDR_EL1 sys_reg(3, 0, 9, 9, 7) -#define PMSIDR_EL1_FE_SHIFT 0 -#define PMSIDR_EL1_FT_SHIFT 1 -#define PMSIDR_EL1_FL_SHIFT 2 -#define PMSIDR_EL1_ARCHINST_SHIFT 3 -#define PMSIDR_EL1_LDS_SHIFT 4 -#define PMSIDR_EL1_ERND_SHIFT 5 -#define PMSIDR_EL1_INTERVAL_SHIFT 8 -#define PMSIDR_EL1_INTERVAL_MASK GENMASK_ULL(11, 8) -#define PMSIDR_EL1_MAXSIZE_SHIFT 12 -#define PMSIDR_EL1_MAXSIZE_MASK GENMASK_ULL(15, 12) -#define PMSIDR_EL1_COUNTSIZE_SHIFT 16 -#define PMSIDR_EL1_COUNTSIZE_MASK GENMASK_ULL(19, 16) - -#define SYS_PMBIDR_EL1 sys_reg(3, 0, 9, 10, 7) -#define PMBIDR_EL1_ALIGN_SHIFT 0 -#define PMBIDR_EL1_ALIGN_MASK 0xfU -#define PMBIDR_EL1_P_SHIFT 4 -#define PMBIDR_EL1_F_SHIFT 5 - -/* Sampling controls */ -#define SYS_PMSCR_EL1 sys_reg(3, 0, 9, 9, 0) -#define PMSCR_EL1_E0SPE_SHIFT 0 -#define PMSCR_EL1_E1SPE_SHIFT 1 -#define PMSCR_EL1_CX_SHIFT 3 -#define PMSCR_EL1_PA_SHIFT 4 -#define PMSCR_EL1_TS_SHIFT 5 -#define PMSCR_EL1_PCT_SHIFT 6 - -#define SYS_PMSCR_EL2 sys_reg(3, 4, 9, 9, 0) -#define PMSCR_EL2_E0HSPE_SHIFT 0 -#define PMSCR_EL2_E2SPE_SHIFT 1 -#define PMSCR_EL2_CX_SHIFT 3 -#define PMSCR_EL2_PA_SHIFT 4 -#define PMSCR_EL2_TS_SHIFT 5 -#define PMSCR_EL2_PCT_SHIFT 6 - -#define SYS_PMSICR_EL1 sys_reg(3, 0, 9, 9, 2) - -#define SYS_PMSIRR_EL1 sys_reg(3, 0, 9, 9, 3) -#define PMSIRR_EL1_RND_SHIFT 0 -#define PMSIRR_EL1_INTERVAL_SHIFT 8 -#define PMSIRR_EL1_INTERVAL_MASK GENMASK_ULL(31, 8) - -/* Filtering controls */ -#define SYS_PMSNEVFR_EL1 sys_reg(3, 0, 9, 9, 1) - -#define SYS_PMSFCR_EL1 sys_reg(3, 0, 9, 9, 4) -#define PMSFCR_EL1_FE_SHIFT 0 -#define PMSFCR_EL1_FT_SHIFT 1 -#define PMSFCR_EL1_FL_SHIFT 2 -#define PMSFCR_EL1_B_SHIFT 16 -#define PMSFCR_EL1_LD_SHIFT 17 -#define PMSFCR_EL1_ST_SHIFT 18 - -#define SYS_PMSEVFR_EL1 sys_reg(3, 0, 9, 9, 5) #define PMSEVFR_EL1_RES0_IMP \ (GENMASK_ULL(47, 32) | GENMASK_ULL(23, 16) | GENMASK_ULL(11, 8) |\ BIT_ULL(6) | BIT_ULL(4) | BIT_ULL(2) | BIT_ULL(0)) #define PMSEVFR_EL1_RES0_V1P1 \ (PMSEVFR_EL1_RES0_IMP & ~(BIT_ULL(18) | BIT_ULL(17) | BIT_ULL(11))) =20 -#define SYS_PMSLATFR_EL1 sys_reg(3, 0, 9, 9, 6) -#define PMSLATFR_EL1_MINLAT_SHIFT 0 - -/* Buffer controls */ -#define SYS_PMBLIMITR_EL1 sys_reg(3, 0, 9, 10, 0) -#define PMBLIMITR_EL1_E_SHIFT 0 -#define PMBLIMITR_EL1_FM_SHIFT 1 -#define PMBLIMITR_EL1_FM_MASK GENMASK_ULL(2, 1) -#define PMBLIMITR_EL1_FM_STOP_IRQ 0 - -#define SYS_PMBPTR_EL1 sys_reg(3, 0, 9, 10, 1) - /* Buffer error reporting */ -#define SYS_PMBSR_EL1 sys_reg(3, 0, 9, 10, 3) -#define PMBSR_EL1_COLL_SHIFT 16 -#define PMBSR_EL1_S_SHIFT 17 -#define PMBSR_EL1_EA_SHIFT 18 -#define PMBSR_EL1_DL_SHIFT 19 -#define PMBSR_EL1_EC_SHIFT 26 -#define PMBSR_EL1_EC_MASK GENMASK_ULL(31, 26) - -#define PMBSR_EL1_EC_BUF 0x0UL -#define PMBSR_EL1_EC_FAULT_S1 0x24UL -#define PMBSR_EL1_EC_FAULT_S2 0x25UL - -#define PMBSR_EL1_FAULT_FSC_SHIFT 0 -#define PMBSR_EL1_FAULT_FSC_MASK 0x3fUL - -#define PMBSR_EL1_BUF_BSC_SHIFT 0 -#define PMBSR_EL1_BUF_BSC_MASK 0x3fUL +#define PMBSR_EL1_FAULT_FSC_SHIFT PMBSR_EL1_MSS_SHIFT +#define PMBSR_EL1_FAULT_FSC_MASK PMBSR_EL1_MSS_MASK + +#define PMBSR_EL1_BUF_BSC_SHIFT PMBSR_EL1_MSS_SHIFT +#define PMBSR_EL1_BUF_BSC_MASK PMBSR_EL1_MSS_MASK =20 #define PMBSR_EL1_BUF_BSC_FULL 0x1UL =20 diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 384757a7eda9..2fbfe625dacc 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -854,6 +854,111 @@ Sysreg FAR_EL1 3 0 6 0 0 Field 63:0 ADDR EndSysreg =20 +Sysreg PMSCR_EL1 3 0 9 9 0 +Res0 63:8 +Field 7:6 PCT +Field 5 TS +Field 4 PA +Field 3 CX +Res0 2 +Field 1 E1SPE +Field 0 E0SPE +EndSysreg + +Sysreg PMSNEVFR_EL1 3 0 9 9 1 +Field 63:0 E +EndSysreg + +Sysreg PMSICR_EL1 3 0 9 9 2 +Field 63:56 ECOUNT +Res0 55:32 +Field 31:0 COUNT +EndSysreg + +Sysreg PMSIRR_EL1 3 0 9 9 3 +Res0 63:32 +Field 31:8 INTERVAL +Res0 7:1 +Field 0 RND +EndSysreg + +Sysreg PMSFCR_EL1 3 0 9 9 4 +Res0 63:19 +Field 18 ST +Field 17 LD +Field 16 B +Res0 15:4 +Field 3 FnE +Field 2 FL +Field 1 FT +Field 0 FE +EndSysreg + +Sysreg PMSEVFR_EL1 3 0 9 9 5 +Field 63:0 E +EndSysreg + +Sysreg PMSLATFR_EL1 3 0 9 9 6 +Res0 63:16 +Field 15:0 MINLAT +EndSysreg + +Sysreg PMSIDR_EL1 3 0 9 9 7 +Res0 63:25 +Field 24 PBT +Field 23:20 FORMAT +Field 19:16 COUNTSIZE +Field 15:12 MAXSIZE +Field 11:8 INTERVAL +Res0 7 +Field 6 FnE +Field 5 ERND +Field 4 LDS +Field 3 ARCHINST +Field 2 FL +Field 1 FT +Field 0 FE +EndSysreg + +Sysreg PMBLIMITR_EL1 3 0 9 10 0 +Field 63:12 LIMIT +Res0 11:6 +Field 5 PMFZ +Res0 4:3 +Enum 2:1 FM + 0b0000 STOP_IRQ +EndEnum +Field 0 E +EndSysreg + +Sysreg PMBPTR_EL1 3 0 9 10 1 +Field 63:0 PTR +EndSysreg + +Sysreg PMBSR_EL1 3 0 9 10 3 +Res0 63:32 +Enum 31:26 EC + 0b000000 BUF + 0b100100 FAULT_S1 + 0b100101 FAULT_S2 +EndEnum +Res0 25:20 +Field 19 DL +Field 18 EA +Field 17 S +Field 16 COLL +Field 15:0 MSS +EndSysreg + +Sysreg PMBIDR_EL1 3 0 9 10 7 +Res0 63:12 +Field 11:8 EA +Res0 7:6 +Field 5 F +Field 4 P +Field 3:0 ALIGN +EndSysreg + SysregFields CONTEXTIDR_ELx Res0 63:32 Field 31:0 PROCID @@ -1008,6 +1113,17 @@ Sysreg FAR_EL2 3 4 6 0 0 Field 63:0 ADDR EndSysreg =20 +Sysreg PMSCR_EL2 3 4 9 9 0 +Res0 63:8 +Field 7:6 PCT +Field 5 TS +Field 4 PA +Field 3 CX +Res0 2 +Field 1 E2SPE +Field 0 E0HSPE +EndSysreg + Sysreg CONTEXTIDR_EL2 3 4 13 0 1 Fields CONTEXTIDR_ELx EndSysreg --=20 b4 0.11.0-dev From nobody Tue Apr 7 20:29:07 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F057DC4332F for ; Wed, 19 Oct 2022 19:12:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231204AbiJSTMH (ORCPT ); Wed, 19 Oct 2022 15:12:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50240 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230490AbiJSTLi (ORCPT ); Wed, 19 Oct 2022 15:11:38 -0400 Received: from mail-oa1-f51.google.com (mail-oa1-f51.google.com [209.85.160.51]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3BC0B1C3E40; Wed, 19 Oct 2022 12:11:35 -0700 (PDT) Received: by mail-oa1-f51.google.com with SMTP id 586e51a60fabf-1321a1e94b3so21866909fac.1; Wed, 19 Oct 2022 12:11:35 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1uHI8D71nZXIPql0Ea/USh9ISq5jM79VtrVQ2e/RcjE=; b=ESR48RXOEJM6wR5V4PAw26iLcJpjAxftkzN8VatmeWEWPJ4WC6Q8hwcaq6jR1aj48A ZbsRVgO+yNug/ni4pwT75mg3DOTJdY6bLR4pMJ/iO8ZwmYmuwKS76O/RdIZPeJceGPo+ tawU8AmATeauqbkNew8SSg+SZzCD2huvv+c+SRjHXrYa6W/YlJRzWWRJ6ppR5VeAol0L BnZlFycDNgtRMQLl8MQ2KjfS4EqtQlPEYYn3l9cplBxsQ8K2Lo8/CYMoGe6HWC1Gseim ymhyq/rPSp1OlBJkKfd4PSgPpC2OPQtzr+2UUqv/kXrX4OlrZC6SnIVq71+oN8cyQGst Jm6g== X-Gm-Message-State: ACrzQf1c7fmLjqGKCzP4/jzK4bTu2zBHlgBnidYdKwY4ZrE5O0E2POCz tUkDsB6mon/6CnnWTfmo6w== X-Google-Smtp-Source: AMsMyM7WkeQ7g4p9Ezrvy829By+9j1qkB1Fwp6SHcF4UBut9w8J0q3DhODuEycKY6qUiN1eBQPjq9A== X-Received: by 2002:a05:6870:4713:b0:132:d3fb:9f80 with SMTP id b19-20020a056870471300b00132d3fb9f80mr5866965oaq.15.1666206694359; Wed, 19 Oct 2022 12:11:34 -0700 (PDT) Received: from robh_at_kernel.org (66-90-144-107.dyn.grandenetworks.net. [66.90.144.107]) by smtp.gmail.com with ESMTPSA id 23-20020aca2117000000b00354efb5be11sm7001508oiz.15.2022.10.19.12.11.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Oct 2022 12:11:33 -0700 (PDT) Received: (nullmailer pid 3420904 invoked by uid 1000); Wed, 19 Oct 2022 19:11:25 -0000 From: Rob Herring Date: Wed, 19 Oct 2022 14:11:27 -0500 Subject: [PATCH v2 4/7] perf: arm_spe: Drop BIT() and use FIELD_GET/PREP accessors MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20220825-arm-spe-v8-7-v2-4-e37322d68ac0@kernel.org> References: <20220825-arm-spe-v8-7-v2-0-e37322d68ac0@kernel.org> In-Reply-To: <20220825-arm-spe-v8-7-v2-0-e37322d68ac0@kernel.org> To: Namhyung Kim , James Morse , Ingo Molnar , Mark Rutland , Marc Zyngier , Suzuki K Poulose , Will Deacon , Alexandru Elisei , Catalin Marinas , Arnaldo Carvalho de Melo , Peter Zijlstra , Alexander Shishkin , Oliver Upton , Jiri Olsa Cc: kvmarm@lists.cs.columbia.edu, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Brown X-Mailer: b4 0.11.0-dev Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Now that generated sysregs are in place, update the register field accesses. The use of BIT() is no longer needed with the new defines. Use FIELD_GET and FIELD_PREP instead of open coding masking and shifting. No functional change. Signed-off-by: Rob Herring --- drivers/perf/arm_spe_pmu.c | 70 ++++++++++++++++++++++--------------------= ---- 1 file changed, 34 insertions(+), 36 deletions(-) diff --git a/drivers/perf/arm_spe_pmu.c b/drivers/perf/arm_spe_pmu.c index 814ed18346b6..9b4bd72087ea 100644 --- a/drivers/perf/arm_spe_pmu.c +++ b/drivers/perf/arm_spe_pmu.c @@ -283,18 +283,18 @@ static u64 arm_spe_event_to_pmscr(struct perf_event *= event) struct perf_event_attr *attr =3D &event->attr; u64 reg =3D 0; =20 - reg |=3D ATTR_CFG_GET_FLD(attr, ts_enable) << PMSCR_EL1_TS_SHIFT; - reg |=3D ATTR_CFG_GET_FLD(attr, pa_enable) << PMSCR_EL1_PA_SHIFT; - reg |=3D ATTR_CFG_GET_FLD(attr, pct_enable) << PMSCR_EL1_PCT_SHIFT; + reg |=3D FIELD_PREP(PMSCR_EL1_TS, ATTR_CFG_GET_FLD(attr, ts_enable)); + reg |=3D FIELD_PREP(PMSCR_EL1_PA, ATTR_CFG_GET_FLD(attr, pa_enable)); + reg |=3D FIELD_PREP(PMSCR_EL1_PCT, ATTR_CFG_GET_FLD(attr, pct_enable)); =20 if (!attr->exclude_user) - reg |=3D BIT(PMSCR_EL1_E0SPE_SHIFT); + reg |=3D PMSCR_EL1_E0SPE; =20 if (!attr->exclude_kernel) - reg |=3D BIT(PMSCR_EL1_E1SPE_SHIFT); + reg |=3D PMSCR_EL1_E1SPE; =20 if (get_spe_event_has_cx(event)) - reg |=3D BIT(PMSCR_EL1_CX_SHIFT); + reg |=3D PMSCR_EL1_CX; =20 return reg; } @@ -322,7 +322,7 @@ static u64 arm_spe_event_to_pmsirr(struct perf_event *e= vent) =20 arm_spe_event_sanitise_period(event); =20 - reg |=3D ATTR_CFG_GET_FLD(attr, jitter) << PMSIRR_EL1_RND_SHIFT; + reg |=3D FIELD_PREP(PMSIRR_EL1_RND, ATTR_CFG_GET_FLD(attr, jitter)); reg |=3D event->hw.sample_period; =20 return reg; @@ -333,18 +333,18 @@ static u64 arm_spe_event_to_pmsfcr(struct perf_event = *event) struct perf_event_attr *attr =3D &event->attr; u64 reg =3D 0; =20 - reg |=3D ATTR_CFG_GET_FLD(attr, load_filter) << PMSFCR_EL1_LD_SHIFT; - reg |=3D ATTR_CFG_GET_FLD(attr, store_filter) << PMSFCR_EL1_ST_SHIFT; - reg |=3D ATTR_CFG_GET_FLD(attr, branch_filter) << PMSFCR_EL1_B_SHIFT; + reg |=3D FIELD_PREP(PMSFCR_EL1_LD, ATTR_CFG_GET_FLD(attr, load_filter)); + reg |=3D FIELD_PREP(PMSFCR_EL1_ST, ATTR_CFG_GET_FLD(attr, store_filter)); + reg |=3D FIELD_PREP(PMSFCR_EL1_B, ATTR_CFG_GET_FLD(attr, branch_filter)); =20 if (reg) - reg |=3D BIT(PMSFCR_EL1_FT_SHIFT); + reg |=3D PMSFCR_EL1_FT; =20 if (ATTR_CFG_GET_FLD(attr, event_filter)) - reg |=3D BIT(PMSFCR_EL1_FE_SHIFT); + reg |=3D PMSFCR_EL1_FE; =20 if (ATTR_CFG_GET_FLD(attr, min_latency)) - reg |=3D BIT(PMSFCR_EL1_FL_SHIFT); + reg |=3D PMSFCR_EL1_FL; =20 return reg; } @@ -358,8 +358,7 @@ static u64 arm_spe_event_to_pmsevfr(struct perf_event *= event) static u64 arm_spe_event_to_pmslatfr(struct perf_event *event) { struct perf_event_attr *attr =3D &event->attr; - return ATTR_CFG_GET_FLD(attr, min_latency) - << PMSLATFR_EL1_MINLAT_SHIFT; + return FIELD_PREP(PMSLATFR_EL1_MINLAT, ATTR_CFG_GET_FLD(attr, min_latency= )); } =20 static void arm_spe_pmu_pad_buf(struct perf_output_handle *handle, int len) @@ -511,7 +510,7 @@ static void arm_spe_perf_aux_output_begin(struct perf_o= utput_handle *handle, limit =3D buf->snapshot ? arm_spe_pmu_next_snapshot_off(handle) : arm_spe_pmu_next_off(handle); if (limit) - limit |=3D BIT(PMBLIMITR_EL1_E_SHIFT); + limit |=3D PMBLIMITR_EL1_E; =20 limit +=3D (u64)buf->base; base =3D (u64)buf->base + PERF_IDX2OFF(handle->head, buf); @@ -570,23 +569,23 @@ arm_spe_pmu_buf_get_fault_act(struct perf_output_hand= le *handle) =20 /* Service required? */ pmbsr =3D read_sysreg_s(SYS_PMBSR_EL1); - if (!(pmbsr & BIT(PMBSR_EL1_S_SHIFT))) + if (!FIELD_GET(PMBSR_EL1_S, pmbsr)) return SPE_PMU_BUF_FAULT_ACT_SPURIOUS; =20 /* * If we've lost data, disable profiling and also set the PARTIAL * flag to indicate that the last record is corrupted. */ - if (pmbsr & BIT(PMBSR_EL1_DL_SHIFT)) + if (FIELD_GET(PMBSR_EL1_DL, pmbsr)) perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED | PERF_AUX_FLAG_PARTIAL); =20 /* Report collisions to userspace so that it can up the period */ - if (pmbsr & BIT(PMBSR_EL1_COLL_SHIFT)) + if (FIELD_GET(PMBSR_EL1_COLL, pmbsr)) perf_aux_output_flag(handle, PERF_AUX_FLAG_COLLISION); =20 /* We only expect buffer management events */ - switch (FIELD_GET(PMBSR_EL1_EC_MASK, pmbsr)) { + switch (FIELD_GET(PMBSR_EL1_EC, pmbsr)) { case PMBSR_EL1_EC_BUF: /* Handled below */ break; @@ -716,23 +715,22 @@ static int arm_spe_pmu_event_init(struct perf_event *= event) return -EINVAL; =20 reg =3D arm_spe_event_to_pmsfcr(event); - if ((reg & BIT(PMSFCR_EL1_FE_SHIFT)) && + if ((FIELD_GET(PMSFCR_EL1_FE, reg)) && !(spe_pmu->features & SPE_PMU_FEAT_FILT_EVT)) return -EOPNOTSUPP; =20 - if ((reg & BIT(PMSFCR_EL1_FT_SHIFT)) && + if ((FIELD_GET(PMSFCR_EL1_FT, reg)) && !(spe_pmu->features & SPE_PMU_FEAT_FILT_TYP)) return -EOPNOTSUPP; =20 - if ((reg & BIT(PMSFCR_EL1_FL_SHIFT)) && + if ((FIELD_GET(PMSFCR_EL1_FL, reg)) && !(spe_pmu->features & SPE_PMU_FEAT_FILT_LAT)) return -EOPNOTSUPP; =20 set_spe_event_has_cx(event); reg =3D arm_spe_event_to_pmscr(event); if (!perfmon_capable() && - (reg & (BIT(PMSCR_EL1_PA_SHIFT) | - BIT(PMSCR_EL1_PCT_SHIFT)))) + (reg & (PMSCR_EL1_PA | PMSCR_EL1_PCT))) return -EACCES; =20 return 0; @@ -970,14 +968,14 @@ static void __arm_spe_pmu_dev_probe(void *info) =20 /* Read PMBIDR first to determine whether or not we have access */ reg =3D read_sysreg_s(SYS_PMBIDR_EL1); - if (reg & BIT(PMBIDR_EL1_P_SHIFT)) { + if (FIELD_GET(PMBIDR_EL1_P, reg)) { dev_err(dev, "profiling buffer owned by higher exception level\n"); return; } =20 /* Minimum alignment. If it's out-of-range, then fail the probe */ - fld =3D (reg & PMBIDR_EL1_ALIGN_MASK) >> PMBIDR_EL1_ALIGN_SHIFT; + fld =3D FIELD_GET(PMBIDR_EL1_ALIGN, reg); spe_pmu->align =3D 1 << fld; if (spe_pmu->align > SZ_2K) { dev_err(dev, "unsupported PMBIDR.Align [%d] on CPU %d\n", @@ -987,26 +985,26 @@ static void __arm_spe_pmu_dev_probe(void *info) =20 /* It's now safe to read PMSIDR and figure out what we've got */ reg =3D read_sysreg_s(SYS_PMSIDR_EL1); - if (reg & BIT(PMSIDR_EL1_FE_SHIFT)) + if (FIELD_GET(PMSIDR_EL1_FE, reg)) spe_pmu->features |=3D SPE_PMU_FEAT_FILT_EVT; =20 - if (reg & BIT(PMSIDR_EL1_FT_SHIFT)) + if (FIELD_GET(PMSIDR_EL1_FT, reg)) spe_pmu->features |=3D SPE_PMU_FEAT_FILT_TYP; =20 - if (reg & BIT(PMSIDR_EL1_FL_SHIFT)) + if (FIELD_GET(PMSIDR_EL1_FL, reg)) spe_pmu->features |=3D SPE_PMU_FEAT_FILT_LAT; =20 - if (reg & BIT(PMSIDR_EL1_ARCHINST_SHIFT)) + if (FIELD_GET(PMSIDR_EL1_ARCHINST, reg)) spe_pmu->features |=3D SPE_PMU_FEAT_ARCH_INST; =20 - if (reg & BIT(PMSIDR_EL1_LDS_SHIFT)) + if (FIELD_GET(PMSIDR_EL1_LDS, reg)) spe_pmu->features |=3D SPE_PMU_FEAT_LDS; =20 - if (reg & BIT(PMSIDR_EL1_ERND_SHIFT)) + if (FIELD_GET(PMSIDR_EL1_ERND, reg)) spe_pmu->features |=3D SPE_PMU_FEAT_ERND; =20 /* This field has a spaced out encoding, so just use a look-up */ - fld =3D (reg & PMSIDR_EL1_INTERVAL_MASK) >> PMSIDR_EL1_INTERVAL_SHIFT; + fld =3D FIELD_GET(PMSIDR_EL1_INTERVAL, reg); switch (fld) { case 0: spe_pmu->min_period =3D 256; @@ -1038,7 +1036,7 @@ static void __arm_spe_pmu_dev_probe(void *info) } =20 /* Maximum record size. If it's out-of-range, then fail the probe */ - fld =3D (reg & PMSIDR_EL1_MAXSIZE_MASK) >> PMSIDR_EL1_MAXSIZE_SHIFT; + fld =3D FIELD_GET(PMSIDR_EL1_MAXSIZE, reg); spe_pmu->max_record_sz =3D 1 << fld; if (spe_pmu->max_record_sz > SZ_2K || spe_pmu->max_record_sz < 16) { dev_err(dev, "unsupported PMSIDR_EL1.MaxSize [%d] on CPU %d\n", @@ -1046,7 +1044,7 @@ static void __arm_spe_pmu_dev_probe(void *info) return; } =20 - fld =3D (reg & PMSIDR_EL1_COUNTSIZE_MASK) >> PMSIDR_EL1_COUNTSIZE_SHIFT; + fld =3D FIELD_GET(PMSIDR_EL1_COUNTSIZE, reg); switch (fld) { default: dev_warn(dev, "unknown PMSIDR_EL1.CountSize [%d]; assuming 2\n", --=20 b4 0.11.0-dev From nobody Tue Apr 7 20:29:07 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C7037C433FE for ; Wed, 19 Oct 2022 19:12:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229727AbiJSTME (ORCPT ); Wed, 19 Oct 2022 15:12:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50192 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230440AbiJSTLh (ORCPT ); Wed, 19 Oct 2022 15:11:37 -0400 Received: from mail-oi1-f179.google.com (mail-oi1-f179.google.com [209.85.167.179]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 283E71C8D6E; Wed, 19 Oct 2022 12:11:32 -0700 (PDT) Received: by mail-oi1-f179.google.com with SMTP id n83so20327732oif.11; Wed, 19 Oct 2022 12:11:32 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ZBd+XTJESJNOGYoq8Sf5QKUv5aLEk2PWt2aI7lcJy1Q=; b=FH4Jubv70siJQE6Ht/gah9yHhInCnUquqAvEklezWAwx2bc3agYqAqTy6zQmCsQ2Qq 2IF+ZHiuSGc+Bwf2FwctAVeqsJmrLdd8lkQ4tjOn0WTkHVy3jx/CaajdMChgY2y3TV0q JSBNQKmu2fAzESYGRek9T7Quo3vWKx+AwLq9OKD0B+pbpDYPkLTs/+i/MNGF7P7q/3VK z+CrxoMH+KmgtvOY5oIBXcG2l42eh/PjO9SHGkulZotePKtd03KL9B2QHl24RxsMuTgE zLhMj/Wq85d4nUDIpwOwenG7p9n4lgqFjrJs7QWufFY67RPeiqfv/p9FAR+O+xBBEi2H GI2w== X-Gm-Message-State: ACrzQf3mxKBFrp1DiGqHsTD3zZX1VZo4g3c04jfKDZgymb5uZplYCRu9 BT+4jzthoHCHpm1K5rLQaV0v2rMIdQ== X-Google-Smtp-Source: AMsMyM53HC4eCK4NKlfS5OabG/2idCaE/8R5DmuO7iXth8yDJHlcBsw0Hkxwf9ZW/H1vTGzH8KmBcw== X-Received: by 2002:a05:6808:1510:b0:354:566c:78e5 with SMTP id u16-20020a056808151000b00354566c78e5mr19239918oiw.188.1666206691599; Wed, 19 Oct 2022 12:11:31 -0700 (PDT) Received: from robh_at_kernel.org (66-90-144-107.dyn.grandenetworks.net. [66.90.144.107]) by smtp.gmail.com with ESMTPSA id q78-20020a4a3351000000b00480db116926sm2048754ooq.27.2022.10.19.12.11.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Oct 2022 12:11:31 -0700 (PDT) Received: (nullmailer pid 3420906 invoked by uid 1000); Wed, 19 Oct 2022 19:11:25 -0000 From: Rob Herring Date: Wed, 19 Oct 2022 14:11:28 -0500 Subject: [PATCH v2 5/7] perf: arm_spe: Support new SPEv1.2/v8.7 'not taken' event MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20220825-arm-spe-v8-7-v2-5-e37322d68ac0@kernel.org> References: <20220825-arm-spe-v8-7-v2-0-e37322d68ac0@kernel.org> In-Reply-To: <20220825-arm-spe-v8-7-v2-0-e37322d68ac0@kernel.org> To: Namhyung Kim , James Morse , Ingo Molnar , Mark Rutland , Marc Zyngier , Suzuki K Poulose , Will Deacon , Alexandru Elisei , Catalin Marinas , Arnaldo Carvalho de Melo , Peter Zijlstra , Alexander Shishkin , Oliver Upton , Jiri Olsa Cc: kvmarm@lists.cs.columbia.edu, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Brown X-Mailer: b4 0.11.0-dev Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Arm SPEv1.2 (Armv8.7/v9.2) adds a new event, 'not taken', in bit 6 of the PMSEVFR_EL1 register. Update arm_spe_pmsevfr_res0() to support the additional event. Signed-off-by: Rob Herring --- v2: - Update for v6.1 sysreg generated header changes --- arch/arm64/include/asm/sysreg.h | 2 ++ drivers/perf/arm_spe_pmu.c | 4 +++- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysre= g.h index d002dd00e53e..06231e896832 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -242,6 +242,8 @@ BIT_ULL(6) | BIT_ULL(4) | BIT_ULL(2) | BIT_ULL(0)) #define PMSEVFR_EL1_RES0_V1P1 \ (PMSEVFR_EL1_RES0_IMP & ~(BIT_ULL(18) | BIT_ULL(17) | BIT_ULL(11))) +#define PMSEVFR_EL1_RES0_V1P2 \ + (PMSEVFR_EL1_RES0_V1P1 & ~BIT_ULL(6)) =20 /* Buffer error reporting */ #define PMBSR_EL1_FAULT_FSC_SHIFT PMBSR_EL1_MSS_SHIFT diff --git a/drivers/perf/arm_spe_pmu.c b/drivers/perf/arm_spe_pmu.c index 9b4bd72087ea..0b9b847919d0 100644 --- a/drivers/perf/arm_spe_pmu.c +++ b/drivers/perf/arm_spe_pmu.c @@ -677,9 +677,11 @@ static u64 arm_spe_pmsevfr_res0(u16 pmsver) case ID_AA64DFR0_EL1_PMSVer_IMP: return PMSEVFR_EL1_RES0_IMP; case ID_AA64DFR0_EL1_PMSVer_V1P1: + return PMSEVFR_EL1_RES0_V1P1; + case ID_AA64DFR0_EL1_PMSVer_V1P2: /* Return the highest version we support in default */ default: - return PMSEVFR_EL1_RES0_V1P1; + return PMSEVFR_EL1_RES0_V1P2; } } =20 --=20 b4 0.11.0-dev From nobody Tue Apr 7 20:29:07 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A8DF6C4332F for ; Wed, 19 Oct 2022 19:11:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230141AbiJSTLx (ORCPT ); Wed, 19 Oct 2022 15:11:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50092 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229920AbiJSTLd (ORCPT ); Wed, 19 Oct 2022 15:11:33 -0400 Received: from mail-oi1-f175.google.com (mail-oi1-f175.google.com [209.85.167.175]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 85D8A1C3E63; Wed, 19 Oct 2022 12:11:29 -0700 (PDT) Received: by mail-oi1-f175.google.com with SMTP id w196so20341022oiw.8; Wed, 19 Oct 2022 12:11:29 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4nOSzjJQMiiQFtQCXOfHoj5W8uYrP30fMIHaTAT/kCc=; b=hCTgCrWjB6kwLLIxgXdluNmaFm5dNrHBkl1urJB1KgTnr9Wt7IZLPhCgQM5pjgD0jO gX8pWu2GQM2koFnT5KbPk+DoM2B4JcPVerBc+iOSSu8THL00TnxLgyw+/V6Jxen89zr7 zCkYWt3OWshzgTTa/34AV5eXrXbvmUUp67av57JXG0nPahAXg8FhkoBKpM7DUpM61Hou mLmfIJ+L9JXkuQKrkJIUfcRecTGW9e1qeYRAIPv7upenEk6qDk+layRNbMBHoJZQw/g+ 2w+QDw6D6YhTe1nFmI7VDxYYOWLkyk6zeoyRy6i2Ta1yUoUoFYE0UuQlM+4Rky6iDKbs K7Rg== X-Gm-Message-State: ACrzQf0A1RdBUKwCtyhHZhI6S5Xxn248LGwGgWcN5uwtCIORi2I1MHHu iRTs8YMhPHArXIJvCvfu/A== X-Google-Smtp-Source: AMsMyM6hBFo6lc3QPPJZLi2rdtLDIwN0Hv6MsBsjwIii7y66xrRf5EteOTh2AxrGHMhQuml0B0j83w== X-Received: by 2002:a05:6808:3090:b0:354:e8e2:6512 with SMTP id bl16-20020a056808309000b00354e8e26512mr18775295oib.118.1666206688760; Wed, 19 Oct 2022 12:11:28 -0700 (PDT) Received: from robh_at_kernel.org (66-90-144-107.dyn.grandenetworks.net. [66.90.144.107]) by smtp.gmail.com with ESMTPSA id z9-20020a056870460900b0013191b00f72sm7878011oao.17.2022.10.19.12.11.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Oct 2022 12:11:28 -0700 (PDT) Received: (nullmailer pid 3420908 invoked by uid 1000); Wed, 19 Oct 2022 19:11:25 -0000 From: Rob Herring Date: Wed, 19 Oct 2022 14:11:29 -0500 Subject: [PATCH v2 6/7] perf: Add perf_event_attr::config3 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20220825-arm-spe-v8-7-v2-6-e37322d68ac0@kernel.org> References: <20220825-arm-spe-v8-7-v2-0-e37322d68ac0@kernel.org> In-Reply-To: <20220825-arm-spe-v8-7-v2-0-e37322d68ac0@kernel.org> To: Namhyung Kim , James Morse , Ingo Molnar , Mark Rutland , Marc Zyngier , Suzuki K Poulose , Will Deacon , Alexandru Elisei , Catalin Marinas , Arnaldo Carvalho de Melo , Peter Zijlstra , Alexander Shishkin , Oliver Upton , Jiri Olsa Cc: kvmarm@lists.cs.columbia.edu, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Brown X-Mailer: b4 0.11.0-dev Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Arm SPEv1.2 adds another 64-bits of event filtering control. As the existing perf_event_attr::configN fields are all used up for SPE PMU, an additional field is needed. Add a new 'config3' field. Signed-off-by: Rob Herring --- v2: - Drop tools/ side update --- include/uapi/linux/perf_event.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/uapi/linux/perf_event.h b/include/uapi/linux/perf_even= t.h index 85be78e0e7f6..b2b1d7b54097 100644 --- a/include/uapi/linux/perf_event.h +++ b/include/uapi/linux/perf_event.h @@ -374,6 +374,7 @@ enum perf_event_read_format { #define PERF_ATTR_SIZE_VER5 112 /* add: aux_watermark */ #define PERF_ATTR_SIZE_VER6 120 /* add: aux_sample_size */ #define PERF_ATTR_SIZE_VER7 128 /* add: sig_data */ +#define PERF_ATTR_SIZE_VER8 136 /* add: config3 */ =20 /* * Hardware event_id to monitor via a performance monitoring event: @@ -515,6 +516,8 @@ struct perf_event_attr { * truncated accordingly on 32 bit architectures. */ __u64 sig_data; + + __u64 config3; /* extension of config2 */ }; =20 /* --=20 b4 0.11.0-dev From nobody Tue Apr 7 20:29:07 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BA8ADC4332F for ; Wed, 19 Oct 2022 19:11:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230292AbiJSTL5 (ORCPT ); Wed, 19 Oct 2022 15:11:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50132 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230432AbiJSTLf (ORCPT ); Wed, 19 Oct 2022 15:11:35 -0400 Received: from mail-ot1-f49.google.com (mail-ot1-f49.google.com [209.85.210.49]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9C1411C712E; Wed, 19 Oct 2022 12:11:31 -0700 (PDT) Received: by mail-ot1-f49.google.com with SMTP id p24-20020a9d6958000000b00661c528849eso10067435oto.9; Wed, 19 Oct 2022 12:11:31 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=43IaqXn32YycCBd3/SGJ6Da4qva/kGDXqjobO4DMXeA=; b=wu01KFcU8n49Dijx+qpwD9N7YQGuwsLIRvHnDfNyuZe+3Z384rV/UQ+8F/SotO7i6e DrxY20Cvg4cfQ4QkYaOq5ey1WjyJwueLPpdiUT08K4/jB2LqmV4yKsJqjKITH8rZ6exq li4pLr+4rg74fump5v1f8O0Ell/EXLlCtha+PHVTifq7frUUHH/LEYWyBt33ql9GozQO 7tlPMQ5dwn0ry56KjEdFJUuBqJfdfflST7FMgiQ9nK+TStFpvYcc4AjLdopQQ3zmN1cI PLulEbEEdT3vf/RzLQhOLbUcXSrT7x7hv189NYQWDJGcsmy1pnvLVA+nqblzyu+pp315 ERdA== X-Gm-Message-State: ACrzQf0A8K1UsN4mXHliL9212jwitNKN6eH3xBrfrn518Zpgv6wjr/26 mjj/Azxmelp/J1kE3qMFlw== X-Google-Smtp-Source: AMsMyM52ccM2SuB4fJVuNR6xyd3GwViwYeYnmewRYJ6qofqTylHkTtpXjuHE/sY2iyCkl53jTYlNfw== X-Received: by 2002:a9d:6948:0:b0:661:a43c:77a3 with SMTP id p8-20020a9d6948000000b00661a43c77a3mr4934314oto.222.1666206690183; Wed, 19 Oct 2022 12:11:30 -0700 (PDT) Received: from robh_at_kernel.org (66-90-144-107.dyn.grandenetworks.net. [66.90.144.107]) by smtp.gmail.com with ESMTPSA id q7-20020a4aac47000000b0047f8ceca22bsm6816526oon.15.2022.10.19.12.11.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Oct 2022 12:11:29 -0700 (PDT) Received: (nullmailer pid 3420910 invoked by uid 1000); Wed, 19 Oct 2022 19:11:25 -0000 From: Rob Herring Date: Wed, 19 Oct 2022 14:11:30 -0500 Subject: [PATCH v2 7/7] perf: arm_spe: Add support for SPEv1.2 inverted event filtering MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20220825-arm-spe-v8-7-v2-7-e37322d68ac0@kernel.org> References: <20220825-arm-spe-v8-7-v2-0-e37322d68ac0@kernel.org> In-Reply-To: <20220825-arm-spe-v8-7-v2-0-e37322d68ac0@kernel.org> To: Namhyung Kim , James Morse , Ingo Molnar , Mark Rutland , Marc Zyngier , Suzuki K Poulose , Will Deacon , Alexandru Elisei , Catalin Marinas , Arnaldo Carvalho de Melo , Peter Zijlstra , Alexander Shishkin , Oliver Upton , Jiri Olsa Cc: kvmarm@lists.cs.columbia.edu, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Brown X-Mailer: b4 0.11.0-dev Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Arm SPEv1.2 (Arm v8.7/v9.2) adds a new feature called Inverted Event Filter which excludes samples matching the event filter. The feature mirrors the existing event filter in PMSEVFR_EL1 adding a new register, PMSNEVFR_EL1, which has the same event bit assignments. Signed-off-by: Rob Herring --- v2: - Update for auto generated register defines - Avoid accessing SYS_PMSNEVFR_EL1 on < v8.7 --- drivers/perf/arm_spe_pmu.c | 45 ++++++++++++++++++++++++++++++++++++++++++= +++ 1 file changed, 45 insertions(+) diff --git a/drivers/perf/arm_spe_pmu.c b/drivers/perf/arm_spe_pmu.c index 0b9b847919d0..ab5fcf02a4ca 100644 --- a/drivers/perf/arm_spe_pmu.c +++ b/drivers/perf/arm_spe_pmu.c @@ -85,6 +85,7 @@ struct arm_spe_pmu { #define SPE_PMU_FEAT_ARCH_INST (1UL << 3) #define SPE_PMU_FEAT_LDS (1UL << 4) #define SPE_PMU_FEAT_ERND (1UL << 5) +#define SPE_PMU_FEAT_INV_FILT_EVT (1UL << 6) #define SPE_PMU_FEAT_DEV_PROBED (1UL << 63) u64 features; =20 @@ -202,6 +203,10 @@ static const struct attribute_group arm_spe_pmu_cap_gr= oup =3D { #define ATTR_CFG_FLD_min_latency_LO 0 #define ATTR_CFG_FLD_min_latency_HI 11 =20 +#define ATTR_CFG_FLD_inv_event_filter_CFG config3 /* PMSNEVFR_EL1 */ +#define ATTR_CFG_FLD_inv_event_filter_LO 0 +#define ATTR_CFG_FLD_inv_event_filter_HI 63 + /* Why does everything I do descend into this? */ #define __GEN_PMU_FORMAT_ATTR(cfg, lo, hi) \ (lo) =3D=3D (hi) ? #cfg ":" #lo "\n" : #cfg ":" #lo "-" #hi @@ -232,6 +237,7 @@ GEN_PMU_FORMAT_ATTR(branch_filter); GEN_PMU_FORMAT_ATTR(load_filter); GEN_PMU_FORMAT_ATTR(store_filter); GEN_PMU_FORMAT_ATTR(event_filter); +GEN_PMU_FORMAT_ATTR(inv_event_filter); GEN_PMU_FORMAT_ATTR(min_latency); =20 static struct attribute *arm_spe_pmu_formats_attr[] =3D { @@ -243,12 +249,27 @@ static struct attribute *arm_spe_pmu_formats_attr[] = =3D { &format_attr_load_filter.attr, &format_attr_store_filter.attr, &format_attr_event_filter.attr, + &format_attr_inv_event_filter.attr, &format_attr_min_latency.attr, NULL, }; =20 +static umode_t arm_spe_pmu_format_attr_is_visible(struct kobject *kobj, + struct attribute *attr, + int unused) + { + struct device *dev =3D kobj_to_dev(kobj); + struct arm_spe_pmu *spe_pmu =3D dev_get_drvdata(dev); + + if (attr =3D=3D &format_attr_inv_event_filter.attr && !(spe_pmu->features= & SPE_PMU_FEAT_INV_FILT_EVT)) + return 0; + + return attr->mode; +} + static const struct attribute_group arm_spe_pmu_format_group =3D { .name =3D "format", + .is_visible =3D arm_spe_pmu_format_attr_is_visible, .attrs =3D arm_spe_pmu_formats_attr, }; =20 @@ -343,6 +364,9 @@ static u64 arm_spe_event_to_pmsfcr(struct perf_event *e= vent) if (ATTR_CFG_GET_FLD(attr, event_filter)) reg |=3D PMSFCR_EL1_FE; =20 + if (ATTR_CFG_GET_FLD(attr, inv_event_filter)) + reg |=3D PMSFCR_EL1_FnE; + if (ATTR_CFG_GET_FLD(attr, min_latency)) reg |=3D PMSFCR_EL1_FL; =20 @@ -355,6 +379,12 @@ static u64 arm_spe_event_to_pmsevfr(struct perf_event = *event) return ATTR_CFG_GET_FLD(attr, event_filter); } =20 +static u64 arm_spe_event_to_pmsnevfr(struct perf_event *event) +{ + struct perf_event_attr *attr =3D &event->attr; + return ATTR_CFG_GET_FLD(attr, inv_event_filter); +} + static u64 arm_spe_event_to_pmslatfr(struct perf_event *event) { struct perf_event_attr *attr =3D &event->attr; @@ -703,6 +733,9 @@ static int arm_spe_pmu_event_init(struct perf_event *ev= ent) if (arm_spe_event_to_pmsevfr(event) & arm_spe_pmsevfr_res0(spe_pmu->pmsve= r)) return -EOPNOTSUPP; =20 + if (arm_spe_event_to_pmsnevfr(event) & arm_spe_pmsevfr_res0(spe_pmu->pmsv= er)) + return -EOPNOTSUPP; + if (attr->exclude_idle) return -EOPNOTSUPP; =20 @@ -721,6 +754,10 @@ static int arm_spe_pmu_event_init(struct perf_event *e= vent) !(spe_pmu->features & SPE_PMU_FEAT_FILT_EVT)) return -EOPNOTSUPP; =20 + if ((FIELD_GET(PMSFCR_EL1_FnE, reg)) && + !(spe_pmu->features & SPE_PMU_FEAT_INV_FILT_EVT)) + return -EOPNOTSUPP; + if ((FIELD_GET(PMSFCR_EL1_FT, reg)) && !(spe_pmu->features & SPE_PMU_FEAT_FILT_TYP)) return -EOPNOTSUPP; @@ -756,6 +793,11 @@ static void arm_spe_pmu_start(struct perf_event *event= , int flags) reg =3D arm_spe_event_to_pmsevfr(event); write_sysreg_s(reg, SYS_PMSEVFR_EL1); =20 + if (spe_pmu->features & SPE_PMU_FEAT_INV_FILT_EVT) { + reg =3D arm_spe_event_to_pmsnevfr(event); + write_sysreg_s(reg, SYS_PMSNEVFR_EL1); + } + reg =3D arm_spe_event_to_pmslatfr(event); write_sysreg_s(reg, SYS_PMSLATFR_EL1); =20 @@ -990,6 +1032,9 @@ static void __arm_spe_pmu_dev_probe(void *info) if (FIELD_GET(PMSIDR_EL1_FE, reg)) spe_pmu->features |=3D SPE_PMU_FEAT_FILT_EVT; =20 + if (FIELD_GET(PMSIDR_EL1_FnE, reg)) + spe_pmu->features |=3D SPE_PMU_FEAT_INV_FILT_EVT; + if (FIELD_GET(PMSIDR_EL1_FT, reg)) spe_pmu->features |=3D SPE_PMU_FEAT_FILT_TYP; =20 --=20 b4 0.11.0-dev