From nobody Thu Jun 18 01:44:04 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EDDEBECAA25 for ; Thu, 25 Aug 2022 18:08:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243124AbiHYSIV (ORCPT ); Thu, 25 Aug 2022 14:08:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57578 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243068AbiHYSIK (ORCPT ); Thu, 25 Aug 2022 14:08:10 -0400 Received: from mail-oi1-f170.google.com (mail-oi1-f170.google.com [209.85.167.170]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E8375BD155; Thu, 25 Aug 2022 11:08:07 -0700 (PDT) Received: by mail-oi1-f170.google.com with SMTP id n124so13293594oih.7; Thu, 25 Aug 2022 11:08:07 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc; bh=Sk5vHqzSrLz4606TEoT4An8u20ArqzK6P+IPHBOiaUg=; b=3hvd5mNGRnTsOkuURBNohxzi0TLNbotn2dkawwm95LM0K6TIXns+r1Ig4q3dO+ZnSV UNmtVXhtaq2QTxTK7y8dRNBRmVn4Hx9Qm1x5TAmbzi6s9yh2q0ygL20PRETC+Ftu7ssP pEnfCsqGxZKXIIzryx2GImN+YGe5cVZOFmiKGJCSHXhLvL01VRW3g6EBcEGmpzqIBIiq 5LmuP8ihovi+xGVukxMVhoAkgNZDXX7bBk7vTt9NQFzt05/tzaIUSfjqgS2BrNJ2BRmh 4/jdVjNh/GgSWJlk8ExhCYlQRd/pirwRxQIV5/ZYoAMMpwzGS+xmZ/8hzlj4zebQqb41 RbDg== X-Gm-Message-State: ACgBeo38beyketC/ULtCiLCxhMQviBQBuL1TE0z3wYWxK9dwQQ6Xb2Gd nrdqaM7UnQqaVxpQ6GacMKBby8+6rg== X-Google-Smtp-Source: AA6agR6tmX6O0OQeg40/a66cayp7ZWrOxCAZYXQEEjFQWCLZQTwLxAFer43d7O2YrUBoOEJPMNoEYQ== X-Received: by 2002:a05:6808:1281:b0:344:d85a:9f38 with SMTP id a1-20020a056808128100b00344d85a9f38mr82124oiw.207.1661450887187; Thu, 25 Aug 2022 11:08:07 -0700 (PDT) Received: from [127.0.1.1] (66-90-144-107.dyn.grandenetworks.net. [66.90.144.107]) by smtp.googlemail.com with ESMTPSA id t26-20020a0568080b3a00b003434b221a17sm5000231oij.52.2022.08.25.11.08.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Aug 2022 11:08:06 -0700 (PDT) From: Rob Herring Date: Thu, 25 Aug 2022 13:08:00 -0500 Subject: [PATCH RFC v1 1/3] perf: arm_spe: Support new SPEv1.2/v8.7 'not taken' event MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20220825-arm-spe-v8-7-v1-1-c75b8d92e692@kernel.org> References: <20220825-arm-spe-v8-7-v1-0-c75b8d92e692@kernel.org> In-Reply-To: <20220825-arm-spe-v8-7-v1-0-c75b8d92e692@kernel.org> To: Alexander Shishkin , Ingo Molnar , Catalin Marinas , Peter Zijlstra , Mark Rutland , Will Deacon , Jiri Olsa , Namhyung Kim , Arnaldo Carvalho de Melo Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org X-Mailer: b4 0.10.0-dev Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Arm SPEv1.2 (Armv8.7/v9.2) adds a new event, 'not taken', in bit 6 of the PMSEVFR_EL1 register. Update arm_spe_pmsevfr_res0() to support the additional event. Signed-off-by: Rob Herring diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysre= g.h index 7c71358d44c4..57904c11aece 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -312,6 +312,8 @@ BIT_ULL(6) | BIT_ULL(4) | BIT_ULL(2) | BIT_ULL(0)) #define SYS_PMSEVFR_EL1_RES0_8_3 \ (SYS_PMSEVFR_EL1_RES0_8_2 & ~(BIT_ULL(18) | BIT_ULL(17) | BIT_ULL(11))) +#define SYS_PMSEVFR_EL1_RES0_8_7 \ + (SYS_PMSEVFR_EL1_RES0_8_3 & ~BIT_ULL(6)) =20 #define SYS_PMSLATFR_EL1 sys_reg(3, 0, 9, 9, 6) #define SYS_PMSLATFR_EL1_MINLAT_SHIFT 0 @@ -847,6 +849,7 @@ =20 #define ID_AA64DFR0_PMSVER_8_2 0x1 #define ID_AA64DFR0_PMSVER_8_3 0x2 +#define ID_AA64DFR0_PMSVER_8_7 0x3 =20 #define ID_DFR0_PERFMON_SHIFT 24 =20 diff --git a/drivers/perf/arm_spe_pmu.c b/drivers/perf/arm_spe_pmu.c index b65a7d9640e1..a75b03b5c8f9 100644 --- a/drivers/perf/arm_spe_pmu.c +++ b/drivers/perf/arm_spe_pmu.c @@ -677,9 +677,11 @@ static u64 arm_spe_pmsevfr_res0(u16 pmsver) case ID_AA64DFR0_PMSVER_8_2: return SYS_PMSEVFR_EL1_RES0_8_2; case ID_AA64DFR0_PMSVER_8_3: + return SYS_PMSEVFR_EL1_RES0_8_3; + case ID_AA64DFR0_PMSVER_8_7: /* Return the highest version we support in default */ default: - return SYS_PMSEVFR_EL1_RES0_8_3; + return SYS_PMSEVFR_EL1_RES0_8_7; } } =20 --=20 b4 0.10.0-dev From nobody Thu Jun 18 01:44:04 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A0B3BECAA2A for ; Thu, 25 Aug 2022 18:08:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243080AbiHYSIO (ORCPT ); Thu, 25 Aug 2022 14:08:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57576 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243070AbiHYSIK (ORCPT ); Thu, 25 Aug 2022 14:08:10 -0400 Received: from mail-oa1-f54.google.com (mail-oa1-f54.google.com [209.85.160.54]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 23B93BD14A; Thu, 25 Aug 2022 11:08:09 -0700 (PDT) Received: by mail-oa1-f54.google.com with SMTP id 586e51a60fabf-11d7a859b3aso14694814fac.4; Thu, 25 Aug 2022 11:08:09 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc; bh=01rEmmNrDVKSyl8VLDT9G5HuxPTw6FkrMpKcesbH32I=; b=wXeNhxJmfWj0VmyGJI5n3FE/ZZdx4P4m4L2uJzqBXNQPYltYgdY2xipA/m8mbHeBIz fma4rUWQAB3o1rsn6BORHDwuaNeX7Rmdv7R5/wEGTZEbBdN21P3TL2JxOLisNS05IHsu YEEm1AWdSNGefaRl+4agJg3PeCmws3VbIfD4Cxgj9QhJjJ6Xqe6gI3/XBvVJmPIaUtXg dm1m83ecXz9/Dut45WmDnhzQDUlmNfnrFiBJpaPLzdVzdFNrBdutoVldOAjzaUYoOknl 95ifGyRfWzcvLQYlaKn/A78Vlte7jrZO8Fs1gZZo5SH82rpjfCtPHaiZnWjaE1itzi0y YjFg== X-Gm-Message-State: ACgBeo3jzTHc0qgztVtJA0qEbaWCJuzTQuGAqM/+nSy4YTBQBEt0nPmp GeZoiopl+Z1O16qUACRWPg== X-Google-Smtp-Source: AA6agR69ouslPscBnnihLnHTVesjlGc7oGHvQng69WDQdJq7kDlyfdLirsSr+DvtWdQiBSUROGhT4w== X-Received: by 2002:a05:6870:d69e:b0:10e:3b6e:b0a5 with SMTP id z30-20020a056870d69e00b0010e3b6eb0a5mr172499oap.200.1661450888384; Thu, 25 Aug 2022 11:08:08 -0700 (PDT) Received: from [127.0.1.1] (66-90-144-107.dyn.grandenetworks.net. [66.90.144.107]) by smtp.googlemail.com with ESMTPSA id t26-20020a0568080b3a00b003434b221a17sm5000231oij.52.2022.08.25.11.08.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Aug 2022 11:08:08 -0700 (PDT) From: Rob Herring Date: Thu, 25 Aug 2022 13:08:01 -0500 Subject: [PATCH RFC v1 2/3] perf: Add perf_event_attr::config3 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20220825-arm-spe-v8-7-v1-2-c75b8d92e692@kernel.org> References: <20220825-arm-spe-v8-7-v1-0-c75b8d92e692@kernel.org> In-Reply-To: <20220825-arm-spe-v8-7-v1-0-c75b8d92e692@kernel.org> To: Alexander Shishkin , Ingo Molnar , Catalin Marinas , Peter Zijlstra , Mark Rutland , Will Deacon , Jiri Olsa , Namhyung Kim , Arnaldo Carvalho de Melo Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org X-Mailer: b4 0.10.0-dev Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Arm SPEv1.2 adds another 64-bits of event filtering control. As the existing perf_event_attr::configN fields are all used up for SPE PMU, an additional field is needed. Add a new 'config3' field. Signed-off-by: Rob Herring diff --git a/include/uapi/linux/perf_event.h b/include/uapi/linux/perf_even= t.h index 03b370062741..b53f9b958235 100644 --- a/include/uapi/linux/perf_event.h +++ b/include/uapi/linux/perf_event.h @@ -333,6 +333,7 @@ enum perf_event_read_format { #define PERF_ATTR_SIZE_VER5 112 /* add: aux_watermark */ #define PERF_ATTR_SIZE_VER6 120 /* add: aux_sample_size */ #define PERF_ATTR_SIZE_VER7 128 /* add: sig_data */ +#define PERF_ATTR_SIZE_VER8 136 /* add: config3 */ =20 /* * Hardware event_id to monitor via a performance monitoring event: @@ -474,6 +475,8 @@ struct perf_event_attr { * truncated accordingly on 32 bit architectures. */ __u64 sig_data; + + __u64 config3; /* extension of config2 */ }; =20 /* diff --git a/tools/include/uapi/linux/perf_event.h b/tools/include/uapi/lin= ux/perf_event.h index 581ed4bdc062..7fad17853310 100644 --- a/tools/include/uapi/linux/perf_event.h +++ b/tools/include/uapi/linux/perf_event.h @@ -333,6 +333,7 @@ enum perf_event_read_format { #define PERF_ATTR_SIZE_VER5 112 /* add: aux_watermark */ #define PERF_ATTR_SIZE_VER6 120 /* add: aux_sample_size */ #define PERF_ATTR_SIZE_VER7 128 /* add: sig_data */ +#define PERF_ATTR_SIZE_VER8 136 /* add: config3 */ =20 /* * Hardware event_id to monitor via a performance monitoring event: @@ -474,6 +475,8 @@ struct perf_event_attr { * truncated accordingly on 32 bit architectures. */ __u64 sig_data; + + __u64 config3; /* extension of config2 */ }; =20 /* --=20 b4 0.10.0-dev From nobody Thu Jun 18 01:44:04 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2B6B6ECAA25 for ; Thu, 25 Aug 2022 18:08:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243154AbiHYSIY (ORCPT ); Thu, 25 Aug 2022 14:08:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57546 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243003AbiHYSIM (ORCPT ); Thu, 25 Aug 2022 14:08:12 -0400 Received: from mail-oi1-f169.google.com (mail-oi1-f169.google.com [209.85.167.169]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 63E48BD13C; Thu, 25 Aug 2022 11:08:10 -0700 (PDT) Received: by mail-oi1-f169.google.com with SMTP id u14so24257586oie.2; Thu, 25 Aug 2022 11:08:10 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc; bh=tbWJaf7Z6/yVPqCl4RIYma3ZVXVVKCcb3R/w2pBaROw=; b=VeCWyV4KqsUupFjRIdnXTmVL9GyVxfKHiWymaRnHyaywvHGq96A7I8FmliGpIF+VQo +HsO2DXbxDJwoN2jReBEQ3ogFDAtginWrmE5nLcMXVIQSz6DbJzXqCA/DOei1hvvwV3Y gedjgnFWHRugJFLGEIa/J6QlaSK1OJe4YGwO1P5m5OFmy9GIs8pGAr8Apa+6TC/zllAR idhpLRWrHeMjL/vGECEqcQBX8PmTb/iGDKsomw9Kz6woElOUVlS9Yz9LknzxTBhKaELj kczI/DobYc7Yo0ZQJZZdn22QsRxXo4AT9C3Y3SOKwhiheOv+B5kLTUrZO+H3+wa2eNcT WrXg== X-Gm-Message-State: ACgBeo3Lt0JjWgssWj6g2M0lyDanAPoXub1Pbb+o7ioojwN6QrO/0HOp HXnMfyPTecduG+kOWZbhEA== X-Google-Smtp-Source: AA6agR4Puawz6qVua1NOff23UmBZoicECZLLKq/OJ94mLKhSzLt9JdmYy6nz0D2wj92tYXLExuzQRg== X-Received: by 2002:a05:6808:11cf:b0:344:f75e:6716 with SMTP id p15-20020a05680811cf00b00344f75e6716mr75808oiv.285.1661450889613; Thu, 25 Aug 2022 11:08:09 -0700 (PDT) Received: from [127.0.1.1] (66-90-144-107.dyn.grandenetworks.net. [66.90.144.107]) by smtp.googlemail.com with ESMTPSA id t26-20020a0568080b3a00b003434b221a17sm5000231oij.52.2022.08.25.11.08.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Aug 2022 11:08:09 -0700 (PDT) From: Rob Herring Date: Thu, 25 Aug 2022 13:08:02 -0500 Subject: [PATCH RFC v1 3/3] perf: arm_spe: Add support for SPEv1.2 inverted event filtering MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20220825-arm-spe-v8-7-v1-3-c75b8d92e692@kernel.org> References: <20220825-arm-spe-v8-7-v1-0-c75b8d92e692@kernel.org> In-Reply-To: <20220825-arm-spe-v8-7-v1-0-c75b8d92e692@kernel.org> To: Alexander Shishkin , Ingo Molnar , Catalin Marinas , Peter Zijlstra , Mark Rutland , Will Deacon , Jiri Olsa , Namhyung Kim , Arnaldo Carvalho de Melo Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org X-Mailer: b4 0.10.0-dev Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Arm SPEv1.2 (Arm v8.7/v9.2) adds a new feature called Inverted Event Filter which excludes samples matching the event filter. The feature mirrors the existing event filter in PMSEVFR_EL1 adding a new register, PMSNEVFR_EL1, which has the same event bit assignments. Signed-off-by: Rob Herring diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysre= g.h index 57904c11aece..9744da888818 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -258,6 +258,7 @@ #define SYS_PMSIDR_EL1_ARCHINST_SHIFT 3 #define SYS_PMSIDR_EL1_LDS_SHIFT 4 #define SYS_PMSIDR_EL1_ERND_SHIFT 5 +#define SYS_PMSIDR_EL1_FNE_SHIFT 6 #define SYS_PMSIDR_EL1_INTERVAL_SHIFT 8 #define SYS_PMSIDR_EL1_INTERVAL_MASK 0xfUL #define SYS_PMSIDR_EL1_MAXSIZE_SHIFT 12 @@ -302,6 +303,7 @@ #define SYS_PMSFCR_EL1_FE_SHIFT 0 #define SYS_PMSFCR_EL1_FT_SHIFT 1 #define SYS_PMSFCR_EL1_FL_SHIFT 2 +#define SYS_PMSFCR_EL1_FNE_SHIFT 3 #define SYS_PMSFCR_EL1_B_SHIFT 16 #define SYS_PMSFCR_EL1_LD_SHIFT 17 #define SYS_PMSFCR_EL1_ST_SHIFT 18 diff --git a/drivers/perf/arm_spe_pmu.c b/drivers/perf/arm_spe_pmu.c index a75b03b5c8f9..724409a88423 100644 --- a/drivers/perf/arm_spe_pmu.c +++ b/drivers/perf/arm_spe_pmu.c @@ -82,6 +82,7 @@ struct arm_spe_pmu { #define SPE_PMU_FEAT_ARCH_INST (1UL << 3) #define SPE_PMU_FEAT_LDS (1UL << 4) #define SPE_PMU_FEAT_ERND (1UL << 5) +#define SPE_PMU_FEAT_INV_FILT_EVT (1UL << 6) #define SPE_PMU_FEAT_DEV_PROBED (1UL << 63) u64 features; =20 @@ -199,6 +200,10 @@ static const struct attribute_group arm_spe_pmu_cap_gr= oup =3D { #define ATTR_CFG_FLD_min_latency_LO 0 #define ATTR_CFG_FLD_min_latency_HI 11 =20 +#define ATTR_CFG_FLD_inv_event_filter_CFG config3 /* PMSNEVFR_EL1 */ +#define ATTR_CFG_FLD_inv_event_filter_LO 0 +#define ATTR_CFG_FLD_inv_event_filter_HI 63 + /* Why does everything I do descend into this? */ #define __GEN_PMU_FORMAT_ATTR(cfg, lo, hi) \ (lo) =3D=3D (hi) ? #cfg ":" #lo "\n" : #cfg ":" #lo "-" #hi @@ -229,6 +234,7 @@ GEN_PMU_FORMAT_ATTR(branch_filter); GEN_PMU_FORMAT_ATTR(load_filter); GEN_PMU_FORMAT_ATTR(store_filter); GEN_PMU_FORMAT_ATTR(event_filter); +GEN_PMU_FORMAT_ATTR(inv_event_filter); GEN_PMU_FORMAT_ATTR(min_latency); =20 static struct attribute *arm_spe_pmu_formats_attr[] =3D { @@ -240,12 +246,27 @@ static struct attribute *arm_spe_pmu_formats_attr[] = =3D { &format_attr_load_filter.attr, &format_attr_store_filter.attr, &format_attr_event_filter.attr, + &format_attr_inv_event_filter.attr, &format_attr_min_latency.attr, NULL, }; =20 +static umode_t arm_spe_pmu_format_attr_is_visible(struct kobject *kobj, + struct attribute *attr, + int unused) + { + struct device *dev =3D kobj_to_dev(kobj); + struct arm_spe_pmu *spe_pmu =3D dev_get_drvdata(dev); + + if (attr =3D=3D &format_attr_inv_event_filter.attr && !(spe_pmu->features= & SPE_PMU_FEAT_INV_FILT_EVT)) + return 0; + + return attr->mode; +} + static const struct attribute_group arm_spe_pmu_format_group =3D { .name =3D "format", + .is_visible =3D arm_spe_pmu_format_attr_is_visible, .attrs =3D arm_spe_pmu_formats_attr, }; =20 @@ -341,6 +362,9 @@ static u64 arm_spe_event_to_pmsfcr(struct perf_event *e= vent) if (ATTR_CFG_GET_FLD(attr, event_filter)) reg |=3D BIT(SYS_PMSFCR_EL1_FE_SHIFT); =20 + if (ATTR_CFG_GET_FLD(attr, inv_event_filter)) + reg |=3D BIT(SYS_PMSFCR_EL1_FNE_SHIFT); + if (ATTR_CFG_GET_FLD(attr, min_latency)) reg |=3D BIT(SYS_PMSFCR_EL1_FL_SHIFT); =20 @@ -353,6 +377,12 @@ static u64 arm_spe_event_to_pmsevfr(struct perf_event = *event) return ATTR_CFG_GET_FLD(attr, event_filter); } =20 +static u64 arm_spe_event_to_pmsnevfr(struct perf_event *event) +{ + struct perf_event_attr *attr =3D &event->attr; + return ATTR_CFG_GET_FLD(attr, inv_event_filter); +} + static u64 arm_spe_event_to_pmslatfr(struct perf_event *event) { struct perf_event_attr *attr =3D &event->attr; @@ -703,6 +733,9 @@ static int arm_spe_pmu_event_init(struct perf_event *ev= ent) if (arm_spe_event_to_pmsevfr(event) & arm_spe_pmsevfr_res0(spe_pmu->pmsve= r)) return -EOPNOTSUPP; =20 + if (arm_spe_event_to_pmsnevfr(event) & arm_spe_pmsevfr_res0(spe_pmu->pmsv= er)) + return -EOPNOTSUPP; + if (attr->exclude_idle) return -EOPNOTSUPP; =20 @@ -721,6 +754,10 @@ static int arm_spe_pmu_event_init(struct perf_event *e= vent) !(spe_pmu->features & SPE_PMU_FEAT_FILT_EVT)) return -EOPNOTSUPP; =20 + if ((reg & BIT(SYS_PMSFCR_EL1_FNE_SHIFT)) && + !(spe_pmu->features & SPE_PMU_FEAT_INV_FILT_EVT)) + return -EOPNOTSUPP; + if ((reg & BIT(SYS_PMSFCR_EL1_FT_SHIFT)) && !(spe_pmu->features & SPE_PMU_FEAT_FILT_TYP)) return -EOPNOTSUPP; @@ -757,6 +794,9 @@ static void arm_spe_pmu_start(struct perf_event *event,= int flags) reg =3D arm_spe_event_to_pmsevfr(event); write_sysreg_s(reg, SYS_PMSEVFR_EL1); =20 + reg =3D arm_spe_event_to_pmsnevfr(event); + write_sysreg_s(reg, SYS_PMSNEVFR_EL1); + reg =3D arm_spe_event_to_pmslatfr(event); write_sysreg_s(reg, SYS_PMSLATFR_EL1); =20 @@ -991,6 +1031,9 @@ static void __arm_spe_pmu_dev_probe(void *info) if (reg & BIT(SYS_PMSIDR_EL1_FE_SHIFT)) spe_pmu->features |=3D SPE_PMU_FEAT_FILT_EVT; =20 + if (reg & BIT(SYS_PMSIDR_EL1_FNE_SHIFT)) + spe_pmu->features |=3D SPE_PMU_FEAT_INV_FILT_EVT; + if (reg & BIT(SYS_PMSIDR_EL1_FT_SHIFT)) spe_pmu->features |=3D SPE_PMU_FEAT_FILT_TYP; =20 --=20 b4 0.10.0-dev