From nobody Wed Apr 8 01:17:15 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4D888C32796 for ; Wed, 24 Aug 2022 09:37:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236434AbiHXJhy (ORCPT ); Wed, 24 Aug 2022 05:37:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58052 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236120AbiHXJhM (ORCPT ); Wed, 24 Aug 2022 05:37:12 -0400 Received: from smtp2.axis.com (smtp2.axis.com [195.60.68.18]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 48C2195AE5; Wed, 24 Aug 2022 02:37:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=axis.com; q=dns/txt; s=axis-central1; t=1661333832; x=1692869832; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=YJCzYLp8Y2/CRNKGcIXUTUMWNoKrWZYcZFG32dKFNeM=; b=Q2Q+QCcUfcchcyMhjEa6cYy+q29S9bGzZrBTqaZiE2TWpFL41JoqmQu4 +KL6oQFj7q5ODzOqrgIJoyYlsigBDte0H7/PGUFNWgMb7OgFVJEu0kM4Y aH872UfP3jJeEjwcGTQOQ2fYP4qe321nOFrhbtkphnwyl0a/UED0X8i6Q A6SXvIZMtFtynToxANU8UcKEpb08ue+OLnOwtMyUae9UzwX/c9f5Omhu4 +uuqNFnmSEQe9kBfWtHHYaF8F5xKdsp4o+V9XoRgT1dkts9lYNEynrNxW Svngfd8GIFNM5/xfjm3Bg5tGMb1fCYOpPRf4K7S8z3exiMcTv+HB+YX+d Q==; From: Marcus Carlberg To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni CC: , Marcus Carlberg , , Subject: [PATCH] net: dsa: mv88e6xxx: Allow external SMI if serial Date: Wed, 24 Aug 2022 11:37:06 +0200 Message-ID: <20220824093706.19049-1-marcus.carlberg@axis.com> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" p0_mode set to one of the supported serial mode should not prevent configuring the external SMI interface in mv88e6xxx_g2_scratch_gpio_set_smi. The current masking of the p0_mode only checks the first 2 bits. This results in switches supporting serial mode cannot setup external SMI on certain serial modes (Ex: 1000BASE-X and SGMII). Extend the mask of the p0_mode to include the reduced modes and serial modes as allowed modes for the external SMI interface. Signed-off-by: Marcus Carlberg --- drivers/net/dsa/mv88e6xxx/global2.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/dsa/mv88e6xxx/global2.h b/drivers/net/dsa/mv88e6xx= x/global2.h index 807aeaad9830..7536b8b0ad01 100644 --- a/drivers/net/dsa/mv88e6xxx/global2.h +++ b/drivers/net/dsa/mv88e6xxx/global2.h @@ -298,7 +298,7 @@ #define MV88E6352_G2_SCRATCH_CONFIG_DATA1 0x71 #define MV88E6352_G2_SCRATCH_CONFIG_DATA1_NO_CPU BIT(2) #define MV88E6352_G2_SCRATCH_CONFIG_DATA2 0x72 -#define MV88E6352_G2_SCRATCH_CONFIG_DATA2_P0_MODE_MASK 0x3 +#define MV88E6352_G2_SCRATCH_CONFIG_DATA2_P0_MODE_MASK 0xf #define MV88E6352_G2_SCRATCH_CONFIG_DATA3 0x73 #define MV88E6352_G2_SCRATCH_CONFIG_DATA3_S_SEL BIT(1) =20 --=20 2.20.1