From nobody Sat Apr 11 00:44:30 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 368C7C32772 for ; Tue, 23 Aug 2022 19:37:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229743AbiHWThj (ORCPT ); Tue, 23 Aug 2022 15:37:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59460 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232081AbiHWThR (ORCPT ); Tue, 23 Aug 2022 15:37:17 -0400 Received: from mail-wr1-x429.google.com (mail-wr1-x429.google.com [IPv6:2a00:1450:4864:20::429]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 90B8D9412B for ; Tue, 23 Aug 2022 11:33:56 -0700 (PDT) Received: by mail-wr1-x429.google.com with SMTP id bs25so18036844wrb.2 for ; Tue, 23 Aug 2022 11:33:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=conchuod.ie; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=gfYO45Fhrr292YriQBgq+GL0i0hKssdiRtp+ptuTmB8=; b=cxhWc3M4obppLHYQ1+1dtIkL3cRvwms6r8PwhRPdHDTBOodgqvj+O9GT+FIXT+jVHM cLh/Qw3HVakfK6G2nWP1Yew4MJQDEtQI7QpU+r6N0eHqbjF0wJ41mxQK6Mlb8s/QZ3fy SdDOP+rFnRzP1U+moj1P99yf0KdJkXioTWpwRdqUa42HEjRci3ryA21S6QskbzqnjstD jYKuJAKEa0RgEOdq0ZSHUh/D9OU86R7A5NtNLdP2Whs8V1ITPGcIIait/JWspTt/7gUn VMWDd+BN7Y836i5XYRf1P+fGFGKd5HdoE2zvCUi/n6n2FMcrbn/7MFxO7ncgmhXv1wKg jicA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=gfYO45Fhrr292YriQBgq+GL0i0hKssdiRtp+ptuTmB8=; b=TuLUSxi7nqg/lfxJR/I8gJc0/8zzjvT4D8HRCLAKBIDc2G/KkzlgAKNTEo4dvJIa9K r0yQDEzf0t8Wqd/8Wt/JHT6JQ1u7IEixOCiMeMQHwRhS8pXJrYFn3DlI+NUdIERVWcsq KCZplMLlxKMrtSNW47xz508OGDtlNK/K7KcTLqcYNEKf+7Z2MyoFHEmO+o7813UF+TNE K6wOpaOQ/opwaKAijVUehGALsqYsR9diEtEpEQMDrgiaClRfuZIKjAx+t56qlq4VtBtZ AZUEVnaK9nx81LA4ih00QTxReWpJh7AS2k6dyaFcO1vtPEcBIwurbVAcjOyT9WYifE2t OKzg== X-Gm-Message-State: ACgBeo0ey3cxzjj3mxSrgEXTxpnR01PHjtD3wZucQSHkYZhVTt/88vn9 SW0+DfyCtQwwBIGR7i/OpuFr4Q== X-Google-Smtp-Source: AA6agR7bBIo4WvfaTQmBmKbZYuyKOKLHUXCNnIkzR2yMddKcJrOEa3tcvpyzuyC0FL4VN5JT0BNR4A== X-Received: by 2002:adf:fa0d:0:b0:225:1bd4:5d8a with SMTP id m13-20020adffa0d000000b002251bd45d8amr14077231wrr.106.1661279634905; Tue, 23 Aug 2022 11:33:54 -0700 (PDT) Received: from henark71.. ([51.37.149.245]) by smtp.gmail.com with ESMTPSA id p16-20020a05600c1d9000b003a5fcae64d4sm19396556wms.29.2022.08.23.11.33.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Aug 2022 11:33:54 -0700 (PDT) From: Conor Dooley To: Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Palmer Dabbelt , Paul Walmsley , Albert Ou Cc: Daniel Lezcano , Anup Patel , Conor Dooley , Guo Ren , Sagar Kadam , Jessica Clarke , Andrew Jones , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, qemu-riscv@nongnu.org, Rob Herring Subject: [PATCH v4 1/4] dt-bindings: timer: sifive,clint: add legacy riscv compatible Date: Tue, 23 Aug 2022 19:33:17 +0100 Message-Id: <20220823183319.3314940-2-mail@conchuod.ie> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220823183319.3314940-1-mail@conchuod.ie> References: <20220823183319.3314940-1-mail@conchuod.ie> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Conor Dooley While "real" hardware might not use the compatible string "riscv,clint0" it is present in the driver & QEMU uses it for automatically generated virt machine dtbs. To avoid dt-validate problems with QEMU produced dtbs, such as the following, add it to the binding. riscv-virt.dtb: clint@2000000: compatible:0: 'sifive,clint0' is not one of = ['sifive,fu540-c000-clint', 'starfive,jh7100-clint', 'canaan,k210-clint'] Reported-by: Rob Herring Link: https://lore.kernel.org/linux-riscv/20220803170552.GA2250266-robh@ker= nel.org/ Reviewed-by: Rob Herring Signed-off-by: Conor Dooley Reviewed-by: Heiko Stuebner --- .../bindings/timer/sifive,clint.yaml | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Do= cumentation/devicetree/bindings/timer/sifive,clint.yaml index e64f46339079..bbad24165837 100644 --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml @@ -22,12 +22,18 @@ description: =20 properties: compatible: - items: - - enum: - - sifive,fu540-c000-clint - - starfive,jh7100-clint - - canaan,k210-clint - - const: sifive,clint0 + oneOf: + - items: + - enum: + - sifive,fu540-c000-clint + - starfive,jh7100-clint + - canaan,k210-clint + - const: sifive,clint0 + - items: + - const: sifive,clint0 + - const: riscv,clint0 + deprecated: true + description: For the QEMU virt machine only =20 description: Should be ",-clint" and "sifive,clint". --=20 2.37.1 From nobody Sat Apr 11 00:44:30 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 94BB4C32772 for ; Tue, 23 Aug 2022 19:37:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232442AbiHWThr (ORCPT ); Tue, 23 Aug 2022 15:37:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56668 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231502AbiHWThV (ORCPT ); Tue, 23 Aug 2022 15:37:21 -0400 Received: from mail-wm1-x32e.google.com (mail-wm1-x32e.google.com [IPv6:2a00:1450:4864:20::32e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C65CF98367 for ; Tue, 23 Aug 2022 11:33:57 -0700 (PDT) Received: by mail-wm1-x32e.google.com with SMTP id r83-20020a1c4456000000b003a5cb389944so10077742wma.4 for ; Tue, 23 Aug 2022 11:33:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=conchuod.ie; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=SXjC+1eAipiwLVckozeddO7uqjToKvtGjqOQeotcMjA=; b=KbX0skZMzo1dHORnO1cN91HQwYl5fklrhtHhR2L7O0pjBR2WQcmbC6+6QCsRSVABqj suGNDT5zgBvkiN83Nia7Fxsj/GUe4ZrlfG1UmMEwbcLoXEmvZ6cUjQlSkDHA5N85GJ7D MXdfh/3k36Gh681xIxzhAcU5D3VniKUKc7tEsODBfWdS6vC/28mqYdr0qmBYnIIijOqQ 6o4C9Z6SGB/f+JumjLGTtaD8bu4/rwOJUdJ+qMjZPi23lOHvE9w6+/bt9ug4xdsaXDcL 0nTVKQhWqBAP3808O62VC5jQ8sGAcXbvQgO/aibQ4HwTyaZ5rV1mI4kilaKf0RQQhBgU q44A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=SXjC+1eAipiwLVckozeddO7uqjToKvtGjqOQeotcMjA=; b=YcH53LzPbXfamfv9InWZp01u72GbF7M/d5vIrlDBDj8LNDEQlbVGpvBir1qdJXtRKs Cw0gGntptrnkExpU9nkAxsQsVFfd3JohjZms00YW9mF/tsKRYKiFwF5DeBE79ZzLFhtM IZpsylKB2ndl1Gl84pL1miHDHoDZ3dslzEBym42heB3eDO2jB+ZP27zT1LL8vptOxnxh ksiSLbODbqmVKB/zA+dYdWblQEkydr7o3mINCswAAQj7N3L12MWO93OeoyXSOUGxF9QG yAP+t2cwGrclrfCsg/AdO/gnndc6X9K/BFfWJvDtdDktzmD9gjdNs6BhanD8f9cskCD7 gOQA== X-Gm-Message-State: ACgBeo3Gy+4duOMU+hHKh8c20fTXk1Fqpz2ZzAs8EOeb6d/N7j7+R977 UfJ5So3IKLBuWyXxtIsEYlyg5Q== X-Google-Smtp-Source: AA6agR5q5Ekkbe1X55VNXuzYGucNAP21vgIbfd9u4MP8ILX9K+hq65/YrNIaCt5ZG3XgVMMwVoDaHA== X-Received: by 2002:a05:600c:2c47:b0:3a6:4623:4ccf with SMTP id r7-20020a05600c2c4700b003a646234ccfmr3142126wmg.85.1661279636305; Tue, 23 Aug 2022 11:33:56 -0700 (PDT) Received: from henark71.. ([51.37.149.245]) by smtp.gmail.com with ESMTPSA id p16-20020a05600c1d9000b003a5fcae64d4sm19396556wms.29.2022.08.23.11.33.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Aug 2022 11:33:55 -0700 (PDT) From: Conor Dooley To: Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Palmer Dabbelt , Paul Walmsley , Albert Ou Cc: Daniel Lezcano , Anup Patel , Conor Dooley , Guo Ren , Sagar Kadam , Jessica Clarke , Andrew Jones , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, qemu-riscv@nongnu.org, Rob Herring Subject: [PATCH v4 2/4] dt-bindings: interrupt-controller: sifive,plic: add legacy riscv compatible Date: Tue, 23 Aug 2022 19:33:18 +0100 Message-Id: <20220823183319.3314940-3-mail@conchuod.ie> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220823183319.3314940-1-mail@conchuod.ie> References: <20220823183319.3314940-1-mail@conchuod.ie> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Conor Dooley While "real" hardware might not use the compatible string "riscv,plic0" it is present in the driver & QEMU uses it for automatically generated virt machine dtbs. To avoid dt-validate problems with QEMU produced dtbs, such as the following, add it to the binding. riscv-virt.dtb: plic@c000000: compatible: 'oneOf' conditional failed, one m= ust be fixed: 'sifive,plic-1.0.0' is not one of ['sifive,fu540-c000-plic', 'starf= ive,jh7100-plic', 'canaan,k210-plic'] 'sifive,plic-1.0.0' is not one of ['allwinner,sun20i-d1-plic'] 'sifive,plic-1.0.0' was expected 'thead,c900-plic' was expected riscv-virt.dtb: plic@c000000: '#address-cells' is a required property Reported-by: Rob Herring Link: https://lore.kernel.org/linux-riscv/20220803170552.GA2250266-robh@ker= nel.org/ Reviewed-by: Rob Herring Signed-off-by: Conor Dooley Reviewed-by: Heiko Stuebner --- .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,= plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/si= five,plic-1.0.0.yaml index 92e0f8c3eff2..99e01f4d0a69 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.= 0.0.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.= 0.0.yaml @@ -66,6 +66,11 @@ properties: - enum: - allwinner,sun20i-d1-plic - const: thead,c900-plic + - items: + - const: sifive,plic-1.0.0 + - const: riscv,plic0 + deprecated: true + description: For the QEMU virt machine only =20 reg: maxItems: 1 --=20 2.37.1 From nobody Sat Apr 11 00:44:30 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C7520C32772 for ; Tue, 23 Aug 2022 19:37:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232983AbiHWThp (ORCPT ); Tue, 23 Aug 2022 15:37:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60828 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232054AbiHWThS (ORCPT ); Tue, 23 Aug 2022 15:37:18 -0400 Received: from mail-wm1-x330.google.com (mail-wm1-x330.google.com [IPv6:2a00:1450:4864:20::330]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D68FD98CAC for ; Tue, 23 Aug 2022 11:33:59 -0700 (PDT) Received: by mail-wm1-x330.google.com with SMTP id l33-20020a05600c1d2100b003a645240a95so5838602wms.1 for ; Tue, 23 Aug 2022 11:33:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=conchuod.ie; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=zfZqIEnKLgqKdt6yEdOe5gINIOFbq6xfPYo5xvbrixM=; b=f5pjcIK+H2mtPPE5b3VybQ5o01iECTvnw1E+28BxIUWO/6RjUzl2PBeS9opQx/sJtx yG2ysXoQtSd7WBzuZMOdXnT8YJjxr3vYR5+T/JX7WViSSLLzyWulBQl9Ko9BJ17LqXeZ ETGaCTo5yarZMm+oslfXmcNAi4epItnAZqaBYIMkIQm0At1DRkfT+iDb+SfVqSxBugml /5ZzzSEfTKoyNJSdvCwfE6CeTnMSICRVyM7qDc7zTPhZyBfqGkmjUnvVx/itr2tPYaA8 ONtGo4StZVjqqloFXAtoKHXtIcn38GlQfWO7p9BYujiPWphKMNU0v9xU6g0zgzl9njmI LYZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=zfZqIEnKLgqKdt6yEdOe5gINIOFbq6xfPYo5xvbrixM=; b=rzkhJi8y8xJc/JzV5ZwxDMMAnZUmRn6111A6pf/8MUbX2xLfqeWZeJEYnbWZXnBZnV HtzQtCojRWLSC+wcwbA+obhN/Sn+hqrcPD6ZcVPyc2j8P+e6qlU930YLjwxxl7G0ekqB QiOv/4sshcaooBU6iALHyAUP/GIh9uFxZ0MfddOJmPr2SolnGt9SrvnI22bTC2BFnd0h ABJ9alE5oj+e7S+7qRO+F8myS5dauNTLqzJEK/fwXnmfOjKEBSyvnAnJLFnYKBnZ6JDF 0U1vntrwWHo7hlo4xD+9AQ5Wn11B0UrnPmAD8gX3AVdkHppXmQzw8DrHVyTgZOgAOdma q8rg== X-Gm-Message-State: ACgBeo2pzLL1ARKQ+5b0e24nmuBjcr+Dw6dP0/5MHFC0hARfFK5BFI9e Pti1ZXX3T+l0vkvo96fKfN2CUQ== X-Google-Smtp-Source: AA6agR5eS5/PKXnK5uN2L+sdbkehjdJJ73byQpKpkqsyKD/rDgN0AG98DD6sac0atiQVprDQeVTQwA== X-Received: by 2002:a1c:c91a:0:b0:3a6:38bf:2c36 with SMTP id f26-20020a1cc91a000000b003a638bf2c36mr3062339wmb.38.1661279637684; Tue, 23 Aug 2022 11:33:57 -0700 (PDT) Received: from henark71.. ([51.37.149.245]) by smtp.gmail.com with ESMTPSA id p16-20020a05600c1d9000b003a5fcae64d4sm19396556wms.29.2022.08.23.11.33.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Aug 2022 11:33:57 -0700 (PDT) From: Conor Dooley To: Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Palmer Dabbelt , Paul Walmsley , Albert Ou Cc: Daniel Lezcano , Anup Patel , Conor Dooley , Guo Ren , Sagar Kadam , Jessica Clarke , Andrew Jones , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, qemu-riscv@nongnu.org, Rob Herring Subject: [PATCH v4 3/4] dt-bindings: riscv: add new riscv,isa strings for emulators Date: Tue, 23 Aug 2022 19:33:19 +0100 Message-Id: <20220823183319.3314940-4-mail@conchuod.ie> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220823183319.3314940-1-mail@conchuod.ie> References: <20220823183319.3314940-1-mail@conchuod.ie> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Conor Dooley The QEMU virt and spike machines currently export a riscv,isa string of "rv64imafdcsuh", While the RISC-V foundation has been ratifying a bunch of extenstions etc, the kernel has remained relatively static with what hardware is supported - but the same is not true of QEMU. Using the virt machine and running dt-validate on the dumped dtb fails, partly due to the unexpected isa string. Rather than enumerate the many many possbilities, change the pattern to a regex, with the following assumptions: - ima are required - the single letter order is fixed & we don't care about things that can't even do "ima" - the standard multi letter extensions are all in a "_z" format where the first letter of is a valid single letter extension - _s & _h are used for supervisor and hyper visor extensions - convention says that after the first two chars, a standard multi letter extension name could be an english word (ifencei anyone?) so it's not worth restricting the charset - as the above is just convention, don't apply any charset restrictions to reduce future churn - vendor ISA extensions begind with _x and have no charset restrictions - we don't care about an e extension from an OS pov - that attempting to validate the contents of the multiletter extensions with dt-validate beyond the formatting is a futile, massively verbose or unwieldy exercise at best The following limitations also apply: - multi letter extension ordering is not enforced. dt-schema does not appear to allow for named match groups, so the resulting regex would be even more of a headache - ditto for the numbered extensions Finally, add me as a maintainer of the binding so that when it breaks in the future, I can be held responsible! Reported-by: Rob Herring Link: https://lore.kernel.org/linux-riscv/20220803170552.GA2250266-robh@ker= nel.org/ Reviewed-by: Andrew Jones Acked-by: Guo Ren Signed-off-by: Conor Dooley Acked-by: Heiko Stuebner Reviewed-by: Rob Herring --- Palmer, feel free to drop the maintainer addition. I just mostly want to clean up my own mess on this when they decide to ratify more extensions & this comes back up again. --- Documentation/devicetree/bindings/riscv/cpus.yaml | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentat= ion/devicetree/bindings/riscv/cpus.yaml index 873dd12f6e89..90a7cabf58fe 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -9,6 +9,7 @@ title: RISC-V bindings for 'cpus' DT nodes maintainers: - Paul Walmsley - Palmer Dabbelt + - Conor Dooley =20 description: | This document uses some terminology common to the RISC-V community @@ -79,9 +80,7 @@ properties: insensitive, letters in the riscv,isa string must be all lowercase to simplify parsing. $ref: "/schemas/types.yaml#/definitions/string" - enum: - - rv64imac - - rv64imafdc + pattern: ^rv(?:64|32)imaf?d?q?c?b?v?k?h?(?:_[hsxz](?:[a-z])+)*$ =20 # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here timebase-frequency: false --=20 2.37.1 From nobody Sat Apr 11 00:44:30 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C9C57C32772 for ; Tue, 23 Aug 2022 19:37:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233163AbiHWThw (ORCPT ); Tue, 23 Aug 2022 15:37:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56646 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232740AbiHWThV (ORCPT ); Tue, 23 Aug 2022 15:37:21 -0400 Received: from mail-wm1-x32e.google.com (mail-wm1-x32e.google.com [IPv6:2a00:1450:4864:20::32e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 07D8799B43 for ; Tue, 23 Aug 2022 11:34:00 -0700 (PDT) Received: by mail-wm1-x32e.google.com with SMTP id m17-20020a7bce11000000b003a5bedec07bso10115310wmc.0 for ; Tue, 23 Aug 2022 11:34:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=conchuod.ie; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=trv5fw0bTaRkhXK0X5euU+YZQIdt/hyNEtAW//ypjq4=; b=SbIqnUkCy+xr3G4o41X6O/3K6TdfRJnovS+CTSQDtTxCHC12Dr2hCrLWJb14TBsmL7 lWBETJqBGmVPBNTdzb6i97jcciKXvfliHjaVH2WvuQDtdYipzwkytutPbIAoRIhAlXcN BiUQCaIU6+VbOthEftP+Vl5EKnyq3nQH7aRyPJyD0Y8TQ4TQ3IDh9NPwlGGsozrUWCfJ 9gJrSfEZ9qukTVfG9ziZNXXLqbGpMFLs9oyc3pV7HHO2bLKvpzURDQZwqzvXfExw+900 uPyd0qqVtAXIkJRBgKgUTRT7eIJaxdLAebLlBN7VwstK5T3aghNRMyNfOP/6qHrT223r mFdQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=trv5fw0bTaRkhXK0X5euU+YZQIdt/hyNEtAW//ypjq4=; b=eX5snUNLxr7aGaLoxotNjf6KqTD1pD8TsDX5LkjhjUir22ph4CTROqgqhzN1kL4gCX oPkHY1u29YIn6/XIp9i1Elu+x7EurSZ5h4neSYy+XrnOLOfIJjIRVtHRVnUPgnTJxZ5z Sh5BdzXipLdGuy7ebiVxGk8HWeCkveQ3Kyt0l2EvSEnat+2sBCDYfHkYtWi/P/Qw337E R5cc30Ns3au7EQJ2Z/wR35ti30wlLX+dQkZN8dx6YEaqZuUySnv4tARlLI3Jirs9uPdL bAzkEUlib924+UwheO+JIovOlx1QUtZGBj749r7bNVquk/vMDCxD8gumpPfk9goZKu8k JXkA== X-Gm-Message-State: ACgBeo0DN01wIvmatuI+9txJkLiY8KD48Ty3YuecQtqn+OIqVqJfvnbi VyVmjH8siSPyGdrxh+bSQYoDfw== X-Google-Smtp-Source: AA6agR5PsHa/f15Jc+wTtB6380Zen3xwCl+1v7C+oWEpfdzbxeubJb/sNC5ucLm5tjbY479QnKQpqg== X-Received: by 2002:a05:600c:3b92:b0:3a6:5645:5fc7 with SMTP id n18-20020a05600c3b9200b003a656455fc7mr2978623wms.148.1661279638941; Tue, 23 Aug 2022 11:33:58 -0700 (PDT) Received: from henark71.. ([51.37.149.245]) by smtp.gmail.com with ESMTPSA id p16-20020a05600c1d9000b003a5fcae64d4sm19396556wms.29.2022.08.23.11.33.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Aug 2022 11:33:58 -0700 (PDT) From: Conor Dooley To: Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Palmer Dabbelt , Paul Walmsley , Albert Ou Cc: Daniel Lezcano , Anup Patel , Conor Dooley , Guo Ren , Sagar Kadam , Jessica Clarke , Andrew Jones , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, qemu-riscv@nongnu.org Subject: [PATCH v4 4/4] dt-bindings: riscv: isa string bonus content Date: Tue, 23 Aug 2022 19:33:20 +0100 Message-Id: <20220823183319.3314940-5-mail@conchuod.ie> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220823183319.3314940-1-mail@conchuod.ie> References: <20220823183319.3314940-1-mail@conchuod.ie> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Conor Dooley **NOT FOR CONSIDERATION** I figured, sure why not add the strings for version number validation, just in case we need them in the future. The commented out string is considered by dt-schema to be "not a regex", but regex101 thinks it is... Maybe dt-schema does not support named match groups, but they are the only way that I could trivially find to make this somewhat manageable. Either way, it is permissive so it allows combinations of "M", "MpM" & no number. Not-signed-off-by: Conor Dooley --- Documentation/devicetree/bindings/riscv/cpus.yaml | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentat= ion/devicetree/bindings/riscv/cpus.yaml index 90a7cabf58fe..6c725d067846 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -80,7 +80,11 @@ properties: insensitive, letters in the riscv,isa string must be all lowercase to simplify parsing. $ref: "/schemas/types.yaml#/definitions/string" - pattern: ^rv(?:64|32)imaf?d?q?c?b?v?k?h?(?:_[hsxz](?:[a-z])+)*$ + oneOf: + - pattern: ^rv(?:64|32)imaf?d?q?c?b?v?k?h?(?:_[hsxz](?:[a-z])+)*$ + - pattern: ^rv(?:64|32)(?:i\d+)(?:m\d+)(?:a\d+)(?:f\d+)?(?:d\d+)?(?:= q\d+)?(?:c\d+)?(?:b\d+)?(?:v\d+)?(?:k\d+)?(?:h\d+)?(?:(?:_[zsh][imafdqcbvks= h]|_x)(?:[a-z])+\d+)*$ + - pattern: ^rv(?:64|32)(?:i\d+p\d+)(?:m\d+p\d+)(?:a\d+p\d+)(?:f\d+p\= d+)?(?:d\d+p\d+)?(?:q\d+p\d+)?(?:c\d+p\d+)?(?:b\d+p\d+)?(?:v\d+p\d+)?(?:k\d= +p\d+)?(?:h\d+p\d+)?(?:(?:_[zsh][imafdqcbvksh]|_x)(?:[a-z])+(?:\d+p\d+))*$ +# - pattern: ^rv(?:64|32)(?:i(?(?:\d+|\d+p\d+)?)?)(?:m(?:\k= )?)(?:a(?:\k)?)(?:f(?:\k)?)?(?:d(?:\k)?)?(?:q(?:\k)?)?(= ?:c(?:\k)?)?(?:b(?:\k)?)?(?:v(?:\k)?)?(?:k(?:\k)?)?(?:h= (?:\k)?)?(?:(?:_[zsh][imafdqcbvksh]|_x)(?:[a-z])*(?:\d+|\d+p\d+)?)+$ =20 # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here timebase-frequency: false --=20 2.37.1