From nobody Sat Sep 27 20:23:25 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 768B4C32772 for ; Tue, 23 Aug 2022 09:53:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240783AbiHWJxX (ORCPT ); Tue, 23 Aug 2022 05:53:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41040 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1352024AbiHWJvJ (ORCPT ); Tue, 23 Aug 2022 05:51:09 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 02CD09E2DA; Tue, 23 Aug 2022 01:45:41 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 0B348614E7; Tue, 23 Aug 2022 08:44:38 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 12153C433D6; Tue, 23 Aug 2022 08:44:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1661244277; bh=yMB+nDLTD/CtAiCCGvVNDEAEOnYChjmtyxH/gkHlNcw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=RMVocivEfS3XOKQxK+DV5pyZAG3wwIT87OZic8gD0aEiDQ8dKDq3cYwN0+mE7d1LN bnxjEq6iu9rDH/YIJ8w6+PUkDBEP8+CaGWnn4yLqCskGNsjDzMdAFRkaV1jKwMoyuu tmHkaicekXJ0Ymv8jZXYT+lRkdr1eWisWHahxO7Y= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Jernej Skrabec , Heiko Stuebner , Samuel Holland , Linus Walleij Subject: [PATCH 5.15 066/244] pinctrl: sunxi: Add I/O bias setting for H6 R-PIO Date: Tue, 23 Aug 2022 10:23:45 +0200 Message-Id: <20220823080101.285051026@linuxfoundation.org> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220823080059.091088642@linuxfoundation.org> References: <20220823080059.091088642@linuxfoundation.org> User-Agent: quilt/0.67 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Samuel Holland commit fc153c8f283bf5925615195fc9d4056414d7b168 upstream. H6 requires I/O bias configuration on both of its PIO devices. Previously it was only done for the main PIO. The setting for Port L is at bit 0, so the bank calculation needs to account for the pin base. Otherwise the wrong bit is used. Fixes: cc62383fcebe ("pinctrl: sunxi: Support I/O bias voltage setting on H= 6") Reviewed-by: Jernej Skrabec Tested-by: Heiko Stuebner Signed-off-by: Samuel Holland Link: https://lore.kernel.org/r/20220713025233.27248-3-samuel@sholland.org Signed-off-by: Linus Walleij Signed-off-by: Greg Kroah-Hartman --- drivers/pinctrl/sunxi/pinctrl-sun50i-h6-r.c | 1 + drivers/pinctrl/sunxi/pinctrl-sunxi.c | 7 ++++--- 2 files changed, 5 insertions(+), 3 deletions(-) --- a/drivers/pinctrl/sunxi/pinctrl-sun50i-h6-r.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-h6-r.c @@ -107,6 +107,7 @@ static const struct sunxi_pinctrl_desc s .npins =3D ARRAY_SIZE(sun50i_h6_r_pins), .pin_base =3D PL_BASE, .irq_banks =3D 2, + .io_bias_cfg_variant =3D BIAS_VOLTAGE_PIO_POW_MODE_SEL, }; =20 static int sun50i_h6_r_pinctrl_probe(struct platform_device *pdev) --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c @@ -624,7 +624,7 @@ static int sunxi_pinctrl_set_io_bias_cfg unsigned pin, struct regulator *supply) { - unsigned short bank =3D pin / PINS_PER_BANK; + unsigned short bank; unsigned long flags; u32 val, reg; int uV; @@ -640,6 +640,9 @@ static int sunxi_pinctrl_set_io_bias_cfg if (uV =3D=3D 0) return 0; =20 + pin -=3D pctl->desc->pin_base; + bank =3D pin / PINS_PER_BANK; + switch (pctl->desc->io_bias_cfg_variant) { case BIAS_VOLTAGE_GRP_CONFIG: /* @@ -657,8 +660,6 @@ static int sunxi_pinctrl_set_io_bias_cfg else val =3D 0xD; /* 3.3V */ =20 - pin -=3D pctl->desc->pin_base; - reg =3D readl(pctl->membase + sunxi_grp_config_reg(pin)); reg &=3D ~IO_BIAS_MASK; writel(reg | val, pctl->membase + sunxi_grp_config_reg(pin));