From nobody Wed Apr 8 06:10:14 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B1313C28D13 for ; Tue, 23 Aug 2022 00:16:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238894AbiHWAQ4 (ORCPT ); Mon, 22 Aug 2022 20:16:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51534 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238784AbiHWAQr (ORCPT ); Mon, 22 Aug 2022 20:16:47 -0400 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 692DE22A for ; Mon, 22 Aug 2022 17:16:46 -0700 (PDT) Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 27N0GabP084538; Mon, 22 Aug 2022 19:16:36 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1661213796; bh=IXS3eOpGeVTQhnzmRvwBTKZZwv0GAWdYS0tpv7glTv4=; h=From:To:CC:Subject:Date; b=CtsjRT6KqXspxbsq858IDz7DOMgcoMVGPp6gP4znuKH7oUCscQ44v0V13Q7m17q6d zAiVkVVC77V6A3g1BanAqh70jA63g4Duiz6sh6ZFRwlwoTPt7YsrmWyHP9L3ZHFvR0 EZRLmt7CEefrLTaPKti+JhzypQ9ebPnj0AIJBNS8= Received: from DFLE113.ent.ti.com (dfle113.ent.ti.com [10.64.6.34]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 27N0GZqC018842 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 22 Aug 2022 19:16:36 -0500 Received: from DFLE102.ent.ti.com (10.64.6.23) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6; Mon, 22 Aug 2022 19:16:35 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6 via Frontend Transport; Mon, 22 Aug 2022 19:16:35 -0500 Received: from ula0226330.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 27N0GZ0u007537; Mon, 22 Aug 2022 19:16:35 -0500 From: Andrew Davis To: David Airlie , Daniel Vetter , Tomi Valkeinen , Jyri Sarha , , CC: Andrew Davis Subject: [PATCH] drm/tidss: Set max DMA segment size Date: Mon, 22 Aug 2022 19:16:34 -0500 Message-ID: <20220823001634.11461-1-afd@ti.com> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" We have no segment size limitations. Set to unlimited. Signed-off-by: Andrew Davis --- drivers/gpu/drm/tidss/tidss_dispc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/ti= dss_dispc.c index dd3c6a606ae2..624545e4636c 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.c +++ b/drivers/gpu/drm/tidss/tidss_dispc.c @@ -2685,6 +2685,7 @@ int dispc_init(struct tidss_device *tidss) if (r) dev_warn(dev, "cannot set DMA masks to 48-bit\n"); } + dma_set_max_seg_size(dev, UINT_MAX); =20 dispc =3D devm_kzalloc(dev, sizeof(*dispc), GFP_KERNEL); if (!dispc) --=20 2.36.1