From nobody Sat Sep 21 17:01:14 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B43A1C28D13 for ; Mon, 22 Aug 2022 14:47:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235488AbiHVOr0 (ORCPT ); Mon, 22 Aug 2022 10:47:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34480 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235474AbiHVOpY (ORCPT ); Mon, 22 Aug 2022 10:45:24 -0400 Received: from mail-wr1-x434.google.com (mail-wr1-x434.google.com [IPv6:2a00:1450:4864:20::434]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 85F7925589 for ; Mon, 22 Aug 2022 07:45:23 -0700 (PDT) Received: by mail-wr1-x434.google.com with SMTP id h5so12705647wru.7 for ; Mon, 22 Aug 2022 07:45:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=hDgzoGfvkSJprn1pVjh45rvsUgwFKfwgOyRxpaD3tAs=; b=uV6WZ94rfyaXVoUh/a3cSluphqUec+lYu1z+0VkR3Tm4ro//0CSirXWFgW68u3rQa5 Nzc8DnBaHh0WNcqiTCGoWa7wJFzAtwym3pDqM67pa7R/q7WWv7JL5X4JHfMYs12dAplF sEw9sqvvka4ViiNqO52p1bN7LbOUI4bPeVT3GQDJY8ZwthfGdPnPmc0Tevx5d/0UQ445 OE6c3HA9Lbu4NlF+24ZSHs1V9fZ1tzzUO9a6Ma+2brbjykei70MHWoss9Pb1vVCuqIgh bTHQbUGqPzHsgMxFECQpuzhSFmbZVBvM8Bc9GP7QJDuJxslgeVLgg2AyaEMnpHxEVPhL OZGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=hDgzoGfvkSJprn1pVjh45rvsUgwFKfwgOyRxpaD3tAs=; b=BzQBK9+ieFpDAKyF07I7WF3C6yku/hHlaNP8QeMeUUcNiA/0JC/txdMszR9K5D8ta7 1VY8mMO74Ln9tFWEA5wlXzXgCMLbBdjx3aHfg9jhEzjuARszc1AVd8EgDKo8BWMFDtze /I5PbY1cNdkpCNQNFw6IqkQGGeNWOL3A5NPPChjgndUHImfh42MI5gw1jznF7XAzOHeT dNf/F7SvGuHHofNMd0a1RP9FglCSemzfeysy6OHo6xXRzMCRmDASrgKT92jVG+qyNnB9 BcYvLB2m7WBawZId4P8JiBO4zDzFOgIusNHGnZCyb4MKYYnugKakLOEieztK5KfpyMT2 iPhw== X-Gm-Message-State: ACgBeo2oofP2NxHDT/bVzbCpmu4dUr4Da4btfSFFWmJs7TABvKfEq/h8 aZmNlIVaUvCQimPJfp7rVhAdOw== X-Google-Smtp-Source: AA6agR5fjdsY02I9D0DN/Zu7mCPzLbITeHSwG+mjAqQHFtmzGXS7a6CE8dStN62WGowvrhmAMz043A== X-Received: by 2002:adf:eb50:0:b0:21e:3d13:3a91 with SMTP id u16-20020adfeb50000000b0021e3d133a91mr10682767wrn.484.1661179521924; Mon, 22 Aug 2022 07:45:21 -0700 (PDT) Received: from blmsp.fritz.box ([2001:4090:a245:8020:2658:1f7c:362:3e99]) by smtp.gmail.com with ESMTPSA id z24-20020a1cf418000000b003a5dadcf1a8sm14670935wma.19.2022.08.22.07.45.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 07:45:21 -0700 (PDT) From: Markus Schneider-Pargmann To: Rob Herring , Krzysztof Kozlowski , Matthias Brugger Cc: Chun-Jie Chen , AngeloGioacchino Del Regno , Fabien Parent , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Fabien Parent , Markus Schneider-Pargmann Subject: [PATCH v3 1/4] dt-bindings: power: Add MT8365 power domains Date: Mon, 22 Aug 2022 16:43:00 +0200 Message-Id: <20220822144303.3438467-2-msp@baylibre.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220822144303.3438467-1-msp@baylibre.com> References: <20220822144303.3438467-1-msp@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Fabien Parent Add power domains dt-bindings for MT8365. Signed-off-by: Fabien Parent Signed-off-by: Markus Schneider-Pargmann Acked-by: Krzysztof Kozlowski --- Notes: Changes in v3: - Renamed mt8365-power.h to mediatek,mt8365-power.h =20 Changes in v2: - Made include/dt-bindings/power/mt8365-power.h dual-license. .../power/mediatek,power-controller.yaml | 2 ++ .../dt-bindings/power/mediatek,mt8365-power.h | 19 +++++++++++++++++++ 2 files changed, 21 insertions(+) create mode 100644 include/dt-bindings/power/mediatek,mt8365-power.h diff --git a/Documentation/devicetree/bindings/power/mediatek,power-control= ler.yaml b/Documentation/devicetree/bindings/power/mediatek,power-controlle= r.yaml index b448101fac43..a8702706dae4 100644 --- a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml +++ b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml @@ -30,6 +30,7 @@ properties: - mediatek,mt8186-power-controller - mediatek,mt8192-power-controller - mediatek,mt8195-power-controller + - mediatek,mt8365-power-controller =20 '#power-domain-cells': const: 1 @@ -69,6 +70,7 @@ patternProperties: "include/dt-bindings/power/mt8183-power.h" - for MT8183 type= power domain. "include/dt-bindings/power/mt8192-power.h" - for MT8192 type= power domain. "include/dt-bindings/power/mt8195-power.h" - for MT8195 type= power domain. + "include/dt-bindings/power/mediatek,mt8365-power.h" - for MT= 8365 type power domain. maxItems: 1 =20 clocks: diff --git a/include/dt-bindings/power/mediatek,mt8365-power.h b/include/dt= -bindings/power/mediatek,mt8365-power.h new file mode 100644 index 000000000000..e6cfd0ec7871 --- /dev/null +++ b/include/dt-bindings/power/mediatek,mt8365-power.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* + * Copyright (c) 2022 MediaTek Inc. + */ + +#ifndef _DT_BINDINGS_POWER_MT8365_POWER_H +#define _DT_BINDINGS_POWER_MT8365_POWER_H + +#define MT8365_POWER_DOMAIN_MM 0 +#define MT8365_POWER_DOMAIN_CONN 1 +#define MT8365_POWER_DOMAIN_MFG 2 +#define MT8365_POWER_DOMAIN_AUDIO 3 +#define MT8365_POWER_DOMAIN_CAM 4 +#define MT8365_POWER_DOMAIN_DSP 5 +#define MT8365_POWER_DOMAIN_VDEC 6 +#define MT8365_POWER_DOMAIN_VENC 7 +#define MT8365_POWER_DOMAIN_APU 8 + +#endif /* _DT_BINDINGS_POWER_MT8365_POWER_H */ --=20 2.37.2 From nobody Sat Sep 21 17:01:14 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B70BDC3F6B0 for ; Mon, 22 Aug 2022 14:47:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235777AbiHVOqJ (ORCPT ); Mon, 22 Aug 2022 10:46:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34506 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235492AbiHVOpZ (ORCPT ); Mon, 22 Aug 2022 10:45:25 -0400 Received: from mail-wr1-x42e.google.com (mail-wr1-x42e.google.com [IPv6:2a00:1450:4864:20::42e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AF9A82A72A for ; Mon, 22 Aug 2022 07:45:24 -0700 (PDT) Received: by mail-wr1-x42e.google.com with SMTP id e20so13017997wri.13 for ; Mon, 22 Aug 2022 07:45:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=a1iZXrIX4OxA2n5vEsq07pYhl7rKDCQYXsxiPHsCM2g=; b=0RTdnvWOtoD2zIozW9cq9CoU0b0VpvHqXpLv+o61LFYHt0pXq97w2/1Lphq6aLyCU5 9q8QmkH/ZRKnPZXQ8uB5KPHu0izM0A/K3/PRlLXUUdaUfMoKSxbBIVN5OgIrH+WSFscc aklmxjsAkMobKiNtrOXwLH5nalhThb49GTSuh+VYdYkohIVk1ddkgHPVHmAXvhFptUhU 5hrgoC5M23ndnQESF2AnE8YpwQLX7woD1Cg0kEn8GoNxVHEeXdWPGYIxq0zQ7JnlsMHG nuL+FlXCiEC+ohia/ZOFfVK+I4R6rB3pUHD/0o68L3m1QFRzuhFtNOT4xbKrWaI3mDco gSmg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=a1iZXrIX4OxA2n5vEsq07pYhl7rKDCQYXsxiPHsCM2g=; b=K/Y/KiQhBfojIxhxd4ZJakorGs7QxaEgmCWGqCjoA3TZ1xW7ecwZZcmbyZihvvitY1 /lcyCCArkGWROZ7Mpbxm2JxIzRKX+ACwXgbjy/9/4TkZoIa4VJRE1QQoSJgcA6kvAhjy uEQwJfbm1Zvof/I7ng0v+RC/Pc8JZ1ZupkPse5gxlia3ABS+aCC2c/wzOaGqNmrwJkxv wWhWSJTBrMXjRXxUyAJdzgCej4vtAuBVtUvUuYwCYolgz53UCRk/YD0OhKFkH4xpWEJ4 tpyDeZP1vCcIMOMH92vDhpeIc99qZhjQxX72DZRx0LvrKrqne86UqsW+IPlPsLrEnC2v 7h+Q== X-Gm-Message-State: ACgBeo3Km0h9sAToe32ujeKHNYf/iNQ1KiFlcfOeqzxJvUAeKvh++kTp NPepvoA2MP6LULyMKEpN3spbVA== X-Google-Smtp-Source: AA6agR4qIR/Ei3WdW/ukb1I60l3z+3Vd1HGBT8z/XvP7Y6+oaR9FtidHTw7VxajFqH/a/F5o3FLtzg== X-Received: by 2002:a5d:61c7:0:b0:225:307b:b557 with SMTP id q7-20020a5d61c7000000b00225307bb557mr10225664wrv.402.1661179523150; Mon, 22 Aug 2022 07:45:23 -0700 (PDT) Received: from blmsp.fritz.box ([2001:4090:a245:8020:2658:1f7c:362:3e99]) by smtp.gmail.com with ESMTPSA id z24-20020a1cf418000000b003a5dadcf1a8sm14670935wma.19.2022.08.22.07.45.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 07:45:22 -0700 (PDT) From: Markus Schneider-Pargmann To: Rob Herring , Krzysztof Kozlowski , Matthias Brugger Cc: Chun-Jie Chen , AngeloGioacchino Del Regno , Fabien Parent , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Alexandre Bailon , Fabien Parent , Markus Schneider-Pargmann Subject: [PATCH v3 2/4] soc: mediatek: Add support of WAY_EN operations Date: Mon, 22 Aug 2022 16:43:01 +0200 Message-Id: <20220822144303.3438467-3-msp@baylibre.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220822144303.3438467-1-msp@baylibre.com> References: <20220822144303.3438467-1-msp@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Alexandre Bailon This updates the power domain to support WAY_EN operations. These operations enable a path between different units of the chip and are labeled as 'way_en' in the register descriptions. This operation is required by the mt8365 for the MM power domain. Signed-off-by: Alexandre Bailon Signed-off-by: Fabien Parent Signed-off-by: Markus Schneider-Pargmann --- Notes: Changes in v3: - Separated the way_en functions for clarity - Added some checks for infracfg_nao =20 Changes in v2: - some minor style fixes. - Renamed 'wayen' to 'way_en' to clarify the meaning - Updated commit message drivers/soc/mediatek/mtk-pm-domains.c | 162 +++++++++++++++++++++----- drivers/soc/mediatek/mtk-pm-domains.h | 28 +++-- 2 files changed, 149 insertions(+), 41 deletions(-) diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/m= tk-pm-domains.c index 9734f1091c69..c2cbe0de6aa1 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.c +++ b/drivers/soc/mediatek/mtk-pm-domains.c @@ -43,6 +43,7 @@ struct scpsys_domain { struct clk_bulk_data *clks; int num_subsys_clks; struct clk_bulk_data *subsys_clks; + struct regmap *infracfg_nao; struct regmap *infracfg; struct regmap *smi; struct regulator *supply; @@ -117,26 +118,61 @@ static int scpsys_sram_disable(struct scpsys_domain *= pd) MTK_POLL_TIMEOUT); } =20 -static int _scpsys_bus_protect_enable(const struct scpsys_bus_prot_data *b= pd, struct regmap *regmap) +static int __scpsys_bus_protect_enable(const struct scpsys_bus_prot_data *= bpd, + struct regmap *regmap) +{ + u32 val; + u32 mask =3D bpd->bus_prot_mask; + u32 sta_mask =3D bpd->bus_prot_sta_mask; + + if (bpd->bus_prot_reg_update) + regmap_set_bits(regmap, bpd->bus_prot_set, mask); + else + regmap_write(regmap, bpd->bus_prot_set, mask); + + return regmap_read_poll_timeout(regmap, bpd->bus_prot_sta, val, + (val & sta_mask) =3D=3D sta_mask, + MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); +} + +static int scpsys_bus_way_disable(const struct scpsys_bus_prot_data *bpd, + struct regmap *regmap, + struct regmap *ack_regmap) +{ + u32 val; + u32 mask =3D bpd->bus_prot_mask; + u32 sta_mask =3D bpd->bus_prot_sta_mask; + + if (bpd->bus_prot_reg_update) + regmap_clear_bits(regmap, bpd->bus_prot_set, mask); + else + regmap_write(regmap, bpd->bus_prot_set, mask); + + if (bpd->ignore_clr_ack) + return 0; + + return regmap_read_poll_timeout(ack_regmap, bpd->bus_prot_sta, val, + (val & sta_mask) =3D=3D sta_mask, + MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); +} + +static int _scpsys_bus_protect_enable(const struct scpsys_bus_prot_data *b= pd, + struct regmap *regmap, struct regmap *infracfg_nao) { int i, ret; =20 for (i =3D 0; i < SPM_MAX_BUS_PROT_DATA; i++) { - u32 val, mask =3D bpd[i].bus_prot_mask; - - if (!mask) + if (!bpd[i].bus_prot_mask) break; =20 - if (bpd[i].bus_prot_reg_update) - regmap_set_bits(regmap, bpd[i].bus_prot_set, mask); + if (bpd[i].way_en) + ret =3D scpsys_bus_way_disable(&bpd[i], regmap, infracfg_nao); else - regmap_write(regmap, bpd[i].bus_prot_set, mask); - - ret =3D regmap_read_poll_timeout(regmap, bpd[i].bus_prot_sta, - val, (val & mask) =3D=3D mask, - MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); - if (ret) + ret =3D __scpsys_bus_protect_enable(&bpd[i], regmap); + if (ret) { + pr_err("%s %d %d\n", __PRETTY_FUNCTION__, __LINE__, ret); return ret; + } } =20 return 0; @@ -146,37 +182,71 @@ static int scpsys_bus_protect_enable(struct scpsys_do= main *pd) { int ret; =20 - ret =3D _scpsys_bus_protect_enable(pd->data->bp_infracfg, pd->infracfg); + ret =3D _scpsys_bus_protect_enable(pd->data->bp_infracfg, + pd->infracfg, pd->infracfg_nao); if (ret) return ret; =20 - return _scpsys_bus_protect_enable(pd->data->bp_smi, pd->smi); + return _scpsys_bus_protect_enable(pd->data->bp_smi, pd->smi, NULL); +} + +static int __scpsys_bus_protect_disable(const struct scpsys_bus_prot_data = *bpd, + struct regmap *regmap) +{ + u32 val; + u32 mask =3D bpd->bus_prot_mask; + u32 sta_mask =3D bpd->bus_prot_sta_mask; + + if (bpd->bus_prot_reg_update) + regmap_clear_bits(regmap, bpd->bus_prot_clr, mask); + else + regmap_write(regmap, bpd->bus_prot_clr, mask); + + if (bpd->ignore_clr_ack) + return 0; + + return regmap_read_poll_timeout(regmap, bpd->bus_prot_sta, val, + !(val & sta_mask), MTK_POLL_DELAY_US, + MTK_POLL_TIMEOUT); +} + +static int scpsys_bus_way_enable(const struct scpsys_bus_prot_data *bpd, + struct regmap *regmap, + struct regmap *ack_regmap) +{ + u32 val; + u32 mask =3D bpd->bus_prot_mask; + u32 sta_mask =3D bpd->bus_prot_sta_mask; + + if (bpd->bus_prot_reg_update) + regmap_set_bits(regmap, bpd->bus_prot_clr, mask); + else + regmap_write(regmap, bpd->bus_prot_clr, mask); + + return regmap_read_poll_timeout(ack_regmap, bpd->bus_prot_sta, val, + (val & sta_mask) =3D=3D sta_mask, + MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); } =20 static int _scpsys_bus_protect_disable(const struct scpsys_bus_prot_data *= bpd, - struct regmap *regmap) + struct regmap *regmap, + struct regmap *infracfg_nao) { int i, ret; =20 for (i =3D SPM_MAX_BUS_PROT_DATA - 1; i >=3D 0; i--) { - u32 val, mask =3D bpd[i].bus_prot_mask; - - if (!mask) + if (!bpd[i].bus_prot_mask) continue; =20 - if (bpd[i].bus_prot_reg_update) - regmap_clear_bits(regmap, bpd[i].bus_prot_clr, mask); + if (bpd[i].way_en) + ret =3D scpsys_bus_way_enable(&bpd[i], regmap, + infracfg_nao); else - regmap_write(regmap, bpd[i].bus_prot_clr, mask); - - if (bpd[i].ignore_clr_ack) - continue; - - ret =3D regmap_read_poll_timeout(regmap, bpd[i].bus_prot_sta, - val, !(val & mask), - MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); - if (ret) + ret =3D __scpsys_bus_protect_disable(&bpd[i], regmap); + if (ret) { + pr_err("%s %d %d\n", __PRETTY_FUNCTION__, __LINE__, ret); return ret; + } } =20 return 0; @@ -186,11 +256,12 @@ static int scpsys_bus_protect_disable(struct scpsys_d= omain *pd) { int ret; =20 - ret =3D _scpsys_bus_protect_disable(pd->data->bp_smi, pd->smi); + ret =3D _scpsys_bus_protect_disable(pd->data->bp_smi, pd->smi, NULL); if (ret) return ret; =20 - return _scpsys_bus_protect_disable(pd->data->bp_infracfg, pd->infracfg); + return _scpsys_bus_protect_disable(pd->data->bp_infracfg, + pd->infracfg, pd->infracfg_nao); } =20 static int scpsys_regulator_enable(struct regulator *supply) @@ -294,6 +365,21 @@ static int scpsys_power_off(struct generic_pm_domain *= genpd) return 0; } =20 +static bool scpsys_bp_infracfg_has_way_en(const struct scpsys_bus_prot_dat= a *bpd) +{ + int i; + + for (i =3D 0; i < SPM_MAX_BUS_PROT_DATA; i++) { + if (!bpd[i].bus_prot_mask) + break; + + if (bpd[i].way_en) + return true; + } + + return false; +} + static struct generic_pm_domain *scpsys_add_one_domain(struct scpsys *scpsys, struct dev= ice_node *node) { @@ -364,6 +450,20 @@ generic_pm_domain *scpsys_add_one_domain(struct scpsys= *scpsys, struct device_no return ERR_CAST(pd->smi); } =20 + if (scpsys_bp_infracfg_has_way_en(pd->data->bp_smi)) { + dev_err(scpsys->dev, "bp_smi does not support WAY_EN\n"); + return ERR_PTR(-EINVAL); + } + + pd->infracfg_nao =3D syscon_regmap_lookup_by_phandle_optional( + node, "mediatek,infracfg_nao"); + if (IS_ERR(pd->infracfg_nao)) { + if (scpsys_bp_infracfg_has_way_en(pd->data->bp_infracfg)) + return ERR_CAST(pd->infracfg_nao); + + pd->infracfg_nao =3D NULL; + } + num_clks =3D of_clk_get_parent_count(node); if (num_clks > 0) { /* Calculate number of subsys_clks */ diff --git a/drivers/soc/mediatek/mtk-pm-domains.h b/drivers/soc/mediatek/m= tk-pm-domains.h index 7d3c0c36316c..974c68a1d89c 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.h +++ b/drivers/soc/mediatek/mtk-pm-domains.h @@ -41,23 +41,29 @@ =20 #define SPM_MAX_BUS_PROT_DATA 6 =20 -#define _BUS_PROT(_mask, _set, _clr, _sta, _update, _ignore) { \ - .bus_prot_mask =3D (_mask), \ - .bus_prot_set =3D _set, \ - .bus_prot_clr =3D _clr, \ - .bus_prot_sta =3D _sta, \ - .bus_prot_reg_update =3D _update, \ - .ignore_clr_ack =3D _ignore, \ +#define _BUS_PROT(_mask, _sta_mask, _set, _clr, _sta, _update, _ignore, _w= ay_en) { \ + .bus_prot_mask =3D (_mask), \ + .bus_prot_set =3D _set, \ + .bus_prot_clr =3D _clr, \ + .bus_prot_sta =3D _sta, \ + .bus_prot_sta_mask =3D _sta_mask, \ + .bus_prot_reg_update =3D _update, \ + .ignore_clr_ack =3D _ignore, \ + .way_en =3D _way_en, \ } =20 #define BUS_PROT_WR(_mask, _set, _clr, _sta) \ - _BUS_PROT(_mask, _set, _clr, _sta, false, false) + _BUS_PROT(_mask, _mask, _set, _clr, _sta, false, false, false) =20 #define BUS_PROT_WR_IGN(_mask, _set, _clr, _sta) \ - _BUS_PROT(_mask, _set, _clr, _sta, false, true) + _BUS_PROT(_mask, _mask, _set, _clr, _sta, false, true, false) =20 #define BUS_PROT_UPDATE(_mask, _set, _clr, _sta) \ - _BUS_PROT(_mask, _set, _clr, _sta, true, false) + _BUS_PROT(_mask, _mask, _set, _clr, _sta, true, false, false) + +#define BUS_PROT_WAY_EN(_en_mask, _sta_mask, _set, _sta) \ + _BUS_PROT(_en_mask, _sta_mask, _set, _set, _sta, true, false, \ + true) =20 #define BUS_PROT_UPDATE_TOPAXI(_mask) \ BUS_PROT_UPDATE(_mask, \ @@ -70,8 +76,10 @@ struct scpsys_bus_prot_data { u32 bus_prot_set; u32 bus_prot_clr; u32 bus_prot_sta; + u32 bus_prot_sta_mask; bool bus_prot_reg_update; bool ignore_clr_ack; + bool way_en; }; =20 /** --=20 2.37.2 From nobody Sat Sep 21 17:01:14 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 699DEC28D13 for ; Mon, 22 Aug 2022 14:47:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235701AbiHVOpv (ORCPT ); Mon, 22 Aug 2022 10:45:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34502 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235502AbiHVOp1 (ORCPT ); Mon, 22 Aug 2022 10:45:27 -0400 Received: from mail-wr1-x42b.google.com (mail-wr1-x42b.google.com [IPv6:2a00:1450:4864:20::42b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9F35A186E7 for ; Mon, 22 Aug 2022 07:45:25 -0700 (PDT) Received: by mail-wr1-x42b.google.com with SMTP id r16so13503676wrm.6 for ; Mon, 22 Aug 2022 07:45:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=bSMvzF6WPZ8nDQB+J28VbvrCg97cVH3Ebn5HDrB27ak=; b=m4y+Z+22JbZ0Ly6iBmFidAPZbkvp3PPRC8y3oYtfAFQ6zt8Qsv0eBQvfUmbwvpR5Fz 6FfER971HaLEhnRP4cPVeZI966k6CvgqRYCznu2N07D+STkzGsmBCWwAs27GojNTHxAb gfgGQK7gfmYhtspMaXzBNGZI8QN+iNbbEWfO1RD64+OxUeqMNHNXqtJWfrO1YBcgZvf/ ltLGBra18ZmCpSqLGVqMvGQr3CEgFaReGa7JDnqLUfwStl5qtHpUwTTTGLIKZQ+JRo2D SDXJAvjea+okphduoXudm34rEiqTE6SIaK/Nn5GnhZyUjgypTOvG5JnUFCysgq1kcBWA A+Lw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=bSMvzF6WPZ8nDQB+J28VbvrCg97cVH3Ebn5HDrB27ak=; b=j1PEzIMALhdAEMn67SRzQdAvG13QFn0CDBXSYDCEkk4uF3Mz3Ss3ilFk3bCExtFSTo 9I832XTptu4vElLwVjowp/rNWLEUkF1Dwk25XgX1oGrlp5qsvAPOlbmLaqaKKMIy7u7r ilnjFDnoXlTd14+SeDyrFQdr/4jrrtoJoE6S5PwdtotWzJFy7OndpMQSbNuJd3MlsEkd 4iTwEEsnnDht1fLQ/U3jQSBEpmMTj5Tw31Du/EBBdTtteyOM6B6mwV1LVt2KKXhJEaXi 3lk4lJSngIF65JH432v5O3oDz7XBfJFrhHY94d6Is2SuPgRLAEVcTHPlchYMV5bolQzV GzoQ== X-Gm-Message-State: ACgBeo12YYDQjEUno8RKk0PH7iuCJOr3XJqh3T0rNue7VbKqM/lvcj6V L84nuG0GtTLt+Xy9fMi+aq4C1A== X-Google-Smtp-Source: AA6agR5R6cBNc/betWL+bcg9LDkG0egcM3JtWWDX14j+emkuV8ZDXIYqm2augz26Mh+LKIlQ0llVbw== X-Received: by 2002:adf:dd0f:0:b0:225:1fd6:66d9 with SMTP id a15-20020adfdd0f000000b002251fd666d9mr11085044wrm.42.1661179524224; Mon, 22 Aug 2022 07:45:24 -0700 (PDT) Received: from blmsp.fritz.box ([2001:4090:a245:8020:2658:1f7c:362:3e99]) by smtp.gmail.com with ESMTPSA id z24-20020a1cf418000000b003a5dadcf1a8sm14670935wma.19.2022.08.22.07.45.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 07:45:23 -0700 (PDT) From: Markus Schneider-Pargmann To: Rob Herring , Krzysztof Kozlowski , Matthias Brugger Cc: Chun-Jie Chen , AngeloGioacchino Del Regno , Fabien Parent , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Alexandre Bailon , Fabien Parent , Markus Schneider-Pargmann Subject: [PATCH v3 3/4] soc: mediatek: add support of MTK_SCPD_STRICT_BUSP cap Date: Mon, 22 Aug 2022 16:43:02 +0200 Message-Id: <20220822144303.3438467-4-msp@baylibre.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220822144303.3438467-1-msp@baylibre.com> References: <20220822144303.3438467-1-msp@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Alexandre Bailon This adds support for MTK_SCPD_STRICT_BUSP capability. It is a strict bus protection policy that requires the bus protection to be disabled before accessing the bus. This is required by the mt8365, for the MM power domain. Signed-off-by: Alexandre Bailon Signed-off-by: Fabien Parent Signed-off-by: Markus Schneider-Pargmann --- Notes: Changes in v3: - Rename MTK_SCPD_STRICT_BUSP to MTK_SCPD_STRICT_BUS_PROTECTION - Remove extra bool variable reflecting the capability =20 Changes in v2: - Fixup error handling path. drivers/soc/mediatek/mtk-pm-domains.c | 27 +++++++++++++++++++++++---- drivers/soc/mediatek/mtk-pm-domains.h | 1 + 2 files changed, 24 insertions(+), 4 deletions(-) diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/m= tk-pm-domains.c index c2cbe0de6aa1..d323275aa11c 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.c +++ b/drivers/soc/mediatek/mtk-pm-domains.c @@ -303,9 +303,17 @@ static int scpsys_power_on(struct generic_pm_domain *g= enpd) regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_ISO_BIT); regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_RST_B_BIT); =20 - ret =3D clk_bulk_prepare_enable(pd->num_subsys_clks, pd->subsys_clks); - if (ret) - goto err_pwr_ack; + /* + * In few Mediatek platforms(e.g. MT6779), the bus protect policy is + * stricter, which leads to bus protect release must be prior to bus + * access. + */ + if (!MTK_SCPD_CAPS(pd, MTK_SCPD_STRICT_BUS_PROTECTION)) { + ret =3D clk_bulk_prepare_enable(pd->num_subsys_clks, + pd->subsys_clks); + if (ret) + goto err_pwr_ack; + } =20 ret =3D scpsys_sram_enable(pd); if (ret < 0) @@ -315,12 +323,23 @@ static int scpsys_power_on(struct generic_pm_domain *= genpd) if (ret < 0) goto err_disable_sram; =20 + if (MTK_SCPD_CAPS(pd, MTK_SCPD_STRICT_BUS_PROTECTION)) { + ret =3D clk_bulk_prepare_enable(pd->num_subsys_clks, + pd->subsys_clks); + if (ret) + goto err_enable_bus_protect; + } + return 0; =20 +err_enable_bus_protect: + scpsys_bus_protect_enable(pd); err_disable_sram: scpsys_sram_disable(pd); err_disable_subsys_clks: - clk_bulk_disable_unprepare(pd->num_subsys_clks, pd->subsys_clks); + if (!MTK_SCPD_CAPS(pd, MTK_SCPD_STRICT_BUS_PROTECTION)) + clk_bulk_disable_unprepare(pd->num_subsys_clks, + pd->subsys_clks); err_pwr_ack: clk_bulk_disable_unprepare(pd->num_clks, pd->clks); err_reg: diff --git a/drivers/soc/mediatek/mtk-pm-domains.h b/drivers/soc/mediatek/m= tk-pm-domains.h index 974c68a1d89c..493f3fa14612 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.h +++ b/drivers/soc/mediatek/mtk-pm-domains.h @@ -10,6 +10,7 @@ #define MTK_SCPD_DOMAIN_SUPPLY BIT(4) /* can't set MTK_SCPD_KEEP_DEFAULT_OFF at the same time */ #define MTK_SCPD_ALWAYS_ON BIT(5) +#define MTK_SCPD_STRICT_BUS_PROTECTION BIT(6) #define MTK_SCPD_CAPS(_scpd, _x) ((_scpd)->data->caps & (_x)) =20 #define SPM_VDE_PWR_CON 0x0210 --=20 2.37.2 From nobody Sat Sep 21 17:01:14 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A1FF5C32772 for ; Mon, 22 Aug 2022 14:47:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235758AbiHVOqH (ORCPT ); Mon, 22 Aug 2022 10:46:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34528 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235511AbiHVOp1 (ORCPT ); Mon, 22 Aug 2022 10:45:27 -0400 Received: from mail-wr1-x434.google.com (mail-wr1-x434.google.com [IPv6:2a00:1450:4864:20::434]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CF0CF24F06 for ; Mon, 22 Aug 2022 07:45:25 -0700 (PDT) Received: by mail-wr1-x434.google.com with SMTP id h5so12705872wru.7 for ; Mon, 22 Aug 2022 07:45:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=Dgr+R+Ooqj7O8IbEZN3k8kABePugAAeIHX9669QxJ80=; b=LXdfeBz4Yy+YTGZJbK0oIjM0jbxrBzTh2JKA8EQRGw5cj7NPVw6DJesIgZzMnzbIUe 6WhtfX1+IUwKruRgjJCYvq5582adxr7Ldir/qTE7UE+tb6hulPZu9JmMnR+fyY9Bjg1C LQ5zeJ5GG1BJxZam5amMZlBnZ8rmsROB7xrRMM9FBINxScP25g3kv3faSjpEQko+Qf9R aZ6Ncv6BPWZANYEWPvWF4NXV8w/qC0O6DfiejY95tuzsbuJ70Qt123vMQ/WJmAZdvdBo 0FnhZ0obLz2wQdDZDQHl8pFRYo/ufJEoji8SN38Lmc5DiOf3VvUZ3NF3bBM+ZjndK7+/ IOVA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=Dgr+R+Ooqj7O8IbEZN3k8kABePugAAeIHX9669QxJ80=; b=zmP54NkWWyICRWw6Wwlc+UKrJH30RW/sbMeBzpdoAvuqYMWidv1cAu7p/87llbRtJL deXA1OMhAubo1HPbrZTBeU4gb6ex+fnCH5Dy/JnOpTUKCYFyCuebBQ/KBp48iv4+cxx/ LXs6HGX0W5WBeCtJg+I/9V+BA2JYggTvhimH9p0oVyj2lHYWmoLNB4a+Q0HZHuzru9vy yYpbljvwfcCh0IhPaRTA1E8ZivJr5etsQtmjOLn1ak7ZyUOh0w0N/5KTPnw7MfFSwcRT uBFCnBFIfBkgU+MhJ8oiPTMkDrREglGuChSb9IK+24IwnO5/P6Dwk5mZeQwVpJg1uTV8 zyFQ== X-Gm-Message-State: ACgBeo2Kwr+CeL1pbdyC9SSTLszT6drjMkIKxuJsJ7OkZTwXk12Khc/x LbMSQdVwg+v6cn+y80KKWbxnrA== X-Google-Smtp-Source: AA6agR6T30+0oOAruQ1NqH8Mc3XrzaGWuY4JttKOMhps4dvfSnG9rR5qWPpPk2ZQkHLHfHOIE3PQ9g== X-Received: by 2002:a05:6000:1806:b0:225:5c19:6c75 with SMTP id m6-20020a056000180600b002255c196c75mr2040295wrh.524.1661179525219; Mon, 22 Aug 2022 07:45:25 -0700 (PDT) Received: from blmsp.fritz.box ([2001:4090:a245:8020:2658:1f7c:362:3e99]) by smtp.gmail.com with ESMTPSA id z24-20020a1cf418000000b003a5dadcf1a8sm14670935wma.19.2022.08.22.07.45.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 07:45:24 -0700 (PDT) From: Markus Schneider-Pargmann To: Rob Herring , Krzysztof Kozlowski , Matthias Brugger Cc: Chun-Jie Chen , AngeloGioacchino Del Regno , Fabien Parent , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Fabien Parent , Markus Schneider-Pargmann Subject: [PATCH v3 4/4] soc: mediatek: pm-domains: Add support for MT8365 Date: Mon, 22 Aug 2022 16:43:03 +0200 Message-Id: <20220822144303.3438467-5-msp@baylibre.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220822144303.3438467-1-msp@baylibre.com> References: <20220822144303.3438467-1-msp@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Fabien Parent Add the needed board data to support MT8365 SoC. Signed-off-by: Fabien Parent Signed-off-by: Markus Schneider-Pargmann --- drivers/soc/mediatek/mt8365-pm-domains.h | 147 +++++++++++++++++++++++ drivers/soc/mediatek/mtk-pm-domains.c | 5 + 2 files changed, 152 insertions(+) create mode 100644 drivers/soc/mediatek/mt8365-pm-domains.h diff --git a/drivers/soc/mediatek/mt8365-pm-domains.h b/drivers/soc/mediate= k/mt8365-pm-domains.h new file mode 100644 index 000000000000..950ff90d5560 --- /dev/null +++ b/drivers/soc/mediatek/mt8365-pm-domains.h @@ -0,0 +1,147 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_MT8365_PM_DOMAINS_H +#define __SOC_MEDIATEK_MT8365_PM_DOMAINS_H + +#include "mtk-pm-domains.h" +#include + +/* + * MT8365 power domain support + */ + +static const struct scpsys_domain_data scpsys_domain_data_mt8365[] =3D { + [MT8365_POWER_DOMAIN_MM] =3D { + .name =3D "mm", + .sta_mask =3D PWR_STATUS_DISP, + .ctl_offs =3D 0x30c, + .pwr_sta_offs =3D 0x0180, + .pwr_sta2nd_offs =3D 0x0184, + .sram_pdn_bits =3D GENMASK(8, 8), + .sram_pdn_ack_bits =3D GENMASK(12, 12), + .caps =3D MTK_SCPD_STRICT_BUS_PROTECTION, + .bp_infracfg =3D { + BUS_PROT_WR(BIT(16) | BIT(17), 0x2a8, 0x2ac, 0x258), + BUS_PROT_WR(BIT(1) | BIT(2) | BIT(10) | BIT(11), 0x2a0, 0x2a4, 0x228), + BUS_PROT_WAY_EN(BIT(6), BIT(24), 0x200, 0x0), + BUS_PROT_WAY_EN(BIT(5), BIT(14), 0x234, 0x28), + BUS_PROT_WR(BIT(6), 0x2a0, 0x2a4, 0x228), + }, + }, + [MT8365_POWER_DOMAIN_VENC] =3D { + .name =3D "venc", + .sta_mask =3D PWR_STATUS_VENC, + .ctl_offs =3D 0x0304, + .pwr_sta_offs =3D 0x0180, + .pwr_sta2nd_offs =3D 0x0184, + .sram_pdn_bits =3D GENMASK(8, 8), + .sram_pdn_ack_bits =3D GENMASK(12, 12), + .bp_smi =3D { + BUS_PROT_WR(BIT(1), 0x3c4, 0x3c8, 0x3c0), + }, + }, + [MT8365_POWER_DOMAIN_AUDIO] =3D { + .name =3D "audio", + .sta_mask =3D PWR_STATUS_AUDIO, + .ctl_offs =3D 0x0314, + .pwr_sta_offs =3D 0x0180, + .pwr_sta2nd_offs =3D 0x0184, + .sram_pdn_bits =3D GENMASK(12, 8), + .sram_pdn_ack_bits =3D GENMASK(17, 13), + .bp_infracfg =3D { + BUS_PROT_WR(BIT(27) | BIT(28), 0x2a8, 0x2ac, 0x258), + }, + .caps =3D MTK_SCPD_ACTIVE_WAKEUP, + }, + [MT8365_POWER_DOMAIN_CONN] =3D { + .name =3D "conn", + .sta_mask =3D PWR_STATUS_CONN, + .ctl_offs =3D 0x032c, + .pwr_sta_offs =3D 0x0180, + .pwr_sta2nd_offs =3D 0x0184, + .sram_pdn_bits =3D 0, + .sram_pdn_ack_bits =3D 0, + .bp_infracfg =3D { + BUS_PROT_WR(BIT(13), 0x2a0, 0x2a4, 0x228), + BUS_PROT_WR(BIT(18), 0x2a8, 0x2ac, 0x258), + BUS_PROT_WR(BIT(14), 0x2a0, 0x2a4, 0x228), + BUS_PROT_WR(BIT(21), 0x2a8, 0x2ac, 0x258), + }, + .caps =3D MTK_SCPD_ACTIVE_WAKEUP | MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT8365_POWER_DOMAIN_MFG] =3D { + .name =3D "mfg", + .sta_mask =3D PWR_STATUS_MFG, + .ctl_offs =3D 0x0338, + .pwr_sta_offs =3D 0x0180, + .pwr_sta2nd_offs =3D 0x0184, + .sram_pdn_bits =3D GENMASK(9, 8), + .sram_pdn_ack_bits =3D GENMASK(13, 12), + .bp_infracfg =3D { + BUS_PROT_WR(BIT(25), 0x2a0, 0x2a4, 0x228), + BUS_PROT_WR(BIT(21) | BIT(22), 0x2a0, 0x2a4, 0x228), + }, + }, + [MT8365_POWER_DOMAIN_CAM] =3D { + .name =3D "cam", + .sta_mask =3D BIT(25), + .ctl_offs =3D 0x0344, + .pwr_sta_offs =3D 0x0180, + .pwr_sta2nd_offs =3D 0x0184, + .sram_pdn_bits =3D GENMASK(9, 8), + .sram_pdn_ack_bits =3D GENMASK(13, 12), + .bp_infracfg =3D { + BUS_PROT_WR(BIT(19), 0x2a8, 0x2ac, 0x258), + }, + .bp_smi =3D { + BUS_PROT_WR(BIT(2), 0x3c4, 0x3c8, 0x3c0), + }, + }, + [MT8365_POWER_DOMAIN_VDEC] =3D { + .name =3D "vdec", + .sta_mask =3D BIT(31), + .ctl_offs =3D 0x0370, + .pwr_sta_offs =3D 0x0180, + .pwr_sta2nd_offs =3D 0x0184, + .sram_pdn_bits =3D GENMASK(8, 8), + .sram_pdn_ack_bits =3D GENMASK(12, 12), + .bp_smi =3D { + BUS_PROT_WR(BIT(3), 0x3c4, 0x3c8, 0x3c0), + }, + }, + [MT8365_POWER_DOMAIN_APU] =3D { + .name =3D "apu", + .sta_mask =3D BIT(16), + .ctl_offs =3D 0x0378, + .pwr_sta_offs =3D 0x0180, + .pwr_sta2nd_offs =3D 0x0184, + .sram_pdn_bits =3D GENMASK(14, 8), + .sram_pdn_ack_bits =3D GENMASK(21, 15), + .bp_infracfg =3D { + BUS_PROT_WR(BIT(2) | BIT(20), 0x2a8, 0x2ac, 0x258), + }, + .bp_smi =3D { + BUS_PROT_WR(BIT(4), 0x3c4, 0x3c8, 0x3c0), + }, + }, + [MT8365_POWER_DOMAIN_DSP] =3D { + .name =3D "dsp", + .sta_mask =3D BIT(17), + .ctl_offs =3D 0x037C, + .pwr_sta_offs =3D 0x0180, + .pwr_sta2nd_offs =3D 0x0184, + .sram_pdn_bits =3D GENMASK(11, 8), + .sram_pdn_ack_bits =3D GENMASK(15, 12), + .bp_infracfg =3D { + BUS_PROT_WR(BIT(24) | BIT(30) | BIT(31), 0x2a8, 0x2ac, 0x258), + }, + .caps =3D MTK_SCPD_ACTIVE_WAKEUP, + }, +}; + +static const struct scpsys_soc_data mt8365_scpsys_data =3D { + .domains_data =3D scpsys_domain_data_mt8365, + .num_domains =3D ARRAY_SIZE(scpsys_domain_data_mt8365), +}; + +#endif /* __SOC_MEDIATEK_MT8365_PM_DOMAINS_H */ diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/m= tk-pm-domains.c index d323275aa11c..dbabdd688a1f 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.c +++ b/drivers/soc/mediatek/mtk-pm-domains.c @@ -23,6 +23,7 @@ #include "mt8186-pm-domains.h" #include "mt8192-pm-domains.h" #include "mt8195-pm-domains.h" +#include "mt8365-pm-domains.h" =20 #define MTK_POLL_DELAY_US 10 #define MTK_POLL_TIMEOUT USEC_PER_SEC @@ -706,6 +707,10 @@ static const struct of_device_id scpsys_of_match[] =3D= { .compatible =3D "mediatek,mt8195-power-controller", .data =3D &mt8195_scpsys_data, }, + { + .compatible =3D "mediatek,mt8365-power-controller", + .data =3D &mt8365_scpsys_data, + }, { } }; =20 --=20 2.37.2