From nobody Fri Apr 10 10:55:54 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 916C7C28D13 for ; Mon, 22 Aug 2022 08:01:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233293AbiHVIBq (ORCPT ); Mon, 22 Aug 2022 04:01:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54204 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233209AbiHVIBg (ORCPT ); Mon, 22 Aug 2022 04:01:36 -0400 Received: from mail.fris.de (mail.fris.de [IPv6:2a01:4f8:c2c:390b::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 79F2D2AE1A; Mon, 22 Aug 2022 01:01:35 -0700 (PDT) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 8268AC018B; Mon, 22 Aug 2022 10:01:31 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fris.de; s=dkim; t=1661155293; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=zU7RWqah3dWELUuDIGga8OUgOvhVsdQkNRY8DYAu0mA=; b=0V3YtkNi8oSxCB1pI3wQ4ewfj16U9R4eGlFjGfwkNXCWngqiKJj7x0mJBgKD/oECttXeJK TJOK2Qglh4xNA5JH9kJWLOMo8kboej+O+SFwzOU3A/FajjRpTmYYw1di1KDETTqZHWl5S2 d56uhaCaAia57AJ8Qw8KpH5quxJqNiXKQYY1bj8oFdkN2mH0fihAFshMLFWhxffYkAP30Z 75BrnxW/8jjadJL3qrKpm/ltOUiVqeX6VyLjF7Ta0Al4gBBOUjhEeIVxNJ4rewk2PafO0n cFAGRF5i64K0VK4HQoaiSs0535lY8wBwoaVVh41q5XXrVp7RY+BhbNmFv58mWQ== From: Frieder Schrempf To: devicetree@vger.kernel.org, Krzysztof Kozlowski , linux-kernel@vger.kernel.org, Li Yang , Rob Herring , Shawn Guo Cc: Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, Frieder Schrempf , Alexander Stein , Denys Drozdov , Fabio Estevam , Marcel Ziswiler , Marek Vasut , Matthias Schiffer , Max Krummenacher , Rob Herring Subject: [PATCH v3 1/8] dt-bindings: arm: fsl: Rename compatibles for Kontron i.MX8MM SoM/board Date: Mon, 22 Aug 2022 10:00:54 +0200 Message-Id: <20220822080103.24016-2-frieder@fris.de> In-Reply-To: <20220822080103.24016-1-frieder@fris.de> References: <20220822080103.24016-1-frieder@fris.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Frieder Schrempf This updates the bindings in order to use names for the boards that follow the latest convention used by Kontron marketing. By updating we make sure, that we can maintain this more easily in future and make sure that the proper devicetree can be selected for the hardware. Signed-off-by: Frieder Schrempf Acked-by: Krzysztof Kozlowski --- Changes in v3: * new patch --- Documentation/devicetree/bindings/arm/fsl.yaml | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation= /devicetree/bindings/arm/fsl.yaml index 7431579ab0e8..4dcfa27044f0 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -831,7 +831,7 @@ properties: - gw,imx8mm-gw7901 # i.MX8MM Gateworks Board - gw,imx8mm-gw7902 # i.MX8MM Gateworks Board - gw,imx8mm-gw7903 # i.MX8MM Gateworks Board - - kontron,imx8mm-n801x-som # i.MX8MM Kontron SL (N801X) SOM + - kontron,imx8mm-sl # i.MX8MM Kontron SL (N801X) SOM - menlo,mx8menlo # i.MX8MM Menlo board with Verdi= n SoM - toradex,verdin-imx8mm # Verdin iMX8M Mini Modules - toradex,verdin-imx8mm-nonwifi # Verdin iMX8M Mini Modules= without Wi-Fi / BT @@ -850,8 +850,8 @@ properties: =20 - description: Kontron BL i.MX8MM (N801X S) Board items: - - const: kontron,imx8mm-n801x-s - - const: kontron,imx8mm-n801x-som + - const: kontron,imx8mm-bl + - const: kontron,imx8mm-sl - const: fsl,imx8mm =20 - description: Toradex Boards with Verdin iMX8M Mini Modules --=20 2.37.1 From nobody Fri Apr 10 10:55:54 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F319BC28D13 for ; Mon, 22 Aug 2022 08:01:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233508AbiHVIBu (ORCPT ); Mon, 22 Aug 2022 04:01:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54210 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233324AbiHVIBh (ORCPT ); Mon, 22 Aug 2022 04:01:37 -0400 Received: from mail.fris.de (mail.fris.de [IPv6:2a01:4f8:c2c:390b::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CCD0E2AC51; Mon, 22 Aug 2022 01:01:36 -0700 (PDT) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 2CB32C01BC; Mon, 22 Aug 2022 10:01:34 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fris.de; s=dkim; t=1661155294; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=hzJyrDoXrhCO0SrbCPDsNSDDOwNsM9vLr50z3j28vZM=; b=v+xGDzjY/NHElhlidd2kj+/PqHlXJZoGyB0Owlbnv2LwftDjhD8f06+EEgAhR3ohR5HWOg 5UKVvr0yQvtc1tqxGeaMFT9HnY2oIz+pCa5MJJImBRBlFJ2DeX0UGBPjXHIJP1/VPMffZX 9GsnfKddcZQxYxit2QcPGO2sdtCQ5OQwoyBPUHphlZ2zTXd+9EII60u2GxId4Vv9EpldCO 8wBV4b4ukvVeg9j8bKsjgjn0hN9drp2b+wTlu2kqhwKdpcB8SY5mnzD6umBKWUgMKvg/3M RqtrFEijM0VFTuUpoQkhFriiGq99o10vQeNlrZR7ELva1bz60H/RLixC3awXyQ== From: Frieder Schrempf To: devicetree@vger.kernel.org, Krzysztof Kozlowski , linux-kernel@vger.kernel.org, Li Yang , Rob Herring , Shawn Guo Cc: Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, Frieder Schrempf , Alexander Stein , Denys Drozdov , Fabio Estevam , Marcel Ziswiler , Marek Vasut , Matthias Schiffer , Max Krummenacher , Peng Fan , Rob Herring Subject: [PATCH v3 2/8] dt-bindings: arm: fsl: Add Kontron BL i.MX8MM OSM-S board Date: Mon, 22 Aug 2022 10:00:55 +0200 Message-Id: <20220822080103.24016-3-frieder@fris.de> In-Reply-To: <20220822080103.24016-1-frieder@fris.de> References: <20220822080103.24016-1-frieder@fris.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Frieder Schrempf Add bindings for the Kontron BL i.MX8MM OSM-S board. Signed-off-by: Frieder Schrempf Acked-by: Krzysztof Kozlowski --- Changes in v3: * rename compatibles * rebase on v6.0-rc1 Changes in v2: * add A-b tag from Krzysztof (Thanks!) --- Documentation/devicetree/bindings/arm/fsl.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation= /devicetree/bindings/arm/fsl.yaml index 4dcfa27044f0..2b5a4d293e25 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -832,6 +832,7 @@ properties: - gw,imx8mm-gw7902 # i.MX8MM Gateworks Board - gw,imx8mm-gw7903 # i.MX8MM Gateworks Board - kontron,imx8mm-sl # i.MX8MM Kontron SL (N801X) SOM + - kontron,imx8mm-osm-s # i.MX8MM Kontron OSM-S (N802X) = SOM - menlo,mx8menlo # i.MX8MM Menlo board with Verdi= n SoM - toradex,verdin-imx8mm # Verdin iMX8M Mini Modules - toradex,verdin-imx8mm-nonwifi # Verdin iMX8M Mini Modules= without Wi-Fi / BT @@ -854,6 +855,12 @@ properties: - const: kontron,imx8mm-sl - const: fsl,imx8mm =20 + - description: Kontron BL i.MX8MM OSM-S (N802X S) Board + items: + - const: kontron,imx8mm-bl-osm-s + - const: kontron,imx8mm-osm-s + - const: fsl,imx8mm + - description: Toradex Boards with Verdin iMX8M Mini Modules items: - enum: --=20 2.37.1 From nobody Fri Apr 10 10:55:54 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AB763C28D13 for ; Mon, 22 Aug 2022 08:01:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233518AbiHVIB4 (ORCPT ); Mon, 22 Aug 2022 04:01:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54246 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233504AbiHVIBr (ORCPT ); Mon, 22 Aug 2022 04:01:47 -0400 Received: from mail.fris.de (mail.fris.de [IPv6:2a01:4f8:c2c:390b::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7CAA62AE22; Mon, 22 Aug 2022 01:01:46 -0700 (PDT) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id E7C7ABFB01; Mon, 22 Aug 2022 10:01:42 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fris.de; s=dkim; t=1661155304; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=VLD7rK7HYJT00mnuzEusL+Azqc9fPUAgIsqUp9tsh68=; b=zSydjTQcxfEakzxHtaN7dSYyaJ2iV8ZPFFd63qCCIhnWwGBFJSqIWaXkkWIwl4BwqTAGHl K4u3Cw7FVzhTkVbpXwgerTNlNLDza85lur/Xbq1083ls7MFIKVgNx0Ep4v/p5w6fZ3EwNC GFEMwNxjI72IzwKb7xG4zlIFiYzKXOzHG3+WerUuKFWuDr+LAxVkO37o3mw8Xx+tI6FY4P I6VVZdP/vc0B52pSOC78z9tJFXPpFqnFgq2/zRY7PHMlQa3w58FTV2bFIGZtIAQfr4xJXo LxyW/X3sScAUMzKmB8Z3kN6XR40K+XUpZkuMqnXuqGjCGzGRJ8xOrJm35H4Ahg== From: Frieder Schrempf To: devicetree@vger.kernel.org, Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rob Herring , Sascha Hauer , Shawn Guo Cc: Krzysztof Kozlowski , Frieder Schrempf , Alexander Stein , Alex Marginean , Fabio Estevam , Heiko Thiery , Krzysztof Kozlowski , Marcel Ziswiler , Marek Vasut , NXP Linux Team , Oleksij Rempel , Pengutronix Kernel Team , Reinhold Mueller , Tim Harvey , Vladimir Oltean Subject: [PATCH v3 3/8] arm64: dts: imx8mm-kontron: Adjust compatibles, file names and model strings Date: Mon, 22 Aug 2022 10:00:56 +0200 Message-Id: <20220822080103.24016-4-frieder@fris.de> In-Reply-To: <20220822080103.24016-1-frieder@fris.de> References: <20220822080103.24016-1-frieder@fris.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Frieder Schrempf The official naming includes "SL" (SoM-Line) or "BL" (Board-Line). By updating we make sure, that we can maintain this more easily in future and make sure that the proper devicetree can be selected for the hardware. Signed-off-by: Frieder Schrempf --- Changes in v3: * also rename compatibles and file names * rebase on v6.0-rc1 Changes in v2: * none --- arch/arm64/boot/dts/freescale/Makefile | 2 +- .../{imx8mm-kontron-n801x-s.dts =3D> imx8mm-kontron-bl.dts} | 4 ++-- .../{imx8mm-kontron-n801x-som.dtsi =3D> imx8mm-kontron-sl.dtsi} | 4 ++-- 3 files changed, 5 insertions(+), 5 deletions(-) rename arch/arm64/boot/dts/freescale/{imx8mm-kontron-n801x-s.dts =3D> imx8= mm-kontron-bl.dts} (98%) rename arch/arm64/boot/dts/freescale/{imx8mm-kontron-n801x-som.dtsi =3D> i= mx8mm-kontron-sl.dtsi} (98%) diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/f= reescale/Makefile index 8bf7f7ecebaa..d014f7c4c888 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -55,7 +55,7 @@ dtb-$(CONFIG_ARCH_MXC) +=3D imx8mm-emcon-avari.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mm-evk.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mm-icore-mx8mm-ctouch2.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mm-icore-mx8mm-edimm2.2.dtb -dtb-$(CONFIG_ARCH_MXC) +=3D imx8mm-kontron-n801x-s.dtb +dtb-$(CONFIG_ARCH_MXC) +=3D imx8mm-kontron-bl.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mm-mx8menlo.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mm-nitrogen-r2.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mm-phyboard-polis-rdk.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-s.dts b/arc= h/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts similarity index 98% rename from arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-s.dts rename to arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts index 23be1ec538ba..4e5828fa815b 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-s.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts @@ -8,8 +8,8 @@ #include "imx8mm-kontron-n801x-som.dtsi" =20 / { - model =3D "Kontron i.MX8MM N801X S"; - compatible =3D "kontron,imx8mm-n801x-s", "kontron,imx8mm-n801x-som", "fsl= ,imx8mm"; + model =3D "Kontron BL i.MX8MM (N801X S)"; + compatible =3D "kontron,imx8mm-bl", "kontron,imx8mm-sl", "fsl,imx8mm"; =20 aliases { ethernet1 =3D &usbnet; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi b/= arch/arm64/boot/dts/freescale/imx8mm-kontron-sl.dtsi similarity index 98% rename from arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi rename to arch/arm64/boot/dts/freescale/imx8mm-kontron-sl.dtsi index 8f90eb02550d..30299c2a98ea 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-sl.dtsi @@ -6,8 +6,8 @@ #include "imx8mm.dtsi" =20 / { - model =3D "Kontron i.MX8MM N801X SoM"; - compatible =3D "kontron,imx8mm-n801x-som", "fsl,imx8mm"; + model =3D "Kontron SL i.MX8MM (N801X SOM)"; + compatible =3D "kontron,imx8mm-sl", "fsl,imx8mm"; =20 memory@40000000 { device_type =3D "memory"; --=20 2.37.1 From nobody Fri Apr 10 10:55:54 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 81497C32772 for ; Mon, 22 Aug 2022 08:02:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232807AbiHVIB7 (ORCPT ); Mon, 22 Aug 2022 04:01:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54286 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233324AbiHVIBx (ORCPT ); Mon, 22 Aug 2022 04:01:53 -0400 Received: from mail.fris.de (mail.fris.de [IPv6:2a01:4f8:c2c:390b::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9604F2B19F; Mon, 22 Aug 2022 01:01:52 -0700 (PDT) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 05392C01B8; Mon, 22 Aug 2022 10:01:49 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fris.de; s=dkim; t=1661155310; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=Xyc3HeD/Wetg/6U2L3dZq0OudoqJsGiwjd9pgCHOEfw=; b=Et6pJqRCG7E1UVTxH8xhhD7/xz8qaLDjQvPnnAi3EAojwv0hUyklMEJpYiYCp5XV9+c3ym mR+01tuwuCbYy97lxfkigFiz3FKJQVRFrCuyUFhi1TFAZaA67FaANE1fRjH3QprfiP3XCK 5Ka4BsGea0rEFXxLigrHeK5lElJU0TWzvklucE7Z6lc76nXHbXzKeH9JoiVKyGH4jQmiwZ aJ1o0Cdv6pMsXAdY0LOCa+/b/uJdYS35BSX8K95hm5Q/BvXjHAf4LkMeVj10i/kd+HKytq 1lrjPQGGrLagI+LGj9/r83RGDn33xBpRQRtyKNkQ1zYMt1tQFonpYL4tKemNOQ== From: Frieder Schrempf To: devicetree@vger.kernel.org, Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rob Herring , Sascha Hauer , Shawn Guo Cc: Krzysztof Kozlowski , Frieder Schrempf , Heiko Thiery , Fabio Estevam , NXP Linux Team , Oleksij Rempel , Pengutronix Kernel Team Subject: [PATCH v3 4/8] arm64: dts: imx8mm-kontron: Use the VSELECT signal to switch SD card IO voltage Date: Mon, 22 Aug 2022 10:00:57 +0200 Message-Id: <20220822080103.24016-5-frieder@fris.de> In-Reply-To: <20220822080103.24016-1-frieder@fris.de> References: <20220822080103.24016-1-frieder@fris.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Frieder Schrempf It turns out that it is not necessary to declare the VSELECT signal as GPIO and let the PMIC driver set it to a fixed high level. This switches the voltage between 3.3V and 1.8V by setting the PMIC register for LDO5 accordingly. Instead we can do it like other boards already do and simply mux the VSELECT signal of the USDHC interface to the pin. This makes sure that the correct voltage is selected by setting the PMIC's SD_VSEL input to high or low accordingly. Reported-by: Heiko Thiery Signed-off-by: Frieder Schrempf Reviewed-by: Heiko Thiery --- Changes in v3: * rebase on v6.0-rc1 Changes in v2: * none --- arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts | 3 +++ arch/arm64/boot/dts/freescale/imx8mm-kontron-sl.dtsi | 2 -- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts b/arch/arm= 64/boot/dts/freescale/imx8mm-kontron-bl.dts index 4e5828fa815b..7af3c476fd9a 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts @@ -321,6 +321,7 @@ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 >; }; =20 @@ -333,6 +334,7 @@ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 >; }; =20 @@ -345,6 +347,7 @@ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 >; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-sl.dtsi b/arch/ar= m64/boot/dts/freescale/imx8mm-kontron-sl.dtsi index 30299c2a98ea..33179157f619 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-sl.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-sl.dtsi @@ -86,7 +86,6 @@ pca9450: pmic@25 { pinctrl-0 =3D <&pinctrl_pmic>; interrupt-parent =3D <&gpio1>; interrupts =3D <0 IRQ_TYPE_LEVEL_LOW>; - sd-vsel-gpios =3D <&gpio1 4 GPIO_ACTIVE_HIGH>; =20 regulators { reg_vdd_soc: BUCK1 { @@ -229,7 +228,6 @@ MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 pinctrl_pmic: pmicgrp { fsl,pins =3D < MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x141 - MX8MM_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x141 >; }; =20 --=20 2.37.1 From nobody Fri Apr 10 10:55:54 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 616E6C28D13 for ; Mon, 22 Aug 2022 08:02:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230517AbiHVICI (ORCPT ); Mon, 22 Aug 2022 04:02:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54316 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233528AbiHVIB4 (ORCPT ); Mon, 22 Aug 2022 04:01:56 -0400 Received: from mail.fris.de (mail.fris.de [116.203.77.234]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C1D6E2AE22; Mon, 22 Aug 2022 01:01:55 -0700 (PDT) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 9DD25C018B; Mon, 22 Aug 2022 10:01:53 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fris.de; s=dkim; t=1661155314; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=DWFAWhIpY/WASigIlLwyV1sUn/XN9i+sYTmP//PqvJw=; b=gnDuNB4svVUncWMoMI+iV2sZU9UeGjBmUHm8IEdg/K/wHn+JRUgOxnL+ZRpXQ1GuHqSMxd 2ctzPgF5ibUYU/m2lSU2GFbEDG8zR+VwRa28M5P+M8xq6njU4DjYLnXMroRV2HhGRZTLSG feqA9DrmE+j1o0hOF74qwn21lc+x1EkILOykliclVrWq3leRS2Jf8z/wpU3hUG11UtV4Wx 6MhA/lmy1VV0HlWbK5Z9uyfUZSX4gIx+QVrfc4iDHk4BfeN0ZFJlVCTAuTm7Uj+ViHEBb6 ObtflsjbxkCYTnlZHUBoY2w1ifgYes5cgBrki+DuHWxB73mwHZa8AiuhDj6vBw== From: Frieder Schrempf To: devicetree@vger.kernel.org, Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rob Herring , Sascha Hauer , Shawn Guo Cc: Krzysztof Kozlowski , Frieder Schrempf , Fabio Estevam , Heiko Thiery , NXP Linux Team , Pengutronix Kernel Team Subject: [PATCH v3 5/8] arm64: dts: imx8mm-kontron: Remove low DDRC operating point Date: Mon, 22 Aug 2022 10:00:58 +0200 Message-Id: <20220822080103.24016-6-frieder@fris.de> In-Reply-To: <20220822080103.24016-1-frieder@fris.de> References: <20220822080103.24016-1-frieder@fris.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Frieder Schrempf For some reason there is a problem with finding a DDR configuration that works on all operating points and all LPDDR4 types used on the SoM. Therefore the bootloader currently doesn't configure the lowest of the three operating points. Let's also skip this in the kernel devicetree to make sure it isn't used. Signed-off-by: Frieder Schrempf --- Changes in v3: * rebase on v6.0-rc1 Changes in v2: * none --- arch/arm64/boot/dts/freescale/imx8mm-kontron-sl.dtsi | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-sl.dtsi b/arch/ar= m64/boot/dts/freescale/imx8mm-kontron-sl.dtsi index 33179157f619..96ecdce67059 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-sl.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-sl.dtsi @@ -46,10 +46,6 @@ &ddrc { ddrc_opp_table: opp-table { compatible =3D "operating-points-v2"; =20 - opp-25M { - opp-hz =3D /bits/ 64 <25000000>; - }; - opp-100M { opp-hz =3D /bits/ 64 <100000000>; }; --=20 2.37.1 From nobody Fri Apr 10 10:55:54 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2DF27C28D13 for ; Mon, 22 Aug 2022 08:02:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233460AbiHVICU (ORCPT ); Mon, 22 Aug 2022 04:02:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54398 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233534AbiHVICA (ORCPT ); Mon, 22 Aug 2022 04:02:00 -0400 Received: from mail.fris.de (mail.fris.de [116.203.77.234]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6041C2B1A1; Mon, 22 Aug 2022 01:01:59 -0700 (PDT) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id F19C2BFAE8; Mon, 22 Aug 2022 10:01:56 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fris.de; s=dkim; t=1661155317; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=bWW/Mcp6FRxk3hYHeb0NVlS/tciRYIln8vZV2wTf7ww=; b=fMV/KNeNGfJlo+dcLotoHj3eso+Z7oy283ct0O8VfSsfWtjQiegvFLE0yGWORsY7dVh+8/ Iky/tZVz589RHc/sSSZK50JrIyND6l/PeLX1/LbiGlZabeTJDnLyciRVhXiRAP7pyIKN1x MMHhxW1ARg7kwDyV51vhYA/bsjcD+M7K8rm5GPSRSyjDYbVmZA+MobMGhDydHm09pzE5JJ 5Yx307VO+HG5XunDN7uh05bUKiAQehsgp+YcpjYbq7ZR4C7fZSWg39y4ME/TCjKbZjIvI8 2oxp4EtY4vBtVjxFix5uYP0w5q7ZPUvGAkGaRvZG4dNIQclLy+OoIKst+eLzfQ== From: Frieder Schrempf To: devicetree@vger.kernel.org, Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rob Herring , Sascha Hauer , Shawn Guo Cc: Krzysztof Kozlowski , Frieder Schrempf , Heiko Thiery , Fabio Estevam , NXP Linux Team , Pengutronix Kernel Team Subject: [PATCH v3 6/8] arm64: dts: imx8mm-kontron: Use voltage rail names from schematic for PMIC regulator-names Date: Mon, 22 Aug 2022 10:00:59 +0200 Message-Id: <20220822080103.24016-7-frieder@fris.de> In-Reply-To: <20220822080103.24016-1-frieder@fris.de> References: <20220822080103.24016-1-frieder@fris.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Frieder Schrempf Improve the naming of the regulators to contain the voltage rail names from the schematic. Suggested-by: Heiko Thiery Signed-off-by: Frieder Schrempf --- Changes in v3: * rebase on v6.0-rc1 Changes in v2: * new patch --- .../boot/dts/freescale/imx8mm-kontron-sl.dtsi | 22 +++++++++---------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-sl.dtsi b/arch/ar= m64/boot/dts/freescale/imx8mm-kontron-sl.dtsi index 96ecdce67059..ce9c27619e26 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-sl.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-sl.dtsi @@ -85,7 +85,7 @@ pca9450: pmic@25 { =20 regulators { reg_vdd_soc: BUCK1 { - regulator-name =3D "buck1"; + regulator-name =3D "+0V8_VDD_SOC (BUCK1)"; regulator-min-microvolt =3D <800000>; regulator-max-microvolt =3D <850000>; regulator-boot-on; @@ -96,7 +96,7 @@ reg_vdd_soc: BUCK1 { }; =20 reg_vdd_arm: BUCK2 { - regulator-name =3D "buck2"; + regulator-name =3D "+0V9_VDD_ARM (BUCK2)"; regulator-min-microvolt =3D <850000>; regulator-max-microvolt =3D <950000>; regulator-boot-on; @@ -107,7 +107,7 @@ reg_vdd_arm: BUCK2 { }; =20 reg_vdd_dram: BUCK3 { - regulator-name =3D "buck3"; + regulator-name =3D "+0V9_VDD_DRAM&PU (BUCK3)"; regulator-min-microvolt =3D <850000>; regulator-max-microvolt =3D <950000>; regulator-boot-on; @@ -115,7 +115,7 @@ reg_vdd_dram: BUCK3 { }; =20 reg_vdd_3v3: BUCK4 { - regulator-name =3D "buck4"; + regulator-name =3D "+3V3 (BUCK4)"; regulator-min-microvolt =3D <3300000>; regulator-max-microvolt =3D <3300000>; regulator-boot-on; @@ -123,7 +123,7 @@ reg_vdd_3v3: BUCK4 { }; =20 reg_vdd_1v8: BUCK5 { - regulator-name =3D "buck5"; + regulator-name =3D "+1V8 (BUCK5)"; regulator-min-microvolt =3D <1800000>; regulator-max-microvolt =3D <1800000>; regulator-boot-on; @@ -131,7 +131,7 @@ reg_vdd_1v8: BUCK5 { }; =20 reg_nvcc_dram: BUCK6 { - regulator-name =3D "buck6"; + regulator-name =3D "+1V1_NVCC_DRAM (BUCK6)"; regulator-min-microvolt =3D <1100000>; regulator-max-microvolt =3D <1100000>; regulator-boot-on; @@ -139,7 +139,7 @@ reg_nvcc_dram: BUCK6 { }; =20 reg_nvcc_snvs: LDO1 { - regulator-name =3D "ldo1"; + regulator-name =3D "+1V8_NVCC_SNVS (LDO1)"; regulator-min-microvolt =3D <1800000>; regulator-max-microvolt =3D <1800000>; regulator-boot-on; @@ -147,7 +147,7 @@ reg_nvcc_snvs: LDO1 { }; =20 reg_vdd_snvs: LDO2 { - regulator-name =3D "ldo2"; + regulator-name =3D "+0V8_VDD_SNVS (LDO2)"; regulator-min-microvolt =3D <800000>; regulator-max-microvolt =3D <900000>; regulator-boot-on; @@ -155,7 +155,7 @@ reg_vdd_snvs: LDO2 { }; =20 reg_vdda: LDO3 { - regulator-name =3D "ldo3"; + regulator-name =3D "+1V8_VDDA (LDO3)"; regulator-min-microvolt =3D <1800000>; regulator-max-microvolt =3D <1800000>; regulator-boot-on; @@ -163,7 +163,7 @@ reg_vdda: LDO3 { }; =20 reg_vdd_phy: LDO4 { - regulator-name =3D "ldo4"; + regulator-name =3D "+0V9_VDD_PHY (LDO4)"; regulator-min-microvolt =3D <900000>; regulator-max-microvolt =3D <900000>; regulator-boot-on; @@ -171,7 +171,7 @@ reg_vdd_phy: LDO4 { }; =20 reg_nvcc_sd: LDO5 { - regulator-name =3D "ldo5"; + regulator-name =3D "NVCC_SD (LDO5)"; regulator-min-microvolt =3D <1800000>; regulator-max-microvolt =3D <3300000>; }; --=20 2.37.1 From nobody Fri Apr 10 10:55:54 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 048B9C28D13 for ; Mon, 22 Aug 2022 08:02:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233634AbiHVICc (ORCPT ); Mon, 22 Aug 2022 04:02:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54706 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233574AbiHVICN (ORCPT ); Mon, 22 Aug 2022 04:02:13 -0400 Received: from mail.fris.de (mail.fris.de [116.203.77.234]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8EDB92B246; Mon, 22 Aug 2022 01:02:03 -0700 (PDT) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 97312BFB01; Mon, 22 Aug 2022 10:02:00 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fris.de; s=dkim; t=1661155321; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=iWm6cbXgNgOMu08msuouo2YkcT7OoKQnsuMv8gfoWnY=; b=kBlJNkF2rUWcnsp353JKgd8ucW5QMw5AO1MgXpEYKZgdP6LE0ZtTo+ptt47ufWZAD9iQlY IdAY9i0viLMQN1YOBFAb7alDPf5QSwFwzgk6Q8bK+DCewp2g7/ONbWTJTRk9jQIdvQpCOt 5XN7jqxM8qw19wFoOUvwmFGOHu+Xb4+vzCr8/yr29fqXw3ieoKDiK0va1OMtzLehb/SWEt QwgMOlsdslB++5rwvGz3ugMj9ec4oa1SvV1pUyufWIXN4i4Z1tRcFq7ZFhj7qsv5GdY/+x 7f5jpuo6Fmpn4TLyM+LFQdH6zmS1K5Cmh2rz3ZUxyYhaiqoLbaji+06nxAt4aQ== From: Frieder Schrempf To: devicetree@vger.kernel.org, Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rob Herring , Sascha Hauer , Shawn Guo Cc: Krzysztof Kozlowski , Frieder Schrempf , Fabio Estevam , Heiko Thiery , NXP Linux Team , Pengutronix Kernel Team Subject: [PATCH v3 7/8] arm64: dts: imx8mm-kontron: Add SPI NOR partition layout Date: Mon, 22 Aug 2022 10:01:00 +0200 Message-Id: <20220822080103.24016-8-frieder@fris.de> In-Reply-To: <20220822080103.24016-1-frieder@fris.de> References: <20220822080103.24016-1-frieder@fris.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Frieder Schrempf This is the layout used by the bootloader. Add it to the kernel devicetree to make the same layout available in Linux and have the devicetrees synced. Signed-off-by: Frieder Schrempf --- Changes in v3: * rebase on v6.0-rc1 Changes in v2: * new patch --- .../boot/dts/freescale/imx8mm-kontron-sl.dtsi | 21 +++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-sl.dtsi b/arch/ar= m64/boot/dts/freescale/imx8mm-kontron-sl.dtsi index ce9c27619e26..c227ca813d9e 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-sl.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-sl.dtsi @@ -66,6 +66,27 @@ flash@0 { compatible =3D "mxicy,mx25r1635f", "jedec,spi-nor"; spi-max-frequency =3D <80000000>; reg =3D <0>; + + partitions { + compatible =3D "fixed-partitions"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + partition@0 { + label =3D "u-boot"; + reg =3D <0x0 0x1E0000>; + }; + + partition@1 { + label =3D "env"; + reg =3D <0x1E0000 0x10000>; + }; + + partition@2 { + label =3D "env_redundant"; + reg =3D <0x1F0000 0x10000>; + }; + }; }; }; =20 --=20 2.37.1 From nobody Fri Apr 10 10:55:54 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 59A09C28D13 for ; Mon, 22 Aug 2022 08:03:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233631AbiHVIDa (ORCPT ); Mon, 22 Aug 2022 04:03:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55804 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233692AbiHVICs (ORCPT ); Mon, 22 Aug 2022 04:02:48 -0400 Received: from mail.fris.de (mail.fris.de [IPv6:2a01:4f8:c2c:390b::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EDF462BB2A; Mon, 22 Aug 2022 01:02:16 -0700 (PDT) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 22E01BFAE8; Mon, 22 Aug 2022 10:02:13 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fris.de; s=dkim; t=1661155334; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=o9DVUnXAlMYVG6yDL64+cXcr0Bmy6scNlBmQFuFNWaM=; b=v79DV7pmOdK+vI5faIfMI93L0c5ukhd0HUFQBoRnLhyq3VJiu/b/YMab1/A73/T+mOiXrk 21OpL5ucJfd01s9D4EAkD9FtYmsFZAkhiMbi3VEGrC0NiVNaJwqUdTApKiZoM2Vye8a5xq 87pgB46pf6SZmnzX9t8PyU1BiLPL3pMAWxqeY+Q5YlRQiwPpbIKczhR5Vng3GVY3bCrF81 gHAoElNsvfRA5DemE4ZFVBlUMTlzeJdnbtUl7sDUvaCZsQmkc0OPZPX67A7Zf4oNcT/1D3 Tp5Opixyw7OJ8G++rbqXOaFhZstk5R1e6m2Sji6g3ke4vDrL9yVhZKmNqWTiWA== From: Frieder Schrempf To: devicetree@vger.kernel.org, Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rob Herring , Sascha Hauer , Shawn Guo Cc: Krzysztof Kozlowski , Frieder Schrempf , Alexander Stein , Alex Marginean , Fabio Estevam , Heiko Thiery , Krzysztof Kozlowski , Marcel Ziswiler , Marek Vasut , NXP Linux Team , Oleksij Rempel , Pengutronix Kernel Team , Reinhold Mueller , Tim Harvey Subject: [PATCH v3 8/8] arm64: dts: Add support for Kontron SL/BL i.MX8MM OSM-S Date: Mon, 22 Aug 2022 10:01:01 +0200 Message-Id: <20220822080103.24016-9-frieder@fris.de> In-Reply-To: <20220822080103.24016-1-frieder@fris.de> References: <20220822080103.24016-1-frieder@fris.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Frieder Schrempf This adds support for the Kontron Electronics SL i.MX8MM OSM-S SoM and the matching baseboard BL i.MX8MM OSM-S. The SoM hardware complies to the Open Standard Module (OSM) 1.0 specification, size S (https://sget.org/standards/osm). Signed-off-by: Frieder Schrempf --- Changes in v3: * rename devicetrees, compatibles and SoM model * rebase on v6.0-rc1 Changes in v2: * add SPI NOR partitions * use voltage rail names for PMIC regulator-name * drop unused header include --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../dts/freescale/imx8mm-kontron-bl-osm-s.dts | 376 ++++++++++++++++++ .../dts/freescale/imx8mm-kontron-osm-s.dtsi | 330 +++++++++++++++ 3 files changed, 707 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-osm-s.d= ts create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/f= reescale/Makefile index d014f7c4c888..542e1d661f30 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -56,6 +56,7 @@ dtb-$(CONFIG_ARCH_MXC) +=3D imx8mm-evk.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mm-icore-mx8mm-ctouch2.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mm-icore-mx8mm-edimm2.2.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mm-kontron-bl.dtb +dtb-$(CONFIG_ARCH_MXC) +=3D imx8mm-kontron-bl-osm-s.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mm-mx8menlo.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mm-nitrogen-r2.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mm-phyboard-polis-rdk.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-osm-s.dts b/ar= ch/arm64/boot/dts/freescale/imx8mm-kontron-bl-osm-s.dts new file mode 100644 index 000000000000..a13a968e1848 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-osm-s.dts @@ -0,0 +1,376 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2022 Kontron Electronics GmbH + */ + +/dts-v1/; + +#include "imx8mm-kontron-n802x-som.dtsi" + +/ { + model =3D "Kontron BL i.MX8MM OSM-S (N802X S)"; + compatible =3D "kontron,imx8mm-bl-osm-s", "kontron,imx8mm-osm-s", "fsl,im= x8mm"; + + aliases { + ethernet1 =3D &usbnet; + }; + + /* fixed crystal dedicated to mcp2542fd */ + osc_can: clock-osc-can { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <40000000>; + clock-output-names =3D "osc-can"; + }; + + leds { + compatible =3D "gpio-leds"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_gpio_led>; + + led1 { + label =3D "led1"; + gpios =3D <&gpio1 12 GPIO_ACTIVE_LOW>; + linux,default-trigger =3D "heartbeat"; + }; + + led2 { + label =3D "led2"; + gpios =3D <&gpio1 13 GPIO_ACTIVE_LOW>; + }; + + led3 { + label =3D "led3"; + gpios =3D <&gpio1 14 GPIO_ACTIVE_LOW>; + }; + }; + + pwm-beeper { + compatible =3D "pwm-beeper"; + pwms =3D <&pwm2 0 5000 0>; + }; + + reg_rst_eth2: regulator-rst-eth2 { + compatible =3D "regulator-fixed"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_usb_eth2>; + gpio =3D <&gpio3 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + regulator-name =3D "rst-usb-eth2"; + }; + + reg_usb1_vbus: regulator-usb1-vbus { + compatible =3D "regulator-fixed"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_reg_usb1_vbus>; + gpio =3D <&gpio3 25 GPIO_ACTIVE_LOW>; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + regulator-name =3D "usb1-vbus"; + }; + + reg_vdd_5v: regulator-5v { + compatible =3D "regulator-fixed"; + regulator-always-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + regulator-name =3D "vdd-5v"; + }; +}; + +&ecspi2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_ecspi2>; + cs-gpios =3D <&gpio5 13 GPIO_ACTIVE_LOW>; + status =3D "okay"; + + can@0 { + compatible =3D "microchip,mcp251xfd"; + reg =3D <0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_can>; + clocks =3D <&osc_can>; + interrupts-extended =3D <&gpio4 28 IRQ_TYPE_LEVEL_LOW>; + /* + * Limit the SPI clock to 15 MHz to prevent issues + * with corrupted data due to chip errata. + */ + spi-max-frequency =3D <15000000>; + vdd-supply =3D <®_vdd_3v3>; + xceiver-supply =3D <®_vdd_5v>; + }; +}; + +&ecspi3 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_ecspi3>; + cs-gpios =3D <&gpio5 25 GPIO_ACTIVE_LOW>; + status =3D "okay"; + + eeram@0 { + compatible =3D "microchip,48l640"; + reg =3D <0>; + spi-max-frequency =3D <20000000>; + }; +}; + +&fec1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_enet>; + phy-connection-type =3D "rgmii-rxid"; + phy-handle =3D <ðphy>; + status =3D "okay"; + + mdio { + #address-cells =3D <1>; + #size-cells =3D <0>; + + ethphy: ethernet-phy@0 { + reg =3D <0>; + reset-assert-us =3D <1>; + reset-deassert-us =3D <15000>; + reset-gpios =3D <&gpio1 1 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&gpio1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_gpio1>; + gpio-line-names =3D "", "", "", "dio1-out", "", "", "dio1-in", "dio2-out", + "dio2-in", "dio3-out", "dio3-in", "dio4-out", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio5 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_gpio5>; + gpio-line-names =3D "", "", "dio4-in", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&i2c4 { + clock-frequency =3D <100000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_i2c4>; + status =3D "okay"; +}; + +&pwm2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_pwm2>; + status =3D "okay"; +}; + +&uart1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_uart1>; + uart-has-rtscts; + status =3D "okay"; +}; + +&uart2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_uart2>; + linux,rs485-enabled-at-boot-time; + uart-has-rtscts; + status =3D "okay"; +}; + +&usbotg1 { + dr_mode =3D "otg"; + disable-over-current; + vbus-supply =3D <®_usb1_vbus>; + status =3D "okay"; +}; + +&usbotg2 { + dr_mode =3D "host"; + disable-over-current; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "okay"; + + usb1@1 { + compatible =3D "usb424,9514"; + reg =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + usbnet: ethernet@1 { + compatible =3D "usb424,ec00"; + reg =3D <1>; + local-mac-address =3D [ 00 00 00 00 00 00 ]; + }; + }; +}; + +&usdhc2 { + pinctrl-names =3D "default", "state_100mhz", "state_200mhz"; + pinctrl-0 =3D <&pinctrl_usdhc2>; + pinctrl-1 =3D <&pinctrl_usdhc2_100mhz>; + pinctrl-2 =3D <&pinctrl_usdhc2_200mhz>; + vmmc-supply =3D <®_vdd_3v3>; + vqmmc-supply =3D <®_nvcc_sd>; + cd-gpios =3D <&gpio2 12 GPIO_ACTIVE_LOW>; + status =3D "okay"; +}; + +&iomuxc { + pinctrl_can: cangrp { + fsl,pins =3D < + MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x19 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins =3D < + MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82 + MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82 + MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82 + MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x19 + >; + }; + + pinctrl_ecspi3: ecspi3grp { + fsl,pins =3D < + MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x82 + MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x82 + MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x82 + MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x19 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins =3D < + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 + MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x19 /* PHY RST */ + MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19 /* ETH IRQ */ + >; + }; + + pinctrl_gpio_led: gpioledgrp { + fsl,pins =3D < + MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x19 + MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x19 + MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x19 + >; + }; + + pinctrl_gpio1: gpio1grp { + fsl,pins =3D < + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x19 + MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 + MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 + MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19 + MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19 + MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x19 + MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 + >; + }; + + pinctrl_gpio5: gpio5grp { + fsl,pins =3D < + MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x19 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins =3D < + MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 + MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins =3D < + MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x19 + >; + }; + + pinctrl_reg_usb1_vbus: regusb1vbusgrp { + fsl,pins =3D < + MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x19 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins =3D < + MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x140 + MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x140 + MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x140 + MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x140 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins =3D < + MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x140 + MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x140 + MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x140 + MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x140 + >; + }; + + pinctrl_usb_eth2: usbeth2grp { + fsl,pins =3D < + MX8MM_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x19 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins =3D < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins =3D < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins =3D < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi b/arch= /arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi new file mode 100644 index 000000000000..d8106677366c --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi @@ -0,0 +1,330 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2022 Kontron Electronics GmbH + */ + +#include +#include "imx8mm.dtsi" + +/ { + model =3D "Kontron OSM-S i.MX8MM (N802X SOM)"; + compatible =3D "kontron,imx8mm-osm-s", "fsl,imx8mm"; + + memory@40000000 { + device_type =3D "memory"; + /* + * There are multiple SoM flavors with different DDR sizes. + * The smallest is 1GB. For larger sizes the bootloader will + * update the reg property. + */ + reg =3D <0x0 0x40000000 0 0x80000000>; + }; + + chosen { + stdout-path =3D &uart3; + }; +}; + +&A53_0 { + cpu-supply =3D <®_vdd_arm>; +}; + +&A53_1 { + cpu-supply =3D <®_vdd_arm>; +}; + +&A53_2 { + cpu-supply =3D <®_vdd_arm>; +}; + +&A53_3 { + cpu-supply =3D <®_vdd_arm>; +}; + +&ddrc { + operating-points-v2 =3D <&ddrc_opp_table>; + + ddrc_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-100M { + opp-hz =3D /bits/ 64 <100000000>; + }; + + opp-750M { + opp-hz =3D /bits/ 64 <750000000>; + }; + }; +}; + +&ecspi1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_ecspi1>; + cs-gpios =3D <&gpio5 9 GPIO_ACTIVE_LOW>; + status =3D "okay"; + + flash@0 { + compatible =3D "mxicy,mx25r1635f", "jedec,spi-nor"; + spi-max-frequency =3D <80000000>; + reg =3D <0>; + + partitions { + compatible =3D "fixed-partitions"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + partition@0 { + label =3D "u-boot"; + reg =3D <0x0 0x1E0000>; + }; + + partition@1 { + label =3D "env"; + reg =3D <0x1E0000 0x10000>; + }; + + partition@2 { + label =3D "env_redundant"; + reg =3D <0x1F0000 0x10000>; + }; + }; + }; +}; + +&i2c1 { + clock-frequency =3D <400000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_i2c1>; + status =3D "okay"; + + pca9450: pmic@25 { + compatible =3D "nxp,pca9450a"; + reg =3D <0x25>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_pmic>; + interrupt-parent =3D <&gpio1>; + interrupts =3D <0 IRQ_TYPE_LEVEL_LOW>; + + regulators { + reg_vdd_soc: BUCK1 { + regulator-name =3D "+0V8_VDD_SOC (BUCK1)"; + regulator-min-microvolt =3D <800000>; + regulator-max-microvolt =3D <850000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay =3D <3125>; + nxp,dvs-run-voltage =3D <850000>; + nxp,dvs-standby-voltage =3D <800000>; + }; + + reg_vdd_arm: BUCK2 { + regulator-name =3D "+0V9_VDD_ARM (BUCK2)"; + regulator-min-microvolt =3D <850000>; + regulator-max-microvolt =3D <950000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay =3D <3125>; + nxp,dvs-run-voltage =3D <950000>; + nxp,dvs-standby-voltage =3D <850000>; + }; + + reg_vdd_dram: BUCK3 { + regulator-name =3D "+0V9_VDD_DRAM&PU (BUCK3)"; + regulator-min-microvolt =3D <850000>; + regulator-max-microvolt =3D <950000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_vdd_3v3: BUCK4 { + regulator-name =3D "+3V3 (BUCK4)"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_vdd_1v8: BUCK5 { + regulator-name =3D "+1V8 (BUCK5)"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_nvcc_dram: BUCK6 { + regulator-name =3D "+1V1_NVCC_DRAM (BUCK6)"; + regulator-min-microvolt =3D <1100000>; + regulator-max-microvolt =3D <1100000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_nvcc_snvs: LDO1 { + regulator-name =3D "+1V8_NVCC_SNVS (LDO1)"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_vdd_snvs: LDO2 { + regulator-name =3D "+0V8_VDD_SNVS (LDO2)"; + regulator-min-microvolt =3D <800000>; + regulator-max-microvolt =3D <900000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_vdda: LDO3 { + regulator-name =3D "+1V8_VDDA (LDO3)"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_vdd_phy: LDO4 { + regulator-name =3D "+0V9_VDD_PHY (LDO4)"; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <900000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_nvcc_sd: LDO5 { + regulator-name =3D "NVCC_SD (LDO5)"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + }; + }; + }; + + rtc@52 { + compatible =3D "microcrystal,rv3028"; + reg =3D <0x52>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_rtc>; + interrupts-extended =3D <&gpio4 1 IRQ_TYPE_LEVEL_HIGH>; + trickle-diode-disable; + }; +}; + +&uart3 { /* console */ + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_uart3>; + status =3D "okay"; +}; + +&usdhc1 { + pinctrl-names =3D "default", "state_100mhz", "state_200mhz"; + pinctrl-0 =3D <&pinctrl_usdhc1>; + pinctrl-1 =3D <&pinctrl_usdhc1_100mhz>; + pinctrl-2 =3D <&pinctrl_usdhc1_200mhz>; + vmmc-supply =3D <®_vdd_3v3>; + vqmmc-supply =3D <®_vdd_1v8>; + bus-width =3D <8>; + non-removable; + status =3D "okay"; +}; + +&wdog1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_wdog>; + fsl,ext-reset-output; + status =3D "okay"; +}; + +&iomuxc { + pinctrl_ecspi1: ecspi1grp { + fsl,pins =3D < + MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82 + MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82 + MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82 + MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x19 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins =3D < + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 + MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins =3D < + MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x141 + >; + }; + + pinctrl_rtc: rtcgrp { + fsl,pins =3D < + MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x19 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins =3D < + MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 + MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins =3D < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 + MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d0 + MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d0 + MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d0 + MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d0 + MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x019 + MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x190 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins =3D < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 + MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d4 + MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d4 + MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d4 + MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d4 + MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x019 + MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x194 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins =3D < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 + MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d6 + MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d6 + MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d6 + MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d6 + MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x019 + MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x196 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins =3D < + MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + >; + }; +}; --=20 2.37.1