From nobody Sat Sep 21 20:05:39 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 05007C25B08 for ; Sat, 20 Aug 2022 08:09:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343719AbiHTIJK (ORCPT ); Sat, 20 Aug 2022 04:09:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37280 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343492AbiHTIJE (ORCPT ); Sat, 20 Aug 2022 04:09:04 -0400 Received: from sender4-op-o14.zoho.com (sender4-op-o14.zoho.com [136.143.188.14]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 03D942F64C; Sat, 20 Aug 2022 01:08:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1660982908; cv=none; d=zohomail.com; s=zohoarc; b=hDTtfMFGADU4leAQCyyfEiRVFZTPOgiZPVfXsF+BLFALJdvyJ/9QOJFGT4Tm9Kz0Gx3nZhdjcYS7u3IdmSSxP2SaRJNdbEJXYaerXpVqfX/QUASqAj8XIeLCA7FWizJAXZYtk6R6hoa8Hc7fCendw9dz46a1fTgOPCDy/u33RXo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1660982908; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:To; bh=H5il8SQXZ0PUGfPI0E3JkFSwueZxe2N6hD1oee9wSV4=; b=V9NuqXP7niWx1VRbJoBMSud8WFKugn3VuL3ljCxeC4Nm7WqB1wwF/Tti8ywd1zgB2stJDmqQVdsl8jYsN/gWGv5fLDb2Ti5i0o1JnMmtiDASf346k9BoBLWMZkxk4WL2AwehDOigdOjyXjlA2QpG2SF2OEi9qAdNaF6KNw0fEaA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=arinc9.com; spf=pass smtp.mailfrom=arinc.unal@arinc9.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1660982908; s=zmail; d=arinc9.com; i=arinc.unal@arinc9.com; h=From:From:To:To:Cc:Cc:Subject:Subject:Date:Date:Message-Id:Message-Id:In-Reply-To:References:MIME-Version:Content-Type:Content-Transfer-Encoding:Reply-To; bh=H5il8SQXZ0PUGfPI0E3JkFSwueZxe2N6hD1oee9wSV4=; b=cI5bNPmydzAjF7xjSjgBxboHYUSH40ACRr8wX2klyV8k1gPR+nIm3e/8tIr3z3pi ahRB/Jc2CwNfhBXhBI5tStvjzD3RIqNXUu5SiqOgHoWByko+bWWK22lQFOCVOhNoCXe j/OKWqzRPyas55MKV9YFAG26GOWXRl3dNYBqF8zY= Received: from arinc9-PC.lan (85.117.236.245 [85.117.236.245]) by mx.zohomail.com with SMTPS id 1660982906760707.8277008654304; Sat, 20 Aug 2022 01:08:26 -0700 (PDT) From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Sean Wang , Landen Chao , DENG Qingfang , Frank Wunderlich , Luiz Angelo Daros de Luca , Sander Vanheule , =?UTF-8?q?Ren=C3=A9=20van=20Dorst?= , Daniel Golle , erkin.bozoglu@xeront.com, Sergio Paracuellos Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= Subject: [PATCH v4 3/6] dt-bindings: net: dsa: mediatek,mt7530: update examples Date: Sat, 20 Aug 2022 11:07:55 +0300 Message-Id: <20220820080758.9829-4-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220820080758.9829-1-arinc.unal@arinc9.com> References: <20220820080758.9829-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMailClient: External Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Update the examples on the binding. - Add examples which include a wide variation of configurations. - Make example comments YAML comment instead of DT binding comment. - Add interrupt controller to the examples. Include header file for interrupt. - Change reset line for MT7621 examples. - Pretty formatting for the examples. - Change switch reg to 0. - Change port labels to fit the example, change port 4 label to wan. Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL Reviewed-by: Krzysztof Kozlowski --- .../bindings/net/dsa/mediatek,mt7530.yaml | 402 +++++++++++++++--- 1 file changed, 347 insertions(+), 55 deletions(-) diff --git a/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml= b/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml index 4c99266ce82a..657e162a1c01 100644 --- a/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml +++ b/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml @@ -210,42 +210,111 @@ allOf: unevaluatedProperties: false =20 examples: + # Example 1: Standalone MT7530 - | #include + mdio { #address-cells =3D <1>; #size-cells =3D <0>; + switch@0 { compatible =3D "mediatek,mt7530"; reg =3D <0>; =20 + reset-gpios =3D <&pio 33 0>; + core-supply =3D <&mt6323_vpa_reg>; io-supply =3D <&mt6323_vemc3v3_reg>; - reset-gpios =3D <&pio 33 GPIO_ACTIVE_HIGH>; =20 ethernet-ports { #address-cells =3D <1>; #size-cells =3D <0>; + port@0 { reg =3D <0>; - label =3D "lan0"; + label =3D "lan1"; }; =20 port@1 { reg =3D <1>; - label =3D "lan1"; + label =3D "lan2"; }; =20 port@2 { reg =3D <2>; - label =3D "lan2"; + label =3D "lan3"; }; =20 port@3 { reg =3D <3>; + label =3D "lan4"; + }; + + port@4 { + reg =3D <4>; + label =3D "wan"; + }; + + port@6 { + reg =3D <6>; + label =3D "cpu"; + ethernet =3D <&gmac0>; + phy-mode =3D "rgmii"; + + fixed-link { + speed =3D <1000>; + full-duplex; + pause; + }; + }; + }; + }; + }; + + # Example 2: MT7530 in MT7623AI SoC + - | + #include + + mdio { + #address-cells =3D <1>; + #size-cells =3D <0>; + + switch@0 { + compatible =3D "mediatek,mt7530"; + reg =3D <0>; + + mediatek,mcm; + resets =3D <ðsys MT2701_ETHSYS_MCM_RST>; + reset-names =3D "mcm"; + + core-supply =3D <&mt6323_vpa_reg>; + io-supply =3D <&mt6323_vemc3v3_reg>; + + ethernet-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + label =3D "lan1"; + }; + + port@1 { + reg =3D <1>; + label =3D "lan2"; + }; + + port@2 { + reg =3D <2>; label =3D "lan3"; }; =20 + port@3 { + reg =3D <3>; + label =3D "lan4"; + }; + port@4 { reg =3D <4>; label =3D "wan"; @@ -256,85 +325,219 @@ examples: label =3D "cpu"; ethernet =3D <&gmac0>; phy-mode =3D "trgmii"; + fixed-link { speed =3D <1000>; full-duplex; + pause; }; }; }; }; }; =20 + # Example 3: Standalone MT7531 - | - //Example 2: MT7621: Port 4 is WAN port: 2nd GMAC -> Port 5 -> PHY por= t 4. + #include + #include =20 - ethernet { + mdio { #address-cells =3D <1>; #size-cells =3D <0>; - gmac0: mac@0 { - compatible =3D "mediatek,eth-mac"; + + switch@0 { + compatible =3D "mediatek,mt7531"; reg =3D <0>; - phy-mode =3D "rgmii"; =20 - fixed-link { - speed =3D <1000>; - full-duplex; - pause; + reset-gpios =3D <&pio 54 0>; + + interrupt-controller; + #interrupt-cells =3D <1>; + interrupt-parent =3D <&pio>; + interrupts =3D <53 IRQ_TYPE_LEVEL_HIGH>; + + ethernet-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + label =3D "lan1"; + }; + + port@1 { + reg =3D <1>; + label =3D "lan2"; + }; + + port@2 { + reg =3D <2>; + label =3D "lan3"; + }; + + port@3 { + reg =3D <3>; + label =3D "lan4"; + }; + + port@4 { + reg =3D <4>; + label =3D "wan"; + }; + + port@6 { + reg =3D <6>; + label =3D "cpu"; + ethernet =3D <&gmac0>; + phy-mode =3D "2500base-x"; + + fixed-link { + speed =3D <2500>; + full-duplex; + pause; + }; + }; }; }; + }; + + # Example 4: MT7530 in MT7621AT, MT7621DAT and MT7621ST SoCs + - | + #include + #include =20 - gmac1: mac@1 { + mdio { + #address-cells =3D <1>; + #size-cells =3D <0>; + + switch@0 { + compatible =3D "mediatek,mt7621"; + reg =3D <0>; + + mediatek,mcm; + resets =3D <&sysc MT7621_RST_MCM>; + reset-names =3D "mcm"; + + interrupt-controller; + #interrupt-cells =3D <1>; + interrupt-parent =3D <&gic>; + interrupts =3D ; + + ethernet-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + label =3D "lan1"; + }; + + port@1 { + reg =3D <1>; + label =3D "lan2"; + }; + + port@2 { + reg =3D <2>; + label =3D "lan3"; + }; + + port@3 { + reg =3D <3>; + label =3D "lan4"; + }; + + port@4 { + reg =3D <4>; + label =3D "wan"; + }; + + port@6 { + reg =3D <6>; + label =3D "cpu"; + ethernet =3D <&gmac0>; + phy-mode =3D "trgmii"; + + fixed-link { + speed =3D <1000>; + full-duplex; + pause; + }; + }; + }; + }; + }; + + # Example 5: MT7621: mux MT7530's phy4 to SoC's gmac1 + - | + #include + #include + + ethernet { + #address-cells =3D <1>; + #size-cells =3D <0>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&rgmii2_pins>; + + mac@1 { compatible =3D "mediatek,eth-mac"; reg =3D <1>; - phy-mode =3D "rgmii-txid"; - phy-handle =3D <&phy4>; + + phy-mode =3D "rgmii"; + phy-handle =3D <&example5_ethphy4>; }; =20 - mdio: mdio-bus { + mdio { #address-cells =3D <1>; #size-cells =3D <0>; =20 - /* Internal phy */ - phy4: ethernet-phy@4 { + /* MT7530's phy4 */ + example5_ethphy4: ethernet-phy@4 { reg =3D <4>; }; =20 - mt7530: switch@1f { + switch@0 { compatible =3D "mediatek,mt7621"; - reg =3D <0x1f>; - mediatek,mcm; + reg =3D <0>; =20 - resets =3D <&rstctrl 2>; + mediatek,mcm; + resets =3D <&sysc MT7621_RST_MCM>; reset-names =3D "mcm"; =20 + interrupt-controller; + #interrupt-cells =3D <1>; + interrupt-parent =3D <&gic>; + interrupts =3D ; + ethernet-ports { #address-cells =3D <1>; #size-cells =3D <0>; =20 port@0 { reg =3D <0>; - label =3D "lan0"; + label =3D "lan1"; }; =20 port@1 { reg =3D <1>; - label =3D "lan1"; + label =3D "lan2"; }; =20 port@2 { reg =3D <2>; - label =3D "lan2"; + label =3D "lan3"; }; =20 port@3 { reg =3D <3>; - label =3D "lan3"; + label =3D "lan4"; }; =20 - /* Commented out. Port 4 is handled by 2nd GMAC. + /* Commented out, phy4 is muxed to gmac1. port@4 { reg =3D <4>; - label =3D "lan4"; + label =3D "wan"; }; */ =20 @@ -342,7 +545,7 @@ examples: reg =3D <6>; label =3D "cpu"; ethernet =3D <&gmac0>; - phy-mode =3D "rgmii"; + phy-mode =3D "trgmii"; =20 fixed-link { speed =3D <1000>; @@ -355,82 +558,171 @@ examples: }; }; =20 + # Example 6: MT7621: mux external phy to SoC's gmac1 - | - //Example 3: MT7621: Port 5 is connected to external PHY: Port 5 -> ex= ternal PHY. + #include + #include =20 ethernet { #address-cells =3D <1>; #size-cells =3D <0>; - gmac_0: mac@0 { + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&rgmii2_pins>; + + mac@1 { compatible =3D "mediatek,eth-mac"; - reg =3D <0>; + reg =3D <1>; + phy-mode =3D "rgmii"; + phy-handle =3D <&example6_ethphy7>; + }; + + mdio { + #address-cells =3D <1>; + #size-cells =3D <0>; + + /* External PHY */ + example6_ethphy7: ethernet-phy@7 { + reg =3D <7>; + phy-mode =3D "rgmii"; + }; + + switch@0 { + compatible =3D "mediatek,mt7621"; + reg =3D <0>; + + mediatek,mcm; + resets =3D <&sysc MT7621_RST_MCM>; + reset-names =3D "mcm"; + + interrupt-controller; + #interrupt-cells =3D <1>; + interrupt-parent =3D <&gic>; + interrupts =3D ; + + ethernet-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + label =3D "lan1"; + }; + + port@1 { + reg =3D <1>; + label =3D "lan2"; + }; + + port@2 { + reg =3D <2>; + label =3D "lan3"; + }; + + port@3 { + reg =3D <3>; + label =3D "lan4"; + }; + + port@4 { + reg =3D <4>; + label =3D "wan"; + }; =20 - fixed-link { - speed =3D <1000>; - full-duplex; - pause; + port@6 { + reg =3D <6>; + label =3D "cpu"; + ethernet =3D <&gmac0>; + phy-mode =3D "trgmii"; + + fixed-link { + speed =3D <1000>; + full-duplex; + pause; + }; + }; + }; }; }; + }; =20 - mdio0: mdio-bus { + # Example 7: MT7621: mux external phy to MT7530's port 5 + - | + #include + #include + + ethernet { + #address-cells =3D <1>; + #size-cells =3D <0>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&rgmii2_pins>; + + mdio { #address-cells =3D <1>; #size-cells =3D <0>; =20 - /* External phy */ - ephy5: ethernet-phy@7 { + /* External PHY */ + example7_ethphy7: ethernet-phy@7 { reg =3D <7>; + phy-mode =3D "rgmii"; }; =20 - switch@1f { + switch@0 { compatible =3D "mediatek,mt7621"; - reg =3D <0x1f>; - mediatek,mcm; + reg =3D <0>; =20 - resets =3D <&rstctrl 2>; + mediatek,mcm; + resets =3D <&sysc MT7621_RST_MCM>; reset-names =3D "mcm"; =20 + interrupt-controller; + #interrupt-cells =3D <1>; + interrupt-parent =3D <&gic>; + interrupts =3D ; + ethernet-ports { #address-cells =3D <1>; #size-cells =3D <0>; =20 port@0 { reg =3D <0>; - label =3D "lan0"; + label =3D "lan1"; }; =20 port@1 { reg =3D <1>; - label =3D "lan1"; + label =3D "lan2"; }; =20 port@2 { reg =3D <2>; - label =3D "lan2"; + label =3D "lan3"; }; =20 port@3 { reg =3D <3>; - label =3D "lan3"; + label =3D "lan4"; }; =20 port@4 { reg =3D <4>; - label =3D "lan4"; + label =3D "wan"; }; =20 port@5 { reg =3D <5>; - label =3D "lan5"; - phy-mode =3D "rgmii"; - phy-handle =3D <&ephy5>; + label =3D "extphy"; + phy-mode =3D "rgmii-txid"; + phy-handle =3D <&example7_ethphy7>; }; =20 - cpu_port0: port@6 { + port@6 { reg =3D <6>; label =3D "cpu"; - ethernet =3D <&gmac_0>; - phy-mode =3D "rgmii"; + ethernet =3D <&gmac0>; + phy-mode =3D "trgmii"; =20 fixed-link { speed =3D <1000>; --=20 2.34.1