From nobody Sat Sep 21 17:33:56 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3B110C25B08 for ; Sat, 20 Aug 2022 08:09:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245699AbiHTIJB (ORCPT ); Sat, 20 Aug 2022 04:09:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36390 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245366AbiHTIIt (ORCPT ); Sat, 20 Aug 2022 04:08:49 -0400 Received: from sender4-op-o14.zoho.com (sender4-op-o14.zoho.com [136.143.188.14]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6FA5E2F3B6; Sat, 20 Aug 2022 01:08:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1660982894; cv=none; d=zohomail.com; s=zohoarc; b=YOeZ9FT04CzN0C/UWm5C7tbvuOXCEzhNJblGjACAtVEgAxhp/eOgw924CV5umlr9Y59lk3a22T5HEBu8t89Oh0jnb6CcrAmDcJWf6ts+swOyqLtNbQzmupHg11LFJzs4pyQjKZxhHYHP9MaYEPpSANMfdPXz2NHfLqA1MRYbkGU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1660982894; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:To; bh=wpAUAfc07ylNY9oSdQ6DPJcvSW66IDwq4Ksnwpr1SWA=; b=Q0VFI8DnLd9MjtYVc6ugauo++fjQdyoRAmwvZo40/cXYEtSdhqKR/qcos23ld4EqhklJe9tPTwHTCLpxdGEKqb+2nNVzaUhy52iWs55FMo4ljFJPFR/LNBY2rZq48eV0ggeweCSz4MmSNdN4SNjd7kOI438cRv9VuuaUINYmCmA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=arinc9.com; spf=pass smtp.mailfrom=arinc.unal@arinc9.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1660982894; s=zmail; d=arinc9.com; i=arinc.unal@arinc9.com; h=From:From:To:To:Cc:Cc:Subject:Subject:Date:Date:Message-Id:Message-Id:In-Reply-To:References:MIME-Version:Content-Type:Content-Transfer-Encoding:Reply-To; bh=wpAUAfc07ylNY9oSdQ6DPJcvSW66IDwq4Ksnwpr1SWA=; b=FeJCBVjwtBZQZ70KyoAhs5579I8g2nQF9vwvSMQa6Qg7ItpqcNDgHgAEVFT//Cms UOEqQKB/cVEPObMHqkCdZNOSC22LS3KwNZbn+fsRwJqbkxz52CZt7QGJJRqyYPMxWbQ hrdpY1ZoPUY0PbxnHkKCJq5Ljqlsyh2mxi8MFvMg= Received: from arinc9-PC.lan (85.117.236.245 [85.117.236.245]) by mx.zohomail.com with SMTPS id 1660982893605333.7936453980019; Sat, 20 Aug 2022 01:08:13 -0700 (PDT) From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Sean Wang , Landen Chao , DENG Qingfang , Frank Wunderlich , Luiz Angelo Daros de Luca , Sander Vanheule , =?UTF-8?q?Ren=C3=A9=20van=20Dorst?= , Daniel Golle , erkin.bozoglu@xeront.com, Sergio Paracuellos Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Rob Herring Subject: [PATCH v4 1/6] dt-bindings: net: dsa: mediatek,mt7530: make trivial changes Date: Sat, 20 Aug 2022 11:07:53 +0300 Message-Id: <20220820080758.9829-2-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220820080758.9829-1-arinc.unal@arinc9.com> References: <20220820080758.9829-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMailClient: External Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Make trivial changes on the binding. - Update title to include MT7531 switch. - Add me as a maintainer. List maintainers in alphabetical order by first name. - Add description to compatible strings. - Stretch descriptions up to the 80 character limit. - Remove quotes from $ref: "dsa.yaml#". Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL Reviewed-by: Rob Herring --- .../bindings/net/dsa/mediatek,mt7530.yaml | 36 ++++++++++++------- 1 file changed, 24 insertions(+), 12 deletions(-) diff --git a/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml= b/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml index 17ab6c69ecc7..edf48e917173 100644 --- a/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml +++ b/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml @@ -4,12 +4,13 @@ $id: http://devicetree.org/schemas/net/dsa/mediatek,mt7530.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 -title: Mediatek MT7530 Ethernet switch +title: Mediatek MT7530 and MT7531 Ethernet Switches =20 maintainers: - - Sean Wang + - Ar=C4=B1n=C3=A7 =C3=9CNAL - Landen Chao - DENG Qingfang + - Sean Wang =20 description: | Port 5 of mt7530 and mt7621 switch is muxed between: @@ -61,10 +62,21 @@ description: | =20 properties: compatible: - enum: - - mediatek,mt7530 - - mediatek,mt7531 - - mediatek,mt7621 + oneOf: + - description: + Standalone MT7530 and multi-chip module MT7530 in MT7623AI SoC + items: + - const: mediatek,mt7530 + + - description: + Standalone MT7531 + items: + - const: mediatek,mt7531 + + - description: + Multi-chip module MT7530 in MT7621AT, MT7621DAT and MT7621ST SoCs + items: + - const: mediatek,mt7621 =20 reg: maxItems: 1 @@ -79,7 +91,7 @@ properties: gpio-controller: type: boolean description: - if defined, MT7530's LED controller will run on GPIO mode. + If defined, MT7530's LED controller will run on GPIO mode. =20 "#interrupt-cells": const: 1 @@ -92,8 +104,8 @@ properties: io-supply: description: Phandle to the regulator node necessary for the I/O power. - See Documentation/devicetree/bindings/regulator/mt6323-regulator.txt - for details for the regulator setup on these boards. + See Documentation/devicetree/bindings/regulator/mt6323-regulator.txt= for + details for the regulator setup on these boards. =20 mediatek,mcm: type: boolean @@ -110,8 +122,8 @@ properties: =20 resets: description: - Phandle pointing to the system reset controller with line index for - the ethsys. + Phandle pointing to the system reset controller with line index for = the + ethsys. maxItems: 1 =20 patternProperties: @@ -148,7 +160,7 @@ required: - reg =20 allOf: - - $ref: "dsa.yaml#" + - $ref: dsa.yaml# - if: required: - mediatek,mcm --=20 2.34.1 From nobody Sat Sep 21 17:33:56 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CCDA3C32772 for ; Sat, 20 Aug 2022 08:09:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343563AbiHTIJF (ORCPT ); Sat, 20 Aug 2022 04:09:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36606 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244490AbiHTIIw (ORCPT ); Sat, 20 Aug 2022 04:08:52 -0400 Received: from sender4-op-o14.zoho.com (sender4-op-o14.zoho.com [136.143.188.14]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 90EC42F64C; Sat, 20 Aug 2022 01:08:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1660982902; cv=none; d=zohomail.com; s=zohoarc; b=mZwnCnw/I9j9729ntS6rn8mobpC+O5bS/R5GDikNlEz7Ko2wqnXZ9O+kFVGJfpUSgcMh7km2cmZ0zZ4YtmyrXJv3QjHCoHL9TSlryIqeW6knezOvGLUdmO7XIrO4dWV5r5NrzXYM6DHHvZNm8Q7xqhNWRZPtOT3cw7vOMXPGXmE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1660982902; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:To; bh=tUPXDCTkwC2zhPMuq078yFzwDdf8nbUXFo0CgcNnnAg=; b=YbxZtEiS7jwHD/oY1oJ1PaCiALs6LmTztXAo9IHUYZl4VIVTJqk880Q6eSW+Fg9PMfvYq+7kR2EVb6JATAwK63caZLqsZdgfO/EKzQpZj567HbA0xpPO4JEZjrJcYCS1kgeQ6QgwIHaG4httWhJmYhsGZ2n0QUvaV62KAXypVsY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=arinc9.com; spf=pass smtp.mailfrom=arinc.unal@arinc9.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1660982902; s=zmail; d=arinc9.com; i=arinc.unal@arinc9.com; h=From:From:To:To:Cc:Cc:Subject:Subject:Date:Date:Message-Id:Message-Id:In-Reply-To:References:MIME-Version:Content-Type:Content-Transfer-Encoding:Reply-To; bh=tUPXDCTkwC2zhPMuq078yFzwDdf8nbUXFo0CgcNnnAg=; b=ZsyKWtpwLDIsS8+gp+14ph2uuQ+7XN319c/hs19p60cvDP1yKBqzTQNK04iPT+LD negUduhs/h8F3M5EzQ2FxVss0b9SNW9ZQGV7WxPPrpJdcNqVXJoqMvfM/XGBY8v/O6C pjhmIQR5BAIn3DFyZp5zEgLVeg+XiMY2FBSqfTcI= Received: from arinc9-PC.lan (85.117.236.245 [85.117.236.245]) by mx.zohomail.com with SMTPS id 1660982899965135.9434403903507; Sat, 20 Aug 2022 01:08:19 -0700 (PDT) From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Sean Wang , Landen Chao , DENG Qingfang , Frank Wunderlich , Luiz Angelo Daros de Luca , Sander Vanheule , =?UTF-8?q?Ren=C3=A9=20van=20Dorst?= , Daniel Golle , erkin.bozoglu@xeront.com, Sergio Paracuellos Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= Subject: [PATCH v4 2/6] dt-bindings: net: dsa: mediatek,mt7530: fix reset lines Date: Sat, 20 Aug 2022 11:07:54 +0300 Message-Id: <20220820080758.9829-3-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220820080758.9829-1-arinc.unal@arinc9.com> References: <20220820080758.9829-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMailClient: External Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org - Fix description of mediatek,mcm. mediatek,mcm is not used on MT7623NI. - Add description for reset-gpios. - Invalidate reset-gpios if mediatek,mcm is used. We cannot use multiple reset lines at the same time. - Invalidate mediatek,mcm if the compatible device is mediatek,mt7531. There is no multi-chip module version of mediatek,mt7531. - Require mediatek,mcm for mediatek,mt7621 as the compatible string is only used for the multi-chip module version of MT7530. Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL --- .../bindings/net/dsa/mediatek,mt7530.yaml | 31 +++++++++++++++++-- 1 file changed, 28 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml= b/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml index edf48e917173..4c99266ce82a 100644 --- a/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml +++ b/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml @@ -110,11 +110,15 @@ properties: mediatek,mcm: type: boolean description: - if defined, indicates that either MT7530 is the part on multi-chip - module belong to MT7623A has or the remotely standalone chip as the - function MT7623N reference board provided for. + Used for MT7621AT, MT7621DAT, MT7621ST and MT7623AI SoCs which the M= T7530 + switch is a part of the multi-chip module. =20 reset-gpios: + description: + GPIO to reset the switch. Use this if mediatek,mcm is not used. + This property is optional because some boards share the reset line w= ith + other components which makes it impossible to probe the switch if the + reset line is used. maxItems: 1 =20 reset-names: @@ -165,6 +169,9 @@ allOf: required: - mediatek,mcm then: + properties: + reset-gpios: false + required: - resets - reset-names @@ -182,6 +189,24 @@ allOf: - core-supply - io-supply =20 + - if: + properties: + compatible: + items: + - const: mediatek,mt7531 + then: + properties: + mediatek,mcm: false + + - if: + properties: + compatible: + items: + - const: mediatek,mt7621 + then: + required: + - mediatek,mcm + unevaluatedProperties: false =20 examples: --=20 2.34.1 From nobody Sat Sep 21 17:33:56 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 05007C25B08 for ; Sat, 20 Aug 2022 08:09:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343719AbiHTIJK (ORCPT ); Sat, 20 Aug 2022 04:09:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37280 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343492AbiHTIJE (ORCPT ); Sat, 20 Aug 2022 04:09:04 -0400 Received: from sender4-op-o14.zoho.com (sender4-op-o14.zoho.com [136.143.188.14]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 03D942F64C; Sat, 20 Aug 2022 01:08:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1660982908; cv=none; d=zohomail.com; s=zohoarc; b=hDTtfMFGADU4leAQCyyfEiRVFZTPOgiZPVfXsF+BLFALJdvyJ/9QOJFGT4Tm9Kz0Gx3nZhdjcYS7u3IdmSSxP2SaRJNdbEJXYaerXpVqfX/QUASqAj8XIeLCA7FWizJAXZYtk6R6hoa8Hc7fCendw9dz46a1fTgOPCDy/u33RXo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1660982908; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:To; bh=H5il8SQXZ0PUGfPI0E3JkFSwueZxe2N6hD1oee9wSV4=; b=V9NuqXP7niWx1VRbJoBMSud8WFKugn3VuL3ljCxeC4Nm7WqB1wwF/Tti8ywd1zgB2stJDmqQVdsl8jYsN/gWGv5fLDb2Ti5i0o1JnMmtiDASf346k9BoBLWMZkxk4WL2AwehDOigdOjyXjlA2QpG2SF2OEi9qAdNaF6KNw0fEaA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=arinc9.com; spf=pass smtp.mailfrom=arinc.unal@arinc9.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1660982908; s=zmail; d=arinc9.com; i=arinc.unal@arinc9.com; h=From:From:To:To:Cc:Cc:Subject:Subject:Date:Date:Message-Id:Message-Id:In-Reply-To:References:MIME-Version:Content-Type:Content-Transfer-Encoding:Reply-To; bh=H5il8SQXZ0PUGfPI0E3JkFSwueZxe2N6hD1oee9wSV4=; b=cI5bNPmydzAjF7xjSjgBxboHYUSH40ACRr8wX2klyV8k1gPR+nIm3e/8tIr3z3pi ahRB/Jc2CwNfhBXhBI5tStvjzD3RIqNXUu5SiqOgHoWByko+bWWK22lQFOCVOhNoCXe j/OKWqzRPyas55MKV9YFAG26GOWXRl3dNYBqF8zY= Received: from arinc9-PC.lan (85.117.236.245 [85.117.236.245]) by mx.zohomail.com with SMTPS id 1660982906760707.8277008654304; Sat, 20 Aug 2022 01:08:26 -0700 (PDT) From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Sean Wang , Landen Chao , DENG Qingfang , Frank Wunderlich , Luiz Angelo Daros de Luca , Sander Vanheule , =?UTF-8?q?Ren=C3=A9=20van=20Dorst?= , Daniel Golle , erkin.bozoglu@xeront.com, Sergio Paracuellos Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= Subject: [PATCH v4 3/6] dt-bindings: net: dsa: mediatek,mt7530: update examples Date: Sat, 20 Aug 2022 11:07:55 +0300 Message-Id: <20220820080758.9829-4-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220820080758.9829-1-arinc.unal@arinc9.com> References: <20220820080758.9829-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMailClient: External Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Update the examples on the binding. - Add examples which include a wide variation of configurations. - Make example comments YAML comment instead of DT binding comment. - Add interrupt controller to the examples. Include header file for interrupt. - Change reset line for MT7621 examples. - Pretty formatting for the examples. - Change switch reg to 0. - Change port labels to fit the example, change port 4 label to wan. Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL Reviewed-by: Krzysztof Kozlowski --- .../bindings/net/dsa/mediatek,mt7530.yaml | 402 +++++++++++++++--- 1 file changed, 347 insertions(+), 55 deletions(-) diff --git a/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml= b/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml index 4c99266ce82a..657e162a1c01 100644 --- a/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml +++ b/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml @@ -210,42 +210,111 @@ allOf: unevaluatedProperties: false =20 examples: + # Example 1: Standalone MT7530 - | #include + mdio { #address-cells =3D <1>; #size-cells =3D <0>; + switch@0 { compatible =3D "mediatek,mt7530"; reg =3D <0>; =20 + reset-gpios =3D <&pio 33 0>; + core-supply =3D <&mt6323_vpa_reg>; io-supply =3D <&mt6323_vemc3v3_reg>; - reset-gpios =3D <&pio 33 GPIO_ACTIVE_HIGH>; =20 ethernet-ports { #address-cells =3D <1>; #size-cells =3D <0>; + port@0 { reg =3D <0>; - label =3D "lan0"; + label =3D "lan1"; }; =20 port@1 { reg =3D <1>; - label =3D "lan1"; + label =3D "lan2"; }; =20 port@2 { reg =3D <2>; - label =3D "lan2"; + label =3D "lan3"; }; =20 port@3 { reg =3D <3>; + label =3D "lan4"; + }; + + port@4 { + reg =3D <4>; + label =3D "wan"; + }; + + port@6 { + reg =3D <6>; + label =3D "cpu"; + ethernet =3D <&gmac0>; + phy-mode =3D "rgmii"; + + fixed-link { + speed =3D <1000>; + full-duplex; + pause; + }; + }; + }; + }; + }; + + # Example 2: MT7530 in MT7623AI SoC + - | + #include + + mdio { + #address-cells =3D <1>; + #size-cells =3D <0>; + + switch@0 { + compatible =3D "mediatek,mt7530"; + reg =3D <0>; + + mediatek,mcm; + resets =3D <ðsys MT2701_ETHSYS_MCM_RST>; + reset-names =3D "mcm"; + + core-supply =3D <&mt6323_vpa_reg>; + io-supply =3D <&mt6323_vemc3v3_reg>; + + ethernet-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + label =3D "lan1"; + }; + + port@1 { + reg =3D <1>; + label =3D "lan2"; + }; + + port@2 { + reg =3D <2>; label =3D "lan3"; }; =20 + port@3 { + reg =3D <3>; + label =3D "lan4"; + }; + port@4 { reg =3D <4>; label =3D "wan"; @@ -256,85 +325,219 @@ examples: label =3D "cpu"; ethernet =3D <&gmac0>; phy-mode =3D "trgmii"; + fixed-link { speed =3D <1000>; full-duplex; + pause; }; }; }; }; }; =20 + # Example 3: Standalone MT7531 - | - //Example 2: MT7621: Port 4 is WAN port: 2nd GMAC -> Port 5 -> PHY por= t 4. + #include + #include =20 - ethernet { + mdio { #address-cells =3D <1>; #size-cells =3D <0>; - gmac0: mac@0 { - compatible =3D "mediatek,eth-mac"; + + switch@0 { + compatible =3D "mediatek,mt7531"; reg =3D <0>; - phy-mode =3D "rgmii"; =20 - fixed-link { - speed =3D <1000>; - full-duplex; - pause; + reset-gpios =3D <&pio 54 0>; + + interrupt-controller; + #interrupt-cells =3D <1>; + interrupt-parent =3D <&pio>; + interrupts =3D <53 IRQ_TYPE_LEVEL_HIGH>; + + ethernet-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + label =3D "lan1"; + }; + + port@1 { + reg =3D <1>; + label =3D "lan2"; + }; + + port@2 { + reg =3D <2>; + label =3D "lan3"; + }; + + port@3 { + reg =3D <3>; + label =3D "lan4"; + }; + + port@4 { + reg =3D <4>; + label =3D "wan"; + }; + + port@6 { + reg =3D <6>; + label =3D "cpu"; + ethernet =3D <&gmac0>; + phy-mode =3D "2500base-x"; + + fixed-link { + speed =3D <2500>; + full-duplex; + pause; + }; + }; }; }; + }; + + # Example 4: MT7530 in MT7621AT, MT7621DAT and MT7621ST SoCs + - | + #include + #include =20 - gmac1: mac@1 { + mdio { + #address-cells =3D <1>; + #size-cells =3D <0>; + + switch@0 { + compatible =3D "mediatek,mt7621"; + reg =3D <0>; + + mediatek,mcm; + resets =3D <&sysc MT7621_RST_MCM>; + reset-names =3D "mcm"; + + interrupt-controller; + #interrupt-cells =3D <1>; + interrupt-parent =3D <&gic>; + interrupts =3D ; + + ethernet-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + label =3D "lan1"; + }; + + port@1 { + reg =3D <1>; + label =3D "lan2"; + }; + + port@2 { + reg =3D <2>; + label =3D "lan3"; + }; + + port@3 { + reg =3D <3>; + label =3D "lan4"; + }; + + port@4 { + reg =3D <4>; + label =3D "wan"; + }; + + port@6 { + reg =3D <6>; + label =3D "cpu"; + ethernet =3D <&gmac0>; + phy-mode =3D "trgmii"; + + fixed-link { + speed =3D <1000>; + full-duplex; + pause; + }; + }; + }; + }; + }; + + # Example 5: MT7621: mux MT7530's phy4 to SoC's gmac1 + - | + #include + #include + + ethernet { + #address-cells =3D <1>; + #size-cells =3D <0>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&rgmii2_pins>; + + mac@1 { compatible =3D "mediatek,eth-mac"; reg =3D <1>; - phy-mode =3D "rgmii-txid"; - phy-handle =3D <&phy4>; + + phy-mode =3D "rgmii"; + phy-handle =3D <&example5_ethphy4>; }; =20 - mdio: mdio-bus { + mdio { #address-cells =3D <1>; #size-cells =3D <0>; =20 - /* Internal phy */ - phy4: ethernet-phy@4 { + /* MT7530's phy4 */ + example5_ethphy4: ethernet-phy@4 { reg =3D <4>; }; =20 - mt7530: switch@1f { + switch@0 { compatible =3D "mediatek,mt7621"; - reg =3D <0x1f>; - mediatek,mcm; + reg =3D <0>; =20 - resets =3D <&rstctrl 2>; + mediatek,mcm; + resets =3D <&sysc MT7621_RST_MCM>; reset-names =3D "mcm"; =20 + interrupt-controller; + #interrupt-cells =3D <1>; + interrupt-parent =3D <&gic>; + interrupts =3D ; + ethernet-ports { #address-cells =3D <1>; #size-cells =3D <0>; =20 port@0 { reg =3D <0>; - label =3D "lan0"; + label =3D "lan1"; }; =20 port@1 { reg =3D <1>; - label =3D "lan1"; + label =3D "lan2"; }; =20 port@2 { reg =3D <2>; - label =3D "lan2"; + label =3D "lan3"; }; =20 port@3 { reg =3D <3>; - label =3D "lan3"; + label =3D "lan4"; }; =20 - /* Commented out. Port 4 is handled by 2nd GMAC. + /* Commented out, phy4 is muxed to gmac1. port@4 { reg =3D <4>; - label =3D "lan4"; + label =3D "wan"; }; */ =20 @@ -342,7 +545,7 @@ examples: reg =3D <6>; label =3D "cpu"; ethernet =3D <&gmac0>; - phy-mode =3D "rgmii"; + phy-mode =3D "trgmii"; =20 fixed-link { speed =3D <1000>; @@ -355,82 +558,171 @@ examples: }; }; =20 + # Example 6: MT7621: mux external phy to SoC's gmac1 - | - //Example 3: MT7621: Port 5 is connected to external PHY: Port 5 -> ex= ternal PHY. + #include + #include =20 ethernet { #address-cells =3D <1>; #size-cells =3D <0>; - gmac_0: mac@0 { + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&rgmii2_pins>; + + mac@1 { compatible =3D "mediatek,eth-mac"; - reg =3D <0>; + reg =3D <1>; + phy-mode =3D "rgmii"; + phy-handle =3D <&example6_ethphy7>; + }; + + mdio { + #address-cells =3D <1>; + #size-cells =3D <0>; + + /* External PHY */ + example6_ethphy7: ethernet-phy@7 { + reg =3D <7>; + phy-mode =3D "rgmii"; + }; + + switch@0 { + compatible =3D "mediatek,mt7621"; + reg =3D <0>; + + mediatek,mcm; + resets =3D <&sysc MT7621_RST_MCM>; + reset-names =3D "mcm"; + + interrupt-controller; + #interrupt-cells =3D <1>; + interrupt-parent =3D <&gic>; + interrupts =3D ; + + ethernet-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + label =3D "lan1"; + }; + + port@1 { + reg =3D <1>; + label =3D "lan2"; + }; + + port@2 { + reg =3D <2>; + label =3D "lan3"; + }; + + port@3 { + reg =3D <3>; + label =3D "lan4"; + }; + + port@4 { + reg =3D <4>; + label =3D "wan"; + }; =20 - fixed-link { - speed =3D <1000>; - full-duplex; - pause; + port@6 { + reg =3D <6>; + label =3D "cpu"; + ethernet =3D <&gmac0>; + phy-mode =3D "trgmii"; + + fixed-link { + speed =3D <1000>; + full-duplex; + pause; + }; + }; + }; }; }; + }; =20 - mdio0: mdio-bus { + # Example 7: MT7621: mux external phy to MT7530's port 5 + - | + #include + #include + + ethernet { + #address-cells =3D <1>; + #size-cells =3D <0>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&rgmii2_pins>; + + mdio { #address-cells =3D <1>; #size-cells =3D <0>; =20 - /* External phy */ - ephy5: ethernet-phy@7 { + /* External PHY */ + example7_ethphy7: ethernet-phy@7 { reg =3D <7>; + phy-mode =3D "rgmii"; }; =20 - switch@1f { + switch@0 { compatible =3D "mediatek,mt7621"; - reg =3D <0x1f>; - mediatek,mcm; + reg =3D <0>; =20 - resets =3D <&rstctrl 2>; + mediatek,mcm; + resets =3D <&sysc MT7621_RST_MCM>; reset-names =3D "mcm"; =20 + interrupt-controller; + #interrupt-cells =3D <1>; + interrupt-parent =3D <&gic>; + interrupts =3D ; + ethernet-ports { #address-cells =3D <1>; #size-cells =3D <0>; =20 port@0 { reg =3D <0>; - label =3D "lan0"; + label =3D "lan1"; }; =20 port@1 { reg =3D <1>; - label =3D "lan1"; + label =3D "lan2"; }; =20 port@2 { reg =3D <2>; - label =3D "lan2"; + label =3D "lan3"; }; =20 port@3 { reg =3D <3>; - label =3D "lan3"; + label =3D "lan4"; }; =20 port@4 { reg =3D <4>; - label =3D "lan4"; + label =3D "wan"; }; =20 port@5 { reg =3D <5>; - label =3D "lan5"; - phy-mode =3D "rgmii"; - phy-handle =3D <&ephy5>; + label =3D "extphy"; + phy-mode =3D "rgmii-txid"; + phy-handle =3D <&example7_ethphy7>; }; =20 - cpu_port0: port@6 { + port@6 { reg =3D <6>; label =3D "cpu"; - ethernet =3D <&gmac_0>; - phy-mode =3D "rgmii"; + ethernet =3D <&gmac0>; + phy-mode =3D "trgmii"; =20 fixed-link { speed =3D <1000>; --=20 2.34.1 From nobody Sat Sep 21 17:33:56 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 36887C32774 for ; Sat, 20 Aug 2022 08:09:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343851AbiHTIJS (ORCPT ); Sat, 20 Aug 2022 04:09:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37396 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343595AbiHTIJG (ORCPT ); Sat, 20 Aug 2022 04:09:06 -0400 Received: from sender4-op-o14.zoho.com (sender4-op-o14.zoho.com [136.143.188.14]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DEAC32F64C; Sat, 20 Aug 2022 01:09:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1660982914; cv=none; d=zohomail.com; s=zohoarc; b=Cw+s+Ut4zFB2EFf5KX8jrEmghyXXyMk8ToPt/Sqil5andrBgX+SR/GSzNqHjtVteskjYjtCrP3NZIINPYC0OTHQiaITEmab6VnxB+rdttqduF0C+Lk9U6fo/K3JSgmdRW/tsNhpVG4f5nEaMLwClJU+vFxLEz9RWIuhWnb36Ego= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1660982914; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:To; bh=auj7qQ5/aix+HuhW0IHlBxdSquG9BXFzhbv1T/Lezro=; b=E3Y/vw/9vhU+GHAF9imAixGYYKBaHal469qHMWfr3LSuTDqMWksUWCt+jGU4a+JMWj9C+jX34bznoIWB1UEbHl+6ikF9PdI2lZ3MMyB1A9LIaKm2d5l60bdIIUqNJPIMzA6nnrlHxqwtMMfbwdfJvSnIy0XF2l+xWG6VtZnn+fI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=arinc9.com; spf=pass smtp.mailfrom=arinc.unal@arinc9.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1660982914; s=zmail; d=arinc9.com; i=arinc.unal@arinc9.com; h=From:From:To:To:Cc:Cc:Subject:Subject:Date:Date:Message-Id:Message-Id:In-Reply-To:References:MIME-Version:Content-Type:Content-Transfer-Encoding:Reply-To; bh=auj7qQ5/aix+HuhW0IHlBxdSquG9BXFzhbv1T/Lezro=; b=KUB3gvE9Y6QAnlhorBrrGMVtEvE+TYNfKA1DBlAgBZbN1umqwcQUmRM+K5Z9mEQB eLCpm6HKQaIcla+iOmmn0teKjOKQt4oHncCycW3STkbRWWbIHEA52+bG09x8lgWvxEC uiKUMECuZinvSPo7CoGofUeK0huJMm4ZII6yrfGo= Received: from arinc9-PC.lan (85.117.236.245 [85.117.236.245]) by mx.zohomail.com with SMTPS id 166098291317911.246125532335668; Sat, 20 Aug 2022 01:08:33 -0700 (PDT) From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Sean Wang , Landen Chao , DENG Qingfang , Frank Wunderlich , Luiz Angelo Daros de Luca , Sander Vanheule , =?UTF-8?q?Ren=C3=A9=20van=20Dorst?= , Daniel Golle , erkin.bozoglu@xeront.com, Sergio Paracuellos Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= Subject: [PATCH v4 4/6] dt-bindings: net: dsa: mediatek,mt7530: define port binding per switch Date: Sat, 20 Aug 2022 11:07:56 +0300 Message-Id: <20220820080758.9829-5-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220820080758.9829-1-arinc.unal@arinc9.com> References: <20220820080758.9829-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMailClient: External Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Define DSA port binding per switch model as each switch model requires different values for certain properties. Define reg property on $defs as it's the same for all switch models. Remove unnecessary lines as they are already included from the referred dsa.yaml. Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL --- .../bindings/net/dsa/mediatek,mt7530.yaml | 56 +++++++++++-------- 1 file changed, 34 insertions(+), 22 deletions(-) diff --git a/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml= b/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml index 657e162a1c01..7c4374e16f96 100644 --- a/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml +++ b/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml @@ -130,38 +130,47 @@ properties: ethsys. maxItems: 1 =20 -patternProperties: - "^(ethernet-)?ports$": - type: object - - patternProperties: - "^(ethernet-)?port@[0-9]+$": - type: object - description: Ethernet switch ports - - unevaluatedProperties: false +required: + - compatible + - reg =20 - properties: - reg: - description: - Port address described must be 5 or 6 for CPU port and from 0 - to 5 for user ports. +$defs: + dsa-port-reg: + properties: + reg: + description: + Port address described must be 5 or 6 for CPU port and from + 0 to 5 for user ports. =20 - allOf: - - $ref: dsa-port.yaml# - - if: + mt7530-dsa-port: + patternProperties: + "^(ethernet-)?ports$": + patternProperties: + "^(ethernet-)?port@[0-9]+$": + $ref: "#/$defs/dsa-port-reg" + if: properties: label: items: - const: cpu then: required: - - reg - phy-mode =20 -required: - - compatible - - reg + mt7531-dsa-port: + patternProperties: + "^(ethernet-)?ports$": + patternProperties: + "^(ethernet-)?port@[0-9]+$": + $ref: "#/$defs/dsa-port-reg" + if: + properties: + label: + items: + - const: cpu + then: + required: + - phy-mode =20 allOf: - $ref: dsa.yaml# @@ -185,6 +194,7 @@ allOf: items: - const: mediatek,mt7530 then: + $ref: "#/$defs/mt7530-dsa-port" required: - core-supply - io-supply @@ -195,6 +205,7 @@ allOf: items: - const: mediatek,mt7531 then: + $ref: "#/$defs/mt7531-dsa-port" properties: mediatek,mcm: false =20 @@ -204,6 +215,7 @@ allOf: items: - const: mediatek,mt7621 then: + $ref: "#/$defs/mt7530-dsa-port" required: - mediatek,mcm =20 --=20 2.34.1 From nobody Sat Sep 21 17:33:56 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A0F17C25B08 for ; Sat, 20 Aug 2022 08:09:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343918AbiHTIJW (ORCPT ); Sat, 20 Aug 2022 04:09:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37686 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343731AbiHTIJL (ORCPT ); Sat, 20 Aug 2022 04:09:11 -0400 Received: from sender4-op-o14.zoho.com (sender4-op-o14.zoho.com [136.143.188.14]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 597C845044; Sat, 20 Aug 2022 01:09:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1660982920; cv=none; d=zohomail.com; s=zohoarc; b=EhvwNYOEg474UV2LgtdxYXDxjL9EMMV5Xk2fSRhCi6ChNrZ+UWIwZ8L84uTOCTnQ7zQXFgi/3JRQaBqJvY6BKAQIR3reBkGePZ2B2GW8lv9wsohq9VrZWTLuowUOYgULnkEENVkuKwxj+9eXxanFmcMOdnKrBAsaHkdpTJU9Kug= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1660982920; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:To; bh=6aqR9O1ypsm2Ib82yZoFMp4k7R74DV794Aen1osXdYY=; b=kTKXPN8qyfHzGOVje9qmJE+J1p5D7WMNDmqx0seACv/wvQJpRhR6YYMGeIEIbo7d1r82VzYwBYZwXuW+QCHqhfVG4TKcZ6STTFuht7Tsq4mAKaao/Fur+PLCFZr14CNPLgpPNqUhKpawtEgvhDI9IRVpSwSN5dHF1YE+tSauLS0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=arinc9.com; spf=pass smtp.mailfrom=arinc.unal@arinc9.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1660982920; s=zmail; d=arinc9.com; i=arinc.unal@arinc9.com; h=From:From:To:To:Cc:Cc:Subject:Subject:Date:Date:Message-Id:Message-Id:In-Reply-To:References:MIME-Version:Content-Type:Content-Transfer-Encoding:Reply-To; bh=6aqR9O1ypsm2Ib82yZoFMp4k7R74DV794Aen1osXdYY=; b=HK0MA+5Rl/kZGQ0l/Uy0/37/dHcq+DzUPerke/284vfWGbPzUf9tb9hrD9s8Op7a pC0BkGWjHMsXIWIrWZtpaNW7W/y1LNDb2191ZJIqwbRpHJUZ0ntvw98ebLgaeRZLsfB 89q1zdur9xHiBh6rG2F3pYdRktRUFl/pQgKpsLks= Received: from arinc9-PC.lan (85.117.236.245 [85.117.236.245]) by mx.zohomail.com with SMTPS id 1660982919579888.5977647355193; Sat, 20 Aug 2022 01:08:39 -0700 (PDT) From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Sean Wang , Landen Chao , DENG Qingfang , Frank Wunderlich , Luiz Angelo Daros de Luca , Sander Vanheule , =?UTF-8?q?Ren=C3=A9=20van=20Dorst?= , Daniel Golle , erkin.bozoglu@xeront.com, Sergio Paracuellos Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= Subject: [PATCH v4 5/6] dt-bindings: net: dsa: mediatek,mt7530: define phy-mode for switch models Date: Sat, 20 Aug 2022 11:07:57 +0300 Message-Id: <20220820080758.9829-6-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220820080758.9829-1-arinc.unal@arinc9.com> References: <20220820080758.9829-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMailClient: External Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Define acceptable phy-mode values for the CPU port of mt7530 and mt7531 switches. Remove relevant information from the description of the binding. Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL --- .../bindings/net/dsa/mediatek,mt7530.yaml | 61 +++++++++++++++---- 1 file changed, 50 insertions(+), 11 deletions(-) diff --git a/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml= b/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml index 7c4374e16f96..eff2f0c6182e 100644 --- a/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml +++ b/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml @@ -49,17 +49,6 @@ description: | * mt7621: phy-mode =3D "rgmii-txid"; * mt7623: phy-mode =3D "rgmii"; =20 - CPU-Ports need a phy-mode property: - Allowed values on mt7530 and mt7621: - - "rgmii" - - "trgmii" - On mt7531: - - "1000base-x" - - "2500base-x" - - "rgmii" - - "sgmii" - - properties: compatible: oneOf: @@ -154,6 +143,30 @@ $defs: items: - const: cpu then: + if: + properties: + reg: + const: 5 + then: + properties: + phy-mode: + enum: + - gmii + - mii + - rgmii + else: + properties: + phy-mode: + enum: + - rgmii + - trgmii + + properties: + reg: + enum: + - 5 + - 6 + required: - phy-mode =20 @@ -169,6 +182,32 @@ $defs: items: - const: cpu then: + if: + properties: + reg: + const: 5 + then: + properties: + phy-mode: + enum: + - 1000base-x + - 2500base-x + - rgmii + - sgmii + else: + properties: + phy-mode: + enum: + - 1000base-x + - 2500base-x + - sgmii + + properties: + reg: + enum: + - 5 + - 6 + required: - phy-mode =20 --=20 2.34.1 From nobody Sat Sep 21 17:33:56 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DE1ECC25B08 for ; Sat, 20 Aug 2022 08:09:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344166AbiHTIJf (ORCPT ); Sat, 20 Aug 2022 04:09:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38302 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343870AbiHTIJU (ORCPT ); Sat, 20 Aug 2022 04:09:20 -0400 Received: from sender4-op-o14.zoho.com (sender4-op-o14.zoho.com [136.143.188.14]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E656B5A3CA; Sat, 20 Aug 2022 01:09:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1660982929; cv=none; d=zohomail.com; s=zohoarc; b=MEcu3imQh3NYN0O4gumjRRnRT4LWeOT1Am2Ug99PiPY1eKfFr/pSRv9q2q9e1zDva8TEnyuzXfHfDK5F0+dMDSaHqFAEoFQGFgvgHur1JYokxvD73qneEPXum9Pc2Q26QBCXufr2BvFrXjxxXGGBESaaH284hjJEn86/pJHfRMY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1660982929; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:To; bh=efZyIMqhvsHv7kWVzGyHqdrHhC0Tjwb1XVhmNHq+bJ4=; b=HZL9Z4LyI63yBisuO4pnl1BRIXGEZJ/8uFPmx8oee75OdV90wDPXaoRy5WO302xjrcaTeavoir8mZYgEGLk0SEaUNQ2W5HoY5kbPf51Z7MJ/3XzBf9WiJCYQvYeF5hPQipmVhMCqli6BkZ5BRC61D+JeQ+KBvjXq+a3hiEQE/bk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=arinc9.com; spf=pass smtp.mailfrom=arinc.unal@arinc9.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1660982929; s=zmail; d=arinc9.com; i=arinc.unal@arinc9.com; h=From:From:To:To:Cc:Cc:Subject:Subject:Date:Date:Message-Id:Message-Id:In-Reply-To:References:MIME-Version:Content-Type:Content-Transfer-Encoding:Reply-To; bh=efZyIMqhvsHv7kWVzGyHqdrHhC0Tjwb1XVhmNHq+bJ4=; b=WVlJw/eAD3Gc7p40X3WujYKXEtCd6IuCCWxb4ouHMeFmSsHL1x1qmDFgQx8+qq79 RkdR2PYIcsyLN9N2OHjIsU1P0gm/Q3lL4u/OvysYENynbcyq5g2uLP2vnaZSAIziPoX y2uFbldAQJT6GimGiT0FMBrpLCMlvQ9cDNmuSvXk= Received: from arinc9-PC.lan (85.117.236.245 [85.117.236.245]) by mx.zohomail.com with SMTPS id 1660982926255105.11458904953486; Sat, 20 Aug 2022 01:08:46 -0700 (PDT) From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Sean Wang , Landen Chao , DENG Qingfang , Frank Wunderlich , Luiz Angelo Daros de Luca , Sander Vanheule , =?UTF-8?q?Ren=C3=A9=20van=20Dorst?= , Daniel Golle , erkin.bozoglu@xeront.com, Sergio Paracuellos Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= Subject: [PATCH v4 6/6] dt-bindings: net: dsa: mediatek,mt7530: update binding description Date: Sat, 20 Aug 2022 11:07:58 +0300 Message-Id: <20220820080758.9829-7-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220820080758.9829-1-arinc.unal@arinc9.com> References: <20220820080758.9829-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMailClient: External Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Update the description of the binding. - Describe the switches, which SoCs they are in, or if they are standalone. - Explain the various ways of configuring MT7530's port 5. - Remove phy-mode =3D "rgmii-txid" from description. Same code path is followed for delayed rgmii and rgmii phy-mode on mtk_eth_soc.c. Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL Acked-by: Krzysztof Kozlowski --- .../bindings/net/dsa/mediatek,mt7530.yaml | 97 ++++++++++++------- 1 file changed, 62 insertions(+), 35 deletions(-) diff --git a/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml= b/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml index eff2f0c6182e..80ec05fd81f6 100644 --- a/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml +++ b/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml @@ -13,41 +13,68 @@ maintainers: - Sean Wang =20 description: | - Port 5 of mt7530 and mt7621 switch is muxed between: - 1. GMAC5: GMAC5 can interface with another external MAC or PHY. - 2. PHY of port 0 or port 4: PHY interfaces with an external MAC like 2nd= GMAC - of the SOC. Used in many setups where port 0/4 becomes the WAN port. - Note: On a MT7621 SOC with integrated switch: 2nd GMAC can only conne= cted to - GMAC5 when the gpios for RGMII2 (GPIO 22-33) are not used and not - connected to external component! - - Port 5 modes/configurations: - 1. Port 5 is disabled and isolated: An external phy can interface to the= 2nd - GMAC of the SOC. - In the case of a build-in MT7530 switch, port 5 shares the RGMII bus = with 2nd - GMAC and an optional external phy. Mind the GPIO/pinctl settings of t= he SOC! - 2. Port 5 is muxed to PHY of port 0/4: Port 0/4 interfaces with 2nd GMAC. - It is a simple MAC to PHY interface, port 5 needs to be setup for xMI= I mode - and RGMII delay. - 3. Port 5 is muxed to GMAC5 and can interface to an external phy. - Port 5 becomes an extra switch port. - Only works on platform where external phy TX<->RX lines are swapped. - Like in the Ubiquiti ER-X-SFP. - 4. Port 5 is muxed to GMAC5 and interfaces with the 2nd GAMC as 2nd CPU = port. - Currently a 2nd CPU port is not supported by DSA code. - - Depending on how the external PHY is wired: - 1. normal: The PHY can only connect to 2nd GMAC but not to the switch - 2. swapped: RGMII TX, RX are swapped; external phy interface with the sw= itch as - a ethernet port. But can't interface to the 2nd GMAC. - - Based on the DT the port 5 mode is configured. - - Driver tries to lookup the phy-handle of the 2nd GMAC of the master devi= ce. - When phy-handle matches PHY of port 0 or 4 then port 5 set-up as mode 2. - phy-mode must be set, see also example 2 below! - * mt7621: phy-mode =3D "rgmii-txid"; - * mt7623: phy-mode =3D "rgmii"; + There are two versions of MT7530, standalone and in a multi-chip module. + + MT7530 is a part of the multi-chip module in MT7620AN, MT7620DA, MT7620D= AN, + MT7620NN, MT7621AT, MT7621DAT, MT7621ST and MT7623AI SoCs. + + MT7530 in MT7620AN, MT7620DA, MT7620DAN and MT7620NN SoCs has got 10/100= PHYs + and the switch registers are directly mapped into SoC's memory map rathe= r than + using MDIO. The DSA driver currently doesn't support this. + + There is only the standalone version of MT7531. + + Port 5 on MT7530 has got various ways of configuration. + + For standalone MT7530: + + - Port 5 can be used as a CPU port. + + - PHY 0 or 4 of the switch can be muxed to connect to the gmac of the = SoC + which port 5 is wired to. Usually used for connecting the wan port + directly to the CPU to achieve 2 Gbps routing in total. + + The driver looks up the reg on the ethernet-phy node which the phy-h= andle + property refers to on the gmac node to mux the specified phy. + + The driver requires the gmac of the SoC to have "mediatek,eth-mac" a= s the + compatible string and the reg must be 1. So, for now, only gmac1 of = an + MediaTek SoC can benefit this. Banana Pi BPI-R2 suits this. + Check out example 5 for a similar configuration. + + - Port 5 can be wired to an external phy. Port 5 becomes a DSA slave. + Check out example 7 for a similar configuration. + + For multi-chip module MT7530: + + - Port 5 can be used as a CPU port. + + - PHY 0 or 4 of the switch can be muxed to connect to gmac1 of the SoC. + Usually used for connecting the wan port directly to the CPU to achi= eve 2 + Gbps routing in total. + + The driver looks up the reg on the ethernet-phy node which the phy-h= andle + property refers to on the gmac node to mux the specified phy. + + For the MT7621 SoCs, rgmii2 group must be claimed with rgmii2 functi= on. + Check out example 5. + + - In case of an external phy wired to gmac1 of the SoC, port 5 must no= t be + enabled. + + In case of muxing PHY 0 or 4, the external phy must not be enabled. + + For the MT7621 SoCs, rgmii2 group must be claimed with rgmii2 functi= on. + Check out example 6. + + - Port 5 can be muxed to an external phy. Port 5 becomes a DSA slave. + The external phy must be wired TX to TX to gmac1 of the SoC for this= to + work. Ubiquiti EdgeRouter X SFP is wired this way. + + Muxing PHY 0 or 4 won't work when the external phy is connected TX t= o TX. + + For the MT7621 SoCs, rgmii2 group must be claimed with gpio function. + Check out example 7. =20 properties: compatible: --=20 2.34.1