From nobody Fri Apr 10 18:34:52 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8DCBFC25B08 for ; Sat, 20 Aug 2022 06:55:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229458AbiHTGz5 (ORCPT ); Sat, 20 Aug 2022 02:55:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33932 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243781AbiHTGzv (ORCPT ); Sat, 20 Aug 2022 02:55:51 -0400 Received: from mail-oi1-x236.google.com (mail-oi1-x236.google.com [IPv6:2607:f8b0:4864:20::236]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A9A99C04E7 for ; Fri, 19 Aug 2022 23:55:50 -0700 (PDT) Received: by mail-oi1-x236.google.com with SMTP id p128so6969753oif.9 for ; Fri, 19 Aug 2022 23:55:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=tQCr/IgKCdRHY8LSP1T2xhus9TIrH4sruSlDTlO3guE=; b=ei8+a9amYDoCpz1QI5IeR7TYam6l5ohxbZI/T1kt/X1fsxq0YHMoqW0v47Oz3RAAAg xqTBjui/X0e6KsM/aQoYTgFSvGmF99FFNS9LZ9IUUFXqS+2SsqVFFtlcCCus00feE1zn 177JILJY5e9+mryKtBTtj6NEu3ew9G6pHpLNrGFtD75A/u7hyrlSrR2XB5HFYvS0WYpY rBvo9BaAWW58MQee7u1gevoo7SGHaBNpW9Z9OEUMw7wNbhzZ6vNcgkxJLop7lKC9ir4j 91RjGjhY5ljxNPiJmQ7gCbcwEM4b0f+BBaOto7yzD/0WEU/f23NVdizyHYhVKRoQONRo X0yw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=tQCr/IgKCdRHY8LSP1T2xhus9TIrH4sruSlDTlO3guE=; b=57/iP6Q8FcEHMtgmNQt+ZzGvyrwbPpbQyWXgEPgFrEoCIt8uR7Xfdu8mTNrPZSIx0Z XLkXrzT1oH7fnQfuF+LndOTEw86lW0LIAH7vLmfej58v/fyOp5qtew+CmmHXdqJVlu08 8rMiuws+MasMY91SrHSmTsECZnDSys6cHD2Hk3QC/KaN61dzSmBbHJkRKRQrIMhnGODM jc4AnfgtAQviesagp6HqYwS6sWDkAmYw/ci48Pwqx1xvYkg26hK63ompzOPIM/oN7zTQ un6mRmVqb6WOakYEFVZ3moLwWa4L5V/XJ3WzmBQhxz+oVeKDC9XWpMHWT68NGSnNAFDn jaDQ== X-Gm-Message-State: ACgBeo0OOX+d8trbNoavJZ6auNxS5f5vOzxGqJaemtJNdtVDRNprMWjw 3MrvotWQ3R1JBfkkdpYcwnymKg== X-Google-Smtp-Source: AA6agR5Oo0DXXb5svYgvBBGq7lg7ZNVbU0D0Ks8xh5M92bnwe0csVlpM4h+ggVcAl9pbcv+gygl2kA== X-Received: by 2002:a05:6808:19a4:b0:343:300c:a1b2 with SMTP id bj36-20020a05680819a400b00343300ca1b2mr5420429oib.253.1660978549973; Fri, 19 Aug 2022 23:55:49 -0700 (PDT) Received: from anup-ubuntu64-vm.. ([171.76.82.68]) by smtp.gmail.com with ESMTPSA id h26-20020a9d641a000000b00636faf5e2d9sm1661098otl.39.2022.08.19.23.55.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Aug 2022 23:55:49 -0700 (PDT) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Marc Zyngier , Daniel Lezcano Cc: Atish Patra , Alistair Francis , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel , Bin Meng Subject: [PATCH v8 1/7] RISC-V: Clear SIP bit only when using SBI IPI operations Date: Sat, 20 Aug 2022 12:24:40 +0530 Message-Id: <20220820065446.389788-2-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220820065446.389788-1-apatel@ventanamicro.com> References: <20220820065446.389788-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The software interrupt pending (i.e. [M|S]SIP) bit is writeable for S-mode but read-only for M-mode so we clear this bit only when using SBI IPI operations. Signed-off-by: Anup Patel Reviewed-by: Bin Meng --- arch/riscv/kernel/sbi.c | 8 +++++++- arch/riscv/kernel/smp.c | 2 -- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c index 775d3322b422..fc614650a2e3 100644 --- a/arch/riscv/kernel/sbi.c +++ b/arch/riscv/kernel/sbi.c @@ -643,8 +643,14 @@ static void sbi_send_cpumask_ipi(const struct cpumask = *target) sbi_send_ipi(target); } =20 +static void sbi_ipi_clear(void) +{ + csr_clear(CSR_IP, IE_SIE); +} + static const struct riscv_ipi_ops sbi_ipi_ops =3D { - .ipi_inject =3D sbi_send_cpumask_ipi + .ipi_inject =3D sbi_send_cpumask_ipi, + .ipi_clear =3D sbi_ipi_clear }; =20 void __init sbi_init(void) diff --git a/arch/riscv/kernel/smp.c b/arch/riscv/kernel/smp.c index 760a64518c58..c56d67f53ea9 100644 --- a/arch/riscv/kernel/smp.c +++ b/arch/riscv/kernel/smp.c @@ -83,8 +83,6 @@ void riscv_clear_ipi(void) { if (ipi_ops && ipi_ops->ipi_clear) ipi_ops->ipi_clear(); - - csr_clear(CSR_IP, IE_SIE); } EXPORT_SYMBOL_GPL(riscv_clear_ipi); =20 --=20 2.34.1 From nobody Fri Apr 10 18:34:52 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6BF89C25B08 for ; Sat, 20 Aug 2022 06:56:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244618AbiHTG4B (ORCPT ); Sat, 20 Aug 2022 02:56:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33938 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244366AbiHTGz4 (ORCPT ); Sat, 20 Aug 2022 02:55:56 -0400 Received: from mail-oi1-x22f.google.com (mail-oi1-x22f.google.com [IPv6:2607:f8b0:4864:20::22f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B1ED2C04E7 for ; Fri, 19 Aug 2022 23:55:55 -0700 (PDT) Received: by mail-oi1-x22f.google.com with SMTP id v125so7017561oie.0 for ; Fri, 19 Aug 2022 23:55:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=7gL51KGK8h2gYdKsAsi/esrqwK4Ga0hyaEGMAaUXEgw=; b=Sw04uJ3vbDVepAg/gWVJcWOV7MbzEmF8dKmsd/rb6F8inqTs1ofPx1MK09cu3sGCTc 0VvQSYC0ZBw+zM+SXSv1L1UObgmZzvYVFbPwoMaYQ42uWio23+ffNmsmi+dimTW8E6u5 8O4T4xGCd206w7/uqNwH9F5bwTQY2wNgBLDZZd9u9xxYKp7pElOD0PXM7AiAvTkAQccV HsMXix2vDP8/m0hM8ddQW0m0vEPms6xLU6j7mPJ0UsUkauth3dyKJ/fDctjj3G+QGcYv lgVblX5ZvzjUpFnGtjWBem/SXRb3s3wrn6p45TOr5X2AUVAdCLOYvqPSYxkWvbZjdx7f b5Gg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=7gL51KGK8h2gYdKsAsi/esrqwK4Ga0hyaEGMAaUXEgw=; b=RkxoBQ1cyKhIe0QwpDDDX1H4/uonRvjBv1A2TmVbVBhaZBAEt/L1Xeew41ajoq1I4Q WPLWECzmBAUHUc5zRa3h3P46jRTVZMAIrYq6zoqk5+CanY363YtNCTrmqyHPpPbMYxrC WQEAgcloLklCrDtF2Wl/ACqsmwg1KZQmUjWCau2FQg+nFRmsjGKzA1/EdwNyf6+g23Qx IU/zkDZUmb8KXl+DxlBb1v5439JEKTy51y09QK49i7+INCjVViwPZg593Qgc1CaheWVF wbVDC6n4OEtTlgoonI3FglKlCL+d4dARKCaLUH39qQFew0C0QkjAgJBZ6/Yprmf9GflD bazw== X-Gm-Message-State: ACgBeo2k6pEaQzHQgrYW1tbFydk+N3RqqISLF3sAscYc4rb93fU5Gv3b K/uEnm0U4JFv6XRqAPmHE4geOA== X-Google-Smtp-Source: AA6agR5utbHM4pipxClH5gyEYq4cq0Nm0cG2E0loDJemIx24wNgpN5lXHXqEGa8/FgPkVBgRhwGxRA== X-Received: by 2002:aca:5e8b:0:b0:344:d1ef:2293 with SMTP id s133-20020aca5e8b000000b00344d1ef2293mr7608063oib.158.1660978554932; Fri, 19 Aug 2022 23:55:54 -0700 (PDT) Received: from anup-ubuntu64-vm.. ([171.76.82.68]) by smtp.gmail.com with ESMTPSA id h26-20020a9d641a000000b00636faf5e2d9sm1661098otl.39.2022.08.19.23.55.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Aug 2022 23:55:54 -0700 (PDT) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Marc Zyngier , Daniel Lezcano Cc: Atish Patra , Alistair Francis , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH v8 2/7] irqchip/riscv-intc: Allow drivers to directly discover INTC hwnode Date: Sat, 20 Aug 2022 12:24:41 +0530 Message-Id: <20220820065446.389788-3-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220820065446.389788-1-apatel@ventanamicro.com> References: <20220820065446.389788-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Various RISC-V drivers (such as SBI IPI, SBI Timer, SBI PMU, and KVM RISC-V) don't have associated DT node but these drivers need standard per-CPU (local) interrupts defined by the RISC-V privileged specification. We add riscv_get_intc_hwnode() in arch/riscv which allows RISC-V drivers not having DT node to discover INTC hwnode which in-turn helps these drivers to map per-CPU (local) interrupts provided by the INTC driver. Signed-off-by: Anup Patel --- arch/riscv/include/asm/irq.h | 4 ++++ arch/riscv/kernel/irq.c | 18 ++++++++++++++++++ drivers/irqchip/irq-riscv-intc.c | 7 +++++++ 3 files changed, 29 insertions(+) diff --git a/arch/riscv/include/asm/irq.h b/arch/riscv/include/asm/irq.h index e4c435509983..43b9ebfbd943 100644 --- a/arch/riscv/include/asm/irq.h +++ b/arch/riscv/include/asm/irq.h @@ -12,6 +12,10 @@ =20 #include =20 +void riscv_set_intc_hwnode_fn(struct fwnode_handle *(*fn)(void)); + +struct fwnode_handle *riscv_get_intc_hwnode(void); + extern void __init init_IRQ(void); =20 #endif /* _ASM_RISCV_IRQ_H */ diff --git a/arch/riscv/kernel/irq.c b/arch/riscv/kernel/irq.c index 7207fa08d78f..96d3171f0ca1 100644 --- a/arch/riscv/kernel/irq.c +++ b/arch/riscv/kernel/irq.c @@ -7,9 +7,27 @@ =20 #include #include +#include +#include #include #include =20 +static struct fwnode_handle *(*__get_intc_node)(void); + +void riscv_set_intc_hwnode_fn(struct fwnode_handle *(*fn)(void)) +{ + __get_intc_node =3D fn; +} + +struct fwnode_handle *riscv_get_intc_hwnode(void) +{ + if (__get_intc_node) + return __get_intc_node(); + + return NULL; +} +EXPORT_SYMBOL_GPL(riscv_get_intc_hwnode); + int arch_show_interrupts(struct seq_file *p, int prec) { show_ipi_stats(p, prec); diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-i= ntc.c index 499e5f81b3fe..9066467e99e4 100644 --- a/drivers/irqchip/irq-riscv-intc.c +++ b/drivers/irqchip/irq-riscv-intc.c @@ -92,6 +92,11 @@ static const struct irq_domain_ops riscv_intc_domain_ops= =3D { .xlate =3D irq_domain_xlate_onecell, }; =20 +static struct fwnode_handle *riscv_intc_hwnode(void) +{ + return intc_domain->fwnode; +} + static int __init riscv_intc_init(struct device_node *node, struct device_node *parent) { @@ -126,6 +131,8 @@ static int __init riscv_intc_init(struct device_node *n= ode, return rc; } =20 + riscv_set_intc_hwnode_fn(riscv_intc_hwnode); + cpuhp_setup_state(CPUHP_AP_IRQ_RISCV_STARTING, "irqchip/riscv/intc:starting", riscv_intc_cpu_starting, --=20 2.34.1 From nobody Fri Apr 10 18:34:52 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 75BB3C32774 for ; Sat, 20 Aug 2022 06:56:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245025AbiHTG4F (ORCPT ); Sat, 20 Aug 2022 02:56:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33974 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244609AbiHTG4B (ORCPT ); Sat, 20 Aug 2022 02:56:01 -0400 Received: from mail-oi1-x235.google.com (mail-oi1-x235.google.com [IPv6:2607:f8b0:4864:20::235]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 972A8C04FE for ; Fri, 19 Aug 2022 23:56:00 -0700 (PDT) Received: by mail-oi1-x235.google.com with SMTP id o184so6943795oif.13 for ; Fri, 19 Aug 2022 23:56:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=8JkNs45nL6eP4dRpsaaqSOVaaU3NIoI49DX3nwl5ILw=; b=KVlpMPp3gUv+2d68mR8Oa7EJjZzvOFkG1tW/z2owCSNC4Ckv6mYmA61WzMM7DVsUZG wNKcBRZJ1OvxThgxYlgDRo8oIVvDrWRIFXEOfo8sI6E8L0MDdwP7+68u5ltFnXt0mqV/ P4pJzE+LCuOo4aEx+C1YYMS1T42BSD+HzeQXFWajDxbH9PA6ZSctCgw/9IYGxcSUbnUm Ao+jgONuFPvyxEgWNcFqyTZB8PqbtbEnAkFKoCiyIS3XeqBQUNOxAQICyDtft11d3l3n QP+wqkCWLUtOs1dQfG/+6O2rG2XjkLjwOOK5iYm9bG3CFHB0R0ogk9d3PtkRY6ZOy9wB 5/WQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=8JkNs45nL6eP4dRpsaaqSOVaaU3NIoI49DX3nwl5ILw=; b=PGBZY8y057SgxOpqpj5zLlYPJEBReU10acjrw9lzwD8FNPjKb6uuSAdNRKQpxYtsno DuHNam5R9jQMIkqhvavVcPSQOzSRFdN3qtLG/cqhOOiB4YGpEW4NFPXx+0ZBVX0uG+sI tLTDpJ2ZvWuAgD9uV3bpAWPYi03D8eCGApuAIRt/o+EwntKbMKB4ZAob/ysCJ5U4CucS mjQorCpQZT6gVNCwat57ULDzpcBQFQutDxdnfdZ/Pz7Vr9CmLZaI8Hd5Kiacyb5V692w UyV1WXAmtSjKGitSTVQdNSKJx3HfuOt8m8A00s4KnJnUYMb5qj6nhpWW6EVvCY1rsU9E 7XJg== X-Gm-Message-State: ACgBeo1c2Mt98r719S0eeW4cOHxLaIPnjVAJlSUD0620LJgT93bn/V2X bBMCQR39BPFc/UGT1JXRz0xMaw== X-Google-Smtp-Source: AA6agR5OMEjMecGksCW8gybtKZsQlV+Jeq2y2o7to0D63swEp5N9vaWTea/99NifK8dMWfcQgGhq+g== X-Received: by 2002:a05:6808:f8e:b0:342:ff09:2c3d with SMTP id o14-20020a0568080f8e00b00342ff092c3dmr5094120oiw.177.1660978559805; Fri, 19 Aug 2022 23:55:59 -0700 (PDT) Received: from anup-ubuntu64-vm.. ([171.76.82.68]) by smtp.gmail.com with ESMTPSA id h26-20020a9d641a000000b00636faf5e2d9sm1661098otl.39.2022.08.19.23.55.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Aug 2022 23:55:59 -0700 (PDT) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Marc Zyngier , Daniel Lezcano Cc: Atish Patra , Alistair Francis , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH v8 3/7] genirq: Add mechanism to multiplex a single HW IPI Date: Sat, 20 Aug 2022 12:24:42 +0530 Message-Id: <20220820065446.389788-4-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220820065446.389788-1-apatel@ventanamicro.com> References: <20220820065446.389788-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" All RISC-V platforms have a single HW IPI provided by the INTC local interrupt controller. The HW method to trigger INTC IPI can be through external irqchip (e.g. RISC-V AIA), through platform specific device (e.g. SiFive CLINT timer), or through firmware (e.g. SBI IPI call). To support multiple IPIs on RISC-V, we add a generic IPI multiplexing mechanism which help us create multiple virtual IPIs using a single HW IPI. This generic IPI multiplexing is shared among various RISC-V irqchip drivers. Signed-off-by: Anup Patel --- include/linux/irq.h | 18 ++++ kernel/irq/Kconfig | 5 + kernel/irq/Makefile | 1 + kernel/irq/ipi-mux.c | 244 +++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 268 insertions(+) create mode 100644 kernel/irq/ipi-mux.c diff --git a/include/linux/irq.h b/include/linux/irq.h index c3eb89606c2b..5ab702cb0a5b 100644 --- a/include/linux/irq.h +++ b/include/linux/irq.h @@ -1266,6 +1266,24 @@ int __ipi_send_mask(struct irq_desc *desc, const str= uct cpumask *dest); int ipi_send_single(unsigned int virq, unsigned int cpu); int ipi_send_mask(unsigned int virq, const struct cpumask *dest); =20 +/** + * struct ipi_mux_ops - IPI multiplex operations + * + * @ipi_mux_pre_handle: Optional function called before handling parent IPI + * @ipi_mux_post_handle:Optional function called after handling parent IPI + * @ipi_mux_send: Trigger parent IPI on target CPUs + */ +struct ipi_mux_ops { + void (*ipi_mux_pre_handle)(unsigned int parent_virq, void *data); + void (*ipi_mux_post_handle)(unsigned int parent_virq, void *data); + void (*ipi_mux_send)(unsigned int parent_virq, void *data, + const struct cpumask *mask); +}; + +void ipi_mux_process(void); +int ipi_mux_create(unsigned int parent_virq, unsigned int nr_ipi, + const struct ipi_mux_ops *ops, void *data); + #ifdef CONFIG_GENERIC_IRQ_MULTI_HANDLER /* * Registers a generic IRQ handling function as the top-level IRQ handler = in diff --git a/kernel/irq/Kconfig b/kernel/irq/Kconfig index db3d174c53d4..df17dbc54b02 100644 --- a/kernel/irq/Kconfig +++ b/kernel/irq/Kconfig @@ -86,6 +86,11 @@ config GENERIC_IRQ_IPI depends on SMP select IRQ_DOMAIN_HIERARCHY =20 +# Generic IRQ IPI Mux support +config GENERIC_IRQ_IPI_MUX + bool + depends on SMP + # Generic MSI interrupt support config GENERIC_MSI_IRQ bool diff --git a/kernel/irq/Makefile b/kernel/irq/Makefile index b4f53717d143..f19d3080bf11 100644 --- a/kernel/irq/Makefile +++ b/kernel/irq/Makefile @@ -15,6 +15,7 @@ obj-$(CONFIG_GENERIC_IRQ_MIGRATION) +=3D cpuhotplug.o obj-$(CONFIG_PM_SLEEP) +=3D pm.o obj-$(CONFIG_GENERIC_MSI_IRQ) +=3D msi.o obj-$(CONFIG_GENERIC_IRQ_IPI) +=3D ipi.o +obj-$(CONFIG_GENERIC_IRQ_IPI_MUX) +=3D ipi-mux.o obj-$(CONFIG_SMP) +=3D affinity.o obj-$(CONFIG_GENERIC_IRQ_DEBUGFS) +=3D debugfs.o obj-$(CONFIG_GENERIC_IRQ_MATRIX_ALLOCATOR) +=3D matrix.o diff --git a/kernel/irq/ipi-mux.c b/kernel/irq/ipi-mux.c new file mode 100644 index 000000000000..8939fa2be73c --- /dev/null +++ b/kernel/irq/ipi-mux.c @@ -0,0 +1,244 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Multiplex several virtual IPIs over a single HW IPI. + * + * Copyright (c) 2022 Ventana Micro Systems Inc. + */ + +#define pr_fmt(fmt) "ipi-mux: " fmt +#include +#include +#include +#include +#include +#include +#include + +static void *ipi_mux_data; +static unsigned int ipi_mux_nr; +static unsigned int ipi_mux_parent_virq; +static struct irq_domain *ipi_mux_domain; +static const struct ipi_mux_ops *ipi_mux_ops; +static DEFINE_PER_CPU(atomic_t, ipi_mux_enable); +static DEFINE_PER_CPU(atomic_t, ipi_mux_bits); + +static void ipi_mux_mask(struct irq_data *d) +{ + atomic_andnot(BIT(irqd_to_hwirq(d)), this_cpu_ptr(&ipi_mux_enable)); +} + +static void ipi_mux_unmask(struct irq_data *d) +{ + u32 ipi_bit =3D BIT(irqd_to_hwirq(d)); + + atomic_or(ipi_bit, this_cpu_ptr(&ipi_mux_enable)); + + /* + * The atomic_or() above must complete before the atomic_read() + * below to avoid racing ipi_mux_send_mask(). + */ + smp_mb__after_atomic(); + + /* If a pending IPI was unmasked, raise a parent IPI immediately. */ + if (atomic_read(this_cpu_ptr(&ipi_mux_bits)) & ipi_bit) + ipi_mux_ops->ipi_mux_send(ipi_mux_parent_virq, ipi_mux_data, + cpumask_of(smp_processor_id())); +} + +static void ipi_mux_send_mask(struct irq_data *d, const struct cpumask *ma= sk) +{ + u32 ipi_bit =3D BIT(irqd_to_hwirq(d)); + struct cpumask pmask =3D { 0 }; + unsigned long pending; + int cpu; + + for_each_cpu(cpu, mask) { + pending =3D atomic_fetch_or_release(ipi_bit, + per_cpu_ptr(&ipi_mux_bits, cpu)); + + /* + * The atomic_fetch_or_release() above must complete before + * the atomic_read() below to avoid racing ipi_mux_unmask(). + */ + smp_mb__after_atomic(); + + if (!(pending & ipi_bit) && + (atomic_read(per_cpu_ptr(&ipi_mux_enable, cpu)) & ipi_bit)) + cpumask_set_cpu(cpu, &pmask); + } + + /* Trigger the parent IPI */ + ipi_mux_ops->ipi_mux_send(ipi_mux_parent_virq, ipi_mux_data, &pmask); +} + +static const struct irq_chip ipi_mux_chip =3D { + .name =3D "IPI Mux", + .irq_mask =3D ipi_mux_mask, + .irq_unmask =3D ipi_mux_unmask, + .ipi_send_mask =3D ipi_mux_send_mask, +}; + +static int ipi_mux_domain_alloc(struct irq_domain *d, unsigned int virq, + unsigned int nr_irqs, void *arg) +{ + struct irq_fwspec *fwspec =3D arg; + irq_hw_number_t hwirq; + unsigned int type; + int i, ret; + + ret =3D irq_domain_translate_onecell(d, fwspec, &hwirq, &type); + if (ret) + return ret; + + for (i =3D 0; i < nr_irqs; i++) { + irq_set_percpu_devid(virq + i); + irq_domain_set_info(d, virq + i, hwirq + i, + &ipi_mux_chip, d->host_data, + handle_percpu_devid_irq, NULL, NULL); + } + + return 0; +} + +static const struct irq_domain_ops ipi_mux_domain_ops =3D { + .alloc =3D ipi_mux_domain_alloc, + .free =3D irq_domain_free_irqs_top, +}; + +/** + * ipi_mux_process - Process multiplexed virtual IPIs + */ +void ipi_mux_process(void) +{ + irq_hw_number_t hwirq; + unsigned long ipis; + int en, err; + + if (ipi_mux_ops->ipi_mux_pre_handle) + ipi_mux_ops->ipi_mux_pre_handle(ipi_mux_parent_virq, + ipi_mux_data); + + /* + * Reading enable mask does not need to be ordered as long as + * this function called from interrupt handler because only + * the CPU itself can change it's own enable mask. + */ + en =3D atomic_read(this_cpu_ptr(&ipi_mux_enable)); + + /* + * Clear the IPIs we are about to handle. This pairs with the + * atomic_fetch_or_release() in ipi_mux_send_mask(). + */ + ipis =3D atomic_fetch_andnot(en, this_cpu_ptr(&ipi_mux_bits)) & en; + + for_each_set_bit(hwirq, &ipis, ipi_mux_nr) { + err =3D generic_handle_domain_irq(ipi_mux_domain, + hwirq); + if (unlikely(err)) + pr_warn_ratelimited( + "can't find mapping for hwirq %lu\n", + hwirq); + } + + if (ipi_mux_ops->ipi_mux_post_handle) + ipi_mux_ops->ipi_mux_post_handle(ipi_mux_parent_virq, + ipi_mux_data); +} + +static void ipi_mux_handler(struct irq_desc *desc) +{ + struct irq_chip *chip =3D irq_desc_get_chip(desc); + + chained_irq_enter(chip, desc); + ipi_mux_process(); + chained_irq_exit(chip, desc); +} + +static int ipi_mux_dying_cpu(unsigned int cpu) +{ + disable_percpu_irq(ipi_mux_parent_virq); + return 0; +} + +static int ipi_mux_starting_cpu(unsigned int cpu) +{ + enable_percpu_irq(ipi_mux_parent_virq, + irq_get_trigger_type(ipi_mux_parent_virq)); + return 0; +} + +/** + * ipi_mux_create - Create virtual IPIs multiplexed on top of a single + * parent IPI. + * @parent_virq: virq of the parent per-CPU IRQ + * @nr_ipi: number of virtual IPIs to create. This should + * be <=3D BITS_PER_TYPE(int) + * @ops: multiplexing operations for the parent IPI + * @data: opaque data used by the multiplexing operations + * + * If the parent IPI > 0 then ipi_mux_process() will be automatically + * called via chained handler. + * + * If the parent IPI <=3D 0 then it is responsibility of irqchip drivers + * to explicitly call ipi_mux_process() for processing muxed IPIs. + * + * Returns first virq of the newly created virtual IPIs upon success + * or <=3D0 upon failure + */ +int ipi_mux_create(unsigned int parent_virq, unsigned int nr_ipi, + const struct ipi_mux_ops *ops, void *data) +{ + struct fwnode_handle *fwnode; + struct irq_domain *domain; + struct irq_fwspec ipi; + int virq; + + if (ipi_mux_domain || BITS_PER_TYPE(int) < nr_ipi || + !ops || !ops->ipi_mux_send) + return -EINVAL; + + if (parent_virq && + !irqd_is_per_cpu(irq_desc_get_irq_data(irq_to_desc(parent_virq)))) + return -EINVAL; + + fwnode =3D irq_domain_alloc_named_fwnode("IPI-Mux"); + if (!fwnode) { + pr_err("unable to create IPI Mux fwnode\n"); + return -ENOMEM; + } + + domain =3D irq_domain_create_simple(fwnode, nr_ipi, 0, + &ipi_mux_domain_ops, NULL); + if (!domain) { + pr_err("unable to add IPI Mux domain\n"); + irq_domain_free_fwnode(fwnode); + return -ENOMEM; + } + + ipi.fwnode =3D domain->fwnode; + ipi.param_count =3D 1; + ipi.param[0] =3D 0; + virq =3D __irq_domain_alloc_irqs(domain, -1, nr_ipi, + NUMA_NO_NODE, &ipi, false, NULL); + if (virq <=3D 0) { + pr_err("unable to alloc IRQs from IPI Mux domain\n"); + irq_domain_remove(domain); + irq_domain_free_fwnode(fwnode); + return virq; + } + + ipi_mux_domain =3D domain; + ipi_mux_data =3D data; + ipi_mux_nr =3D nr_ipi; + ipi_mux_parent_virq =3D parent_virq; + ipi_mux_ops =3D ops; + + if (parent_virq > 0) { + irq_set_chained_handler(parent_virq, ipi_mux_handler); + cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, + "irqchip/ipi-mux:starting", + ipi_mux_starting_cpu, ipi_mux_dying_cpu); + } + + return virq; +} --=20 2.34.1 From nobody Fri Apr 10 18:34:52 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6924EC32772 for ; Sat, 20 Aug 2022 06:56:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245709AbiHTG4U (ORCPT ); Sat, 20 Aug 2022 02:56:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34022 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244609AbiHTG4H (ORCPT ); Sat, 20 Aug 2022 02:56:07 -0400 Received: from mail-oi1-x234.google.com (mail-oi1-x234.google.com [IPv6:2607:f8b0:4864:20::234]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8E792C0B4D for ; Fri, 19 Aug 2022 23:56:05 -0700 (PDT) Received: by mail-oi1-x234.google.com with SMTP id c185so6962208oia.7 for ; Fri, 19 Aug 2022 23:56:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=R2qzmF1tqlb5sXVnVAPi3895l0EF4P+hvfQ4PCi4vTY=; b=KXFcGSYdUb2+Jb5+gvAg7DtAUyEeMCwLEwG1XvFpayCa7ESP3y0pkMoynihE/G/1ii SaeYlx0a21BdAo7cAQ29C38utx20GDvZJ1t2b6/9QDYUx8Qufp3IZMcptvHtFqxyTLZO V4orZxg/NSjtCw3eQDXgzVBuMIHB1PdDH/BZtkuugBhSlI7XhmSpN5YznEHaW80nNIHm T7EgbCF1dsrmmEkjVYz3PVU7Gjgc1eRHDmEBo1bi3y26DtyQqhhj3TmjYhWtvzgurep1 3ORECLMvAdfMC5aBdOkVvCckMiPIBWCf8HMR5u7KoTzB10Jtc42sMbD/BLU40pFCEn0K 2kcw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=R2qzmF1tqlb5sXVnVAPi3895l0EF4P+hvfQ4PCi4vTY=; b=insOftX8ahiEJ404SUwjJpro8TSpyAvOiTUm/t76HQG7MfpI70QScwU55fGm1cLnP2 JEPfA76OOLNzMdpHko3XgfaGrMFVMk24RusuAbNegl3jBkTqUwb2t7heV0b3sTBIAtyo XyGqPJBmkHCS4c4+OJPUzwk30pkB31QkeIuvSt78ClmH+ytsdqw0TV31+yNR02XOBV0Q F9Twxs3Dn2nq7qp49phq6PltXjB88MZEK0RAxzd5SJhIVWebQuajBLIwRif+hqnn9sl0 19jqHRHQpVyGJF/APFGPJL9NAAJ1PyJrvCWOD6WMJhiEXVi0jRNcfk0dUhuIPpJtZd3B 4PJA== X-Gm-Message-State: ACgBeo02Wbi7vhTPLOD5Zc/ntR6sMURs8nXUYSkYkKhuDLJYSGJlHb+f bwe3a+Td57NZyoAhJXeeSfNtMQ== X-Google-Smtp-Source: AA6agR7DfxVmAeKz7LWY7inE/vo+TQKX7sDRlWJLSLZSjib3BH8INZjLPNrsDeyGdxfyfXzq5ECWEw== X-Received: by 2002:aca:d703:0:b0:343:9d9:1cfa with SMTP id o3-20020acad703000000b0034309d91cfamr5020808oig.16.1660978564754; Fri, 19 Aug 2022 23:56:04 -0700 (PDT) Received: from anup-ubuntu64-vm.. ([171.76.82.68]) by smtp.gmail.com with ESMTPSA id h26-20020a9d641a000000b00636faf5e2d9sm1661098otl.39.2022.08.19.23.56.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Aug 2022 23:56:04 -0700 (PDT) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Marc Zyngier , Daniel Lezcano Cc: Atish Patra , Alistair Francis , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH v8 4/7] RISC-V: Treat IPIs as normal Linux IRQs Date: Sat, 20 Aug 2022 12:24:43 +0530 Message-Id: <20220820065446.389788-5-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220820065446.389788-1-apatel@ventanamicro.com> References: <20220820065446.389788-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Currently, the RISC-V kernel provides arch specific hooks (i.e. struct riscv_ipi_ops) to register IPI handling methods. The stats gathering of IPIs is also arch specific in the RISC-V kernel. Other architectures (such as ARM, ARM64, and MIPS) have moved away from custom arch specific IPI handling methods. Currently, these architectures have Linux irqchip drivers providing a range of Linux IRQ numbers to be used as IPIs and IPI triggering is done using generic IPI APIs. This approach allows architectures to treat IPIs as normal Linux IRQs and IPI stats gathering is done by the generic Linux IRQ subsystem. We extend the RISC-V IPI handling as-per above approach so that arch specific IPI handling methods (struct riscv_ipi_ops) can be removed and the IPI handling is done through the Linux IRQ subsystem. Signed-off-by: Anup Patel --- arch/riscv/Kconfig | 2 + arch/riscv/include/asm/sbi.h | 7 ++ arch/riscv/include/asm/smp.h | 35 ++++--- arch/riscv/kernel/Makefile | 1 + arch/riscv/kernel/cpu-hotplug.c | 3 +- arch/riscv/kernel/irq.c | 3 +- arch/riscv/kernel/sbi-ipi.c | 60 ++++++++++++ arch/riscv/kernel/sbi.c | 17 ---- arch/riscv/kernel/smp.c | 153 +++++++++++++++--------------- arch/riscv/kernel/smpboot.c | 5 +- drivers/clocksource/timer-clint.c | 42 +++++--- drivers/irqchip/irq-riscv-intc.c | 55 +++++------ 12 files changed, 228 insertions(+), 155 deletions(-) create mode 100644 arch/riscv/kernel/sbi-ipi.c diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 0ebd8da388d8..5f52b630bf92 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -59,6 +59,8 @@ config RISCV select GENERIC_GETTIMEOFDAY if HAVE_GENERIC_VDSO select GENERIC_IDLE_POLL_SETUP select GENERIC_IOREMAP if MMU + select GENERIC_IRQ_IPI if SMP + select GENERIC_IRQ_IPI_MUX if SMP select GENERIC_IRQ_MULTI_HANDLER select GENERIC_IRQ_SHOW select GENERIC_IRQ_SHOW_LEVEL diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index 2a0ef738695e..c43f115714a0 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -327,4 +327,11 @@ int sbi_err_map_linux_errno(int err); static inline int sbi_remote_fence_i(const struct cpumask *cpu_mask) { ret= urn -1; } static inline void sbi_init(void) {} #endif /* CONFIG_RISCV_SBI */ + +#if IS_ENABLED(CONFIG_SMP) && IS_ENABLED(CONFIG_RISCV_SBI) +void sbi_ipi_init(void); +#else +static inline void sbi_ipi_init(void) { } +#endif + #endif /* _ASM_RISCV_SBI_H */ diff --git a/arch/riscv/include/asm/smp.h b/arch/riscv/include/asm/smp.h index d3443be7eedc..79ed0b73cd4e 100644 --- a/arch/riscv/include/asm/smp.h +++ b/arch/riscv/include/asm/smp.h @@ -15,11 +15,6 @@ struct seq_file; extern unsigned long boot_cpu_hartid; =20 -struct riscv_ipi_ops { - void (*ipi_inject)(const struct cpumask *target); - void (*ipi_clear)(void); -}; - #ifdef CONFIG_SMP /* * Mapping between linux logical cpu index and hartid. @@ -33,9 +28,6 @@ void show_ipi_stats(struct seq_file *p, int prec); /* SMP initialization hook for setup_arch */ void __init setup_smp(void); =20 -/* Called from C code, this handles an IPI. */ -void handle_IPI(struct pt_regs *regs); - /* Hook for the generic smp_call_function_many() routine. */ void arch_send_call_function_ipi_mask(struct cpumask *mask); =20 @@ -44,11 +36,17 @@ void arch_send_call_function_single_ipi(int cpu); =20 int riscv_hartid_to_cpuid(unsigned long hartid); =20 -/* Set custom IPI operations */ -void riscv_set_ipi_ops(const struct riscv_ipi_ops *ops); +/* Enable IPI for CPU hotplug */ +void riscv_ipi_enable(void); + +/* Disable IPI for CPU hotplug */ +void riscv_ipi_disable(void); =20 -/* Clear IPI for current CPU */ -void riscv_clear_ipi(void); +/* Check if IPI interrupt numbers are available */ +bool riscv_ipi_have_virq_range(void); + +/* Set the IPI interrupt numbers for arch (called by irqchip drivers) */ +void riscv_ipi_set_virq_range(int virq, int nr); =20 /* Secondary hart entry */ asmlinkage void smp_callin(void); @@ -82,11 +80,20 @@ static inline unsigned long cpuid_to_hartid_map(int cpu) return boot_cpu_hartid; } =20 -static inline void riscv_set_ipi_ops(const struct riscv_ipi_ops *ops) +static inline void riscv_ipi_enable(void) { } =20 -static inline void riscv_clear_ipi(void) +static inline void riscv_ipi_disable(void) +{ +} + +static inline bool riscv_ipi_have_virq_range(void) +{ + return false; +} + +static inline void riscv_ipi_set_virq_range(int virq, int nr) { } =20 diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile index 33bb60a354cd..173497b22e95 100644 --- a/arch/riscv/kernel/Makefile +++ b/arch/riscv/kernel/Makefile @@ -74,6 +74,7 @@ obj-$(CONFIG_PERF_EVENTS) +=3D perf_callchain.o obj-$(CONFIG_HAVE_PERF_REGS) +=3D perf_regs.o obj-$(CONFIG_RISCV_SBI) +=3D sbi.o ifeq ($(CONFIG_RISCV_SBI), y) +obj-$(CONFIG_SMP) +=3D sbi-ipi.o obj-$(CONFIG_SMP) +=3D cpu_ops_sbi.o endif obj-$(CONFIG_HOTPLUG_CPU) +=3D cpu-hotplug.o diff --git a/arch/riscv/kernel/cpu-hotplug.c b/arch/riscv/kernel/cpu-hotplu= g.c index f7a832e3a1d1..39235cf50652 100644 --- a/arch/riscv/kernel/cpu-hotplug.c +++ b/arch/riscv/kernel/cpu-hotplug.c @@ -13,7 +13,7 @@ #include #include #include -#include +#include =20 bool cpu_has_hotplug(unsigned int cpu) { @@ -43,6 +43,7 @@ int __cpu_disable(void) remove_cpu_topology(cpu); numa_remove_cpu(cpu); set_cpu_online(cpu, false); + riscv_ipi_disable(); irq_migrate_all_off_this_cpu(); =20 return ret; diff --git a/arch/riscv/kernel/irq.c b/arch/riscv/kernel/irq.c index 96d3171f0ca1..eb9a68a539e6 100644 --- a/arch/riscv/kernel/irq.c +++ b/arch/riscv/kernel/irq.c @@ -10,7 +10,7 @@ #include #include #include -#include +#include =20 static struct fwnode_handle *(*__get_intc_node)(void); =20 @@ -39,4 +39,5 @@ void __init init_IRQ(void) irqchip_init(); if (!handle_arch_irq) panic("No interrupt controller found."); + sbi_ipi_init(); } diff --git a/arch/riscv/kernel/sbi-ipi.c b/arch/riscv/kernel/sbi-ipi.c new file mode 100644 index 000000000000..0bb070a5dcb4 --- /dev/null +++ b/arch/riscv/kernel/sbi-ipi.c @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Multiplex several IPIs over a single HW IPI. + * + * Copyright (c) 2022 Ventana Micro Systems Inc. + */ + +#define pr_fmt(fmt) "riscv: " fmt +#include +#include +#include +#include + +static void sbi_send_cpumask_ipi(unsigned int parent_virq, void *data, + const struct cpumask *target) +{ + sbi_send_ipi(target); +} + +static void sbi_ipi_clear(unsigned int parent_virq, void *data) +{ + csr_clear(CSR_IP, IE_SIE); +} + +static struct ipi_mux_ops sbi_ipi_ops =3D { + .ipi_mux_pre_handle =3D sbi_ipi_clear, + .ipi_mux_send =3D sbi_send_cpumask_ipi, +}; + +void __init sbi_ipi_init(void) +{ + int virq, parent_virq; + struct irq_domain *domain; + + if (riscv_ipi_have_virq_range()) + return; + + domain =3D irq_find_matching_fwnode(riscv_get_intc_hwnode(), + DOMAIN_BUS_ANY); + if (!domain) { + pr_err("unable to find INTC IRQ domain\n"); + return; + } + + parent_virq =3D irq_create_mapping(domain, RV_IRQ_SOFT); + if (!parent_virq) { + pr_err("unable to create INTC IRQ mapping\n"); + return; + } + + virq =3D ipi_mux_create(parent_virq, BITS_PER_BYTE, &sbi_ipi_ops, NULL); + if (virq <=3D 0) { + pr_err("unable to create muxed IPIs\n"); + irq_dispose_mapping(parent_virq); + return; + } + + riscv_ipi_set_virq_range(virq, BITS_PER_BYTE); + pr_info("providing IPIs using SBI IPI extension\n"); +} diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c index fc614650a2e3..e9f04eba0e09 100644 --- a/arch/riscv/kernel/sbi.c +++ b/arch/riscv/kernel/sbi.c @@ -638,21 +638,6 @@ long sbi_get_mimpid(void) return __sbi_base_ecall(SBI_EXT_BASE_GET_MIMPID); } =20 -static void sbi_send_cpumask_ipi(const struct cpumask *target) -{ - sbi_send_ipi(target); -} - -static void sbi_ipi_clear(void) -{ - csr_clear(CSR_IP, IE_SIE); -} - -static const struct riscv_ipi_ops sbi_ipi_ops =3D { - .ipi_inject =3D sbi_send_cpumask_ipi, - .ipi_clear =3D sbi_ipi_clear -}; - void __init sbi_init(void) { int ret; @@ -699,6 +684,4 @@ void __init sbi_init(void) __sbi_send_ipi =3D __sbi_send_ipi_v01; __sbi_rfence =3D __sbi_rfence_v01; } - - riscv_set_ipi_ops(&sbi_ipi_ops); } diff --git a/arch/riscv/kernel/smp.c b/arch/riscv/kernel/smp.c index c56d67f53ea9..e25d39cd2d27 100644 --- a/arch/riscv/kernel/smp.c +++ b/arch/riscv/kernel/smp.c @@ -17,9 +17,9 @@ #include #include #include +#include #include =20 -#include #include #include =20 @@ -41,11 +41,9 @@ void __init smp_setup_processor_id(void) cpuid_to_hartid_map(0) =3D boot_cpu_hartid; } =20 -/* A collection of single bit ipi messages. */ -static struct { - unsigned long stats[IPI_MAX] ____cacheline_aligned; - unsigned long bits ____cacheline_aligned; -} ipi_data[NR_CPUS] __cacheline_aligned; +static int ipi_virq_base __ro_after_init; +static int nr_ipi __ro_after_init =3D IPI_MAX; +static struct irq_desc *ipi_desc[IPI_MAX] __read_mostly; =20 int riscv_hartid_to_cpuid(unsigned long hartid) { @@ -71,46 +69,14 @@ static void ipi_stop(void) wait_for_interrupt(); } =20 -static const struct riscv_ipi_ops *ipi_ops __ro_after_init; - -void riscv_set_ipi_ops(const struct riscv_ipi_ops *ops) -{ - ipi_ops =3D ops; -} -EXPORT_SYMBOL_GPL(riscv_set_ipi_ops); - -void riscv_clear_ipi(void) -{ - if (ipi_ops && ipi_ops->ipi_clear) - ipi_ops->ipi_clear(); -} -EXPORT_SYMBOL_GPL(riscv_clear_ipi); - static void send_ipi_mask(const struct cpumask *mask, enum ipi_message_typ= e op) { - int cpu; - - smp_mb__before_atomic(); - for_each_cpu(cpu, mask) - set_bit(op, &ipi_data[cpu].bits); - smp_mb__after_atomic(); - - if (ipi_ops && ipi_ops->ipi_inject) - ipi_ops->ipi_inject(mask); - else - pr_warn("SMP: IPI inject method not available\n"); + __ipi_send_mask(ipi_desc[op], mask); } =20 static void send_ipi_single(int cpu, enum ipi_message_type op) { - smp_mb__before_atomic(); - set_bit(op, &ipi_data[cpu].bits); - smp_mb__after_atomic(); - - if (ipi_ops && ipi_ops->ipi_inject) - ipi_ops->ipi_inject(cpumask_of(cpu)); - else - pr_warn("SMP: IPI inject method not available\n"); + __ipi_send_mask(ipi_desc[op], cpumask_of(cpu)); } =20 #ifdef CONFIG_IRQ_WORK @@ -120,55 +86,88 @@ void arch_irq_work_raise(void) } #endif =20 -void handle_IPI(struct pt_regs *regs) +static irqreturn_t handle_IPI(int irq, void *data) +{ + int ipi =3D irq - ipi_virq_base; + + switch (ipi) { + case IPI_RESCHEDULE: + scheduler_ipi(); + break; + case IPI_CALL_FUNC: + generic_smp_call_function_interrupt(); + break; + case IPI_CPU_STOP: + ipi_stop(); + break; + case IPI_IRQ_WORK: + irq_work_run(); + break; +#ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST + case IPI_TIMER: + tick_receive_broadcast(); + break; +#endif + default: + pr_warn("CPU%d: unhandled IPI%d\n", smp_processor_id(), ipi); + break; + }; + + return IRQ_HANDLED; +} + +void riscv_ipi_enable(void) { - unsigned long *pending_ipis =3D &ipi_data[smp_processor_id()].bits; - unsigned long *stats =3D ipi_data[smp_processor_id()].stats; + int i; =20 - riscv_clear_ipi(); + if (WARN_ON_ONCE(!ipi_virq_base)) + return; =20 - while (true) { - unsigned long ops; + for (i =3D 0; i < nr_ipi; i++) + enable_percpu_irq(ipi_virq_base + i, 0); +} =20 - /* Order bit clearing and data access. */ - mb(); +void riscv_ipi_disable(void) +{ + int i; =20 - ops =3D xchg(pending_ipis, 0); - if (ops =3D=3D 0) - return; + if (WARN_ON_ONCE(!ipi_virq_base)) + return; =20 - if (ops & (1 << IPI_RESCHEDULE)) { - stats[IPI_RESCHEDULE]++; - scheduler_ipi(); - } + for (i =3D 0; i < nr_ipi; i++) + disable_percpu_irq(ipi_virq_base + i); +} =20 - if (ops & (1 << IPI_CALL_FUNC)) { - stats[IPI_CALL_FUNC]++; - generic_smp_call_function_interrupt(); - } +bool riscv_ipi_have_virq_range(void) +{ + return (ipi_virq_base) ? true : false; +} =20 - if (ops & (1 << IPI_CPU_STOP)) { - stats[IPI_CPU_STOP]++; - ipi_stop(); - } +void riscv_ipi_set_virq_range(int virq, int nr) +{ + int i, err; =20 - if (ops & (1 << IPI_IRQ_WORK)) { - stats[IPI_IRQ_WORK]++; - irq_work_run(); - } + if (WARN_ON(ipi_virq_base)) + return; =20 -#ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST - if (ops & (1 << IPI_TIMER)) { - stats[IPI_TIMER]++; - tick_receive_broadcast(); - } -#endif - BUG_ON((ops >> IPI_MAX) !=3D 0); + WARN_ON(nr < IPI_MAX); + nr_ipi =3D min(nr, IPI_MAX); + ipi_virq_base =3D virq; + + /* Request IPIs */ + for (i =3D 0; i < nr_ipi; i++) { + err =3D request_percpu_irq(ipi_virq_base + i, handle_IPI, + "IPI", &ipi_virq_base); + WARN_ON(err); =20 - /* Order data access and bit testing. */ - mb(); + ipi_desc[i] =3D irq_to_desc(ipi_virq_base + i); + irq_set_status_flags(ipi_virq_base + i, IRQ_HIDDEN); } + + /* Enabled IPIs for boot CPU immediately */ + riscv_ipi_enable(); } +EXPORT_SYMBOL_GPL(riscv_ipi_set_virq_range); =20 static const char * const ipi_names[] =3D { [IPI_RESCHEDULE] =3D "Rescheduling interrupts", @@ -186,7 +185,7 @@ void show_ipi_stats(struct seq_file *p, int prec) seq_printf(p, "%*s%u:%s", prec - 1, "IPI", i, prec >=3D 4 ? " " : ""); for_each_online_cpu(cpu) - seq_printf(p, "%10lu ", ipi_data[cpu].stats[i]); + seq_printf(p, "%10u ", irq_desc_kstat_cpu(ipi_desc[i], cpu)); seq_printf(p, " %s\n", ipi_names[i]); } } diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c index a752c7b41683..0e41c550d3ff 100644 --- a/arch/riscv/kernel/smpboot.c +++ b/arch/riscv/kernel/smpboot.c @@ -30,7 +30,6 @@ #include #include #include -#include #include =20 #include "head.h" @@ -156,12 +155,12 @@ asmlinkage __visible void smp_callin(void) struct mm_struct *mm =3D &init_mm; unsigned int curr_cpuid =3D smp_processor_id(); =20 - riscv_clear_ipi(); - /* All kernel threads share the same mm context. */ mmgrab(mm); current->active_mm =3D mm; =20 + riscv_ipi_enable(); + notify_cpu_starting(curr_cpuid); numa_add_cpu(curr_cpuid); update_siblings_masks(curr_cpuid); diff --git a/drivers/clocksource/timer-clint.c b/drivers/clocksource/timer-= clint.c index 6cfe2ab73eb0..ac7c2caaa65a 100644 --- a/drivers/clocksource/timer-clint.c +++ b/drivers/clocksource/timer-clint.c @@ -17,6 +17,8 @@ #include #include #include +#include +#include #include #include #include @@ -31,6 +33,7 @@ =20 /* CLINT manages IPI and Timer for RISC-V M-mode */ static u32 __iomem *clint_ipi_base; +static unsigned int clint_ipi_irq; static u64 __iomem *clint_timer_cmp; static u64 __iomem *clint_timer_val; static unsigned long clint_timer_freq; @@ -41,7 +44,8 @@ u64 __iomem *clint_time_val; EXPORT_SYMBOL(clint_time_val); #endif =20 -static void clint_send_ipi(const struct cpumask *target) +static void clint_send_ipi(unsigned int parent_virq, void *data, + const struct cpumask *target) { unsigned int cpu; =20 @@ -49,14 +53,14 @@ static void clint_send_ipi(const struct cpumask *target) writel(1, clint_ipi_base + cpuid_to_hartid_map(cpu)); } =20 -static void clint_clear_ipi(void) +static void clint_clear_ipi(unsigned int parent_virq, void *data) { writel(0, clint_ipi_base + cpuid_to_hartid_map(smp_processor_id())); } =20 -static struct riscv_ipi_ops clint_ipi_ops =3D { - .ipi_inject =3D clint_send_ipi, - .ipi_clear =3D clint_clear_ipi, +static struct ipi_mux_ops clint_ipi_ops =3D { + .ipi_mux_pre_handle =3D clint_clear_ipi, + .ipi_mux_send =3D clint_send_ipi, }; =20 #ifdef CONFIG_64BIT @@ -146,7 +150,7 @@ static irqreturn_t clint_timer_interrupt(int irq, void = *dev_id) =20 static int __init clint_timer_init_dt(struct device_node *np) { - int rc; + int rc, virq; u32 i, nr_irqs; void __iomem *base; struct of_phandle_args oirq; @@ -170,6 +174,12 @@ static int __init clint_timer_init_dt(struct device_no= de *np) return -ENODEV; } =20 + /* Find parent irq domain and map ipi irq */ + if (!clint_ipi_irq && + oirq.args[0] =3D=3D RV_IRQ_SOFT && + irq_find_host(oirq.np)) + clint_ipi_irq =3D irq_of_parse_and_map(np, i); + /* Find parent irq domain and map timer irq */ if (!clint_timer_irq && oirq.args[0] =3D=3D RV_IRQ_TIMER && @@ -177,9 +187,9 @@ static int __init clint_timer_init_dt(struct device_nod= e *np) clint_timer_irq =3D irq_of_parse_and_map(np, i); } =20 - /* If CLINT timer irq not found then fail */ - if (!clint_timer_irq) { - pr_err("%pOFP: timer irq not found\n", np); + /* If CLINT ipi or timer irq not found then fail */ + if (!clint_ipi_irq || !clint_timer_irq) { + pr_err("%pOFP: ipi/timer irq not found\n", np); return -ENODEV; } =20 @@ -228,11 +238,21 @@ static int __init clint_timer_init_dt(struct device_n= ode *np) goto fail_free_irq; } =20 - riscv_set_ipi_ops(&clint_ipi_ops); - clint_clear_ipi(); + virq =3D ipi_mux_create(clint_ipi_irq, BITS_PER_BYTE, + &clint_ipi_ops, NULL); + if (virq <=3D 0) { + pr_err("unable to create muxed IPIs\n"); + rc =3D (virq < 0) ? virq : -ENODEV; + goto fail_remove_cpuhp; + } + + riscv_ipi_set_virq_range(virq, BITS_PER_BYTE); + clint_clear_ipi(clint_ipi_irq, NULL); =20 return 0; =20 +fail_remove_cpuhp: + cpuhp_remove_state(CPUHP_AP_CLINT_TIMER_STARTING); fail_free_irq: free_irq(clint_timer_irq, &clint_clock_event); fail_iounmap: diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-i= ntc.c index 9066467e99e4..784d25645704 100644 --- a/drivers/irqchip/irq-riscv-intc.c +++ b/drivers/irqchip/irq-riscv-intc.c @@ -26,20 +26,7 @@ static asmlinkage void riscv_intc_irq(struct pt_regs *re= gs) if (unlikely(cause >=3D BITS_PER_LONG)) panic("unexpected interrupt cause"); =20 - switch (cause) { -#ifdef CONFIG_SMP - case RV_IRQ_SOFT: - /* - * We only use software interrupts to pass IPIs, so if a - * non-SMP system gets one, then we don't know what to do. - */ - handle_IPI(regs); - break; -#endif - default: - generic_handle_domain_irq(intc_domain, cause); - break; - } + generic_handle_domain_irq(intc_domain, cause); } =20 /* @@ -59,18 +46,6 @@ static void riscv_intc_irq_unmask(struct irq_data *d) csr_set(CSR_IE, BIT(d->hwirq)); } =20 -static int riscv_intc_cpu_starting(unsigned int cpu) -{ - csr_set(CSR_IE, BIT(RV_IRQ_SOFT)); - return 0; -} - -static int riscv_intc_cpu_dying(unsigned int cpu) -{ - csr_clear(CSR_IE, BIT(RV_IRQ_SOFT)); - return 0; -} - static struct irq_chip riscv_intc_chip =3D { .name =3D "RISC-V INTC", .irq_mask =3D riscv_intc_irq_mask, @@ -87,9 +62,32 @@ static int riscv_intc_domain_map(struct irq_domain *d, u= nsigned int irq, return 0; } =20 +static int riscv_intc_domain_alloc(struct irq_domain *domain, + unsigned int virq, unsigned int nr_irqs, + void *arg) +{ + int i, ret; + irq_hw_number_t hwirq; + unsigned int type =3D IRQ_TYPE_NONE; + struct irq_fwspec *fwspec =3D arg; + + ret =3D irq_domain_translate_onecell(domain, fwspec, &hwirq, &type); + if (ret) + return ret; + + for (i =3D 0; i < nr_irqs; i++) { + ret =3D riscv_intc_domain_map(domain, virq + i, hwirq + i); + if (ret) + return ret; + } + + return 0; +} + static const struct irq_domain_ops riscv_intc_domain_ops =3D { .map =3D riscv_intc_domain_map, .xlate =3D irq_domain_xlate_onecell, + .alloc =3D riscv_intc_domain_alloc }; =20 static struct fwnode_handle *riscv_intc_hwnode(void) @@ -133,11 +131,6 @@ static int __init riscv_intc_init(struct device_node *= node, =20 riscv_set_intc_hwnode_fn(riscv_intc_hwnode); =20 - cpuhp_setup_state(CPUHP_AP_IRQ_RISCV_STARTING, - "irqchip/riscv/intc:starting", - riscv_intc_cpu_starting, - riscv_intc_cpu_dying); - pr_info("%d local interrupts mapped\n", BITS_PER_LONG); =20 return 0; --=20 2.34.1 From nobody Fri Apr 10 18:34:52 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B20B6C25B08 for ; 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([171.76.82.68]) by smtp.gmail.com with ESMTPSA id h26-20020a9d641a000000b00636faf5e2d9sm1661098otl.39.2022.08.19.23.56.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Aug 2022 23:56:08 -0700 (PDT) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Marc Zyngier , Daniel Lezcano Cc: Atish Patra , Alistair Francis , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH v8 5/7] RISC-V: Allow marking IPIs as suitable for remote FENCEs Date: Sat, 20 Aug 2022 12:24:44 +0530 Message-Id: <20220820065446.389788-6-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220820065446.389788-1-apatel@ventanamicro.com> References: <20220820065446.389788-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" To do remote FENCEs (i.e. remote TLB flushes) using IPI calls on the RISC-V kernel, we need hardware mechanism to directly inject IPI from the supervisor mode (i.e. RISC-V kernel) instead of using SBI calls. The upcoming AIA IMSIC devices allow direct IPI injection from the supervisor mode (i.e. RISC-V kernel). To support this, we extend the riscv_ipi_set_virq_range() function so that IPI provider (i.e. irqchip drivers can mark IPIs as suitable for remote FENCEs. Signed-off-by: Anup Patel --- arch/riscv/include/asm/smp.h | 18 ++++++++++++++++-- arch/riscv/kernel/sbi-ipi.c | 2 +- arch/riscv/kernel/smp.c | 11 ++++++++++- drivers/clocksource/timer-clint.c | 2 +- 4 files changed, 28 insertions(+), 5 deletions(-) diff --git a/arch/riscv/include/asm/smp.h b/arch/riscv/include/asm/smp.h index 79ed0b73cd4e..56976e41a21e 100644 --- a/arch/riscv/include/asm/smp.h +++ b/arch/riscv/include/asm/smp.h @@ -16,6 +16,9 @@ struct seq_file; extern unsigned long boot_cpu_hartid; =20 #ifdef CONFIG_SMP + +#include + /* * Mapping between linux logical cpu index and hartid. */ @@ -46,7 +49,12 @@ void riscv_ipi_disable(void); bool riscv_ipi_have_virq_range(void); =20 /* Set the IPI interrupt numbers for arch (called by irqchip drivers) */ -void riscv_ipi_set_virq_range(int virq, int nr); +void riscv_ipi_set_virq_range(int virq, int nr, bool use_for_rfence); + +/* Check if we can use IPIs for remote FENCEs */ +DECLARE_STATIC_KEY_FALSE(riscv_ipi_for_rfence); +#define riscv_use_ipi_for_rfence() \ + static_branch_unlikely(&riscv_ipi_for_rfence) =20 /* Secondary hart entry */ asmlinkage void smp_callin(void); @@ -93,10 +101,16 @@ static inline bool riscv_ipi_have_virq_range(void) return false; } =20 -static inline void riscv_ipi_set_virq_range(int virq, int nr) +static inline void riscv_ipi_set_virq_range(int virq, int nr, + bool use_for_rfence) { } =20 +static inline bool riscv_use_ipi_for_rfence(void) +{ + return false; +} + #endif /* CONFIG_SMP */ =20 #if defined(CONFIG_HOTPLUG_CPU) && (CONFIG_SMP) diff --git a/arch/riscv/kernel/sbi-ipi.c b/arch/riscv/kernel/sbi-ipi.c index 0bb070a5dcb4..27fdc394d2f0 100644 --- a/arch/riscv/kernel/sbi-ipi.c +++ b/arch/riscv/kernel/sbi-ipi.c @@ -55,6 +55,6 @@ void __init sbi_ipi_init(void) return; } =20 - riscv_ipi_set_virq_range(virq, BITS_PER_BYTE); + riscv_ipi_set_virq_range(virq, BITS_PER_BYTE, false); pr_info("providing IPIs using SBI IPI extension\n"); } diff --git a/arch/riscv/kernel/smp.c b/arch/riscv/kernel/smp.c index e25d39cd2d27..cb2bda4822de 100644 --- a/arch/riscv/kernel/smp.c +++ b/arch/riscv/kernel/smp.c @@ -143,7 +143,10 @@ bool riscv_ipi_have_virq_range(void) return (ipi_virq_base) ? true : false; } =20 -void riscv_ipi_set_virq_range(int virq, int nr) +DEFINE_STATIC_KEY_FALSE(riscv_ipi_for_rfence); +EXPORT_SYMBOL_GPL(riscv_ipi_for_rfence); + +void riscv_ipi_set_virq_range(int virq, int nr, bool use_for_rfence) { int i, err; =20 @@ -166,6 +169,12 @@ void riscv_ipi_set_virq_range(int virq, int nr) =20 /* Enabled IPIs for boot CPU immediately */ riscv_ipi_enable(); + + /* Update RFENCE static key */ + if (use_for_rfence) + static_branch_enable(&riscv_ipi_for_rfence); + else + static_branch_disable(&riscv_ipi_for_rfence); } EXPORT_SYMBOL_GPL(riscv_ipi_set_virq_range); =20 diff --git a/drivers/clocksource/timer-clint.c b/drivers/clocksource/timer-= clint.c index ac7c2caaa65a..f418816fd706 100644 --- a/drivers/clocksource/timer-clint.c +++ b/drivers/clocksource/timer-clint.c @@ -246,7 +246,7 @@ static int __init clint_timer_init_dt(struct device_nod= e *np) goto fail_remove_cpuhp; } =20 - riscv_ipi_set_virq_range(virq, BITS_PER_BYTE); + riscv_ipi_set_virq_range(virq, BITS_PER_BYTE, true); clint_clear_ipi(clint_ipi_irq, NULL); =20 return 0; --=20 2.34.1 From nobody Fri Apr 10 18:34:52 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 27ED4C32772 for ; Sat, 20 Aug 2022 06:56:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245735AbiHTG4c (ORCPT ); Sat, 20 Aug 2022 02:56:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34100 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245541AbiHTG4R (ORCPT ); Sat, 20 Aug 2022 02:56:17 -0400 Received: from mail-oi1-x22c.google.com (mail-oi1-x22c.google.com [IPv6:2607:f8b0:4864:20::22c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 31E0FC0B4A for ; Fri, 19 Aug 2022 23:56:15 -0700 (PDT) Received: by mail-oi1-x22c.google.com with SMTP id s199so6976828oie.3 for ; Fri, 19 Aug 2022 23:56:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=BjmiwAV+qkEddhUojBQVUbZIbS/TIGSArMUYW9Y9o7E=; b=ke50uMDbvR6TR8jTctSoQUUFZ4uWRDpb2TBPkcm72JfcDAy2vcsrV1bwBq9fW6cRmH Ft+KbVyVomoxjrpzCs4vN2YQB0FKHyWmiyJKBC+hxZX5+hgr8+mswTFOTbU2ST38lG3P tjcXo19TZpK9Vbgb69vYKj3FQGCQuWHEiHwC9gZUBdUQt3yrS94eh6Dxg0CPGAs0C661 qNwWH4Ar6G0fDPUVtm7uNoD6DGIanAUo5ek71iM1u+yPilnZDnVWoHM9zz57OHpbYryv s44h3UUhPahaDEb6d4nQ1K/OIKot03usdgpmGt3XG+f/OZL2e/cZYlDOq4SfO82UxZ8p hzPA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=BjmiwAV+qkEddhUojBQVUbZIbS/TIGSArMUYW9Y9o7E=; b=ndXtB3taSIqemXuzN6LzVZyBERZgMbsmgQqkKjKFfqkM6c3USrebMZxj7lEZ211uEj +wduZ5HGssBG5Y2Y/ZSlJiYmOfFDLjDp1iLv6uRgulw5nS9eI7PmkVhzUrrq8f71I7aH RpUnYZkAXcKc+zAkuTb24MxXlT/SyOP6bk7S2udc/q23L01/fk9VRGNnvLTC3Vox2I6x /tufu9WCrU1t4N10h9VSK2q3oEB5NZp80gUO0J+DJfTgzWxYzyCzrE3bANgpNxar3x7m o2Gy25EOqPQmx1FxHcZTGR9/+vzfiST4hNpaY9V3vdETKtG8YIomXfu9QmWAEbn/NeGm oK6w== X-Gm-Message-State: ACgBeo32LW14Fzj+9EbK+AxDYnECzv6lzIk/zRUQfeoEq77koH9LCkCK 4qeHb8vM+eZcevSPwBB0F4mg5A== X-Google-Smtp-Source: AA6agR77yKrj6rrlDl1Dapu8IarhKw8BUnBluIJ+l2drA7Otr3OgkV+I/+PscH3BzI6N9bgfpsOFLA== X-Received: by 2002:a05:6808:1441:b0:333:3929:d079 with SMTP id x1-20020a056808144100b003333929d079mr4973466oiv.21.1660978574361; Fri, 19 Aug 2022 23:56:14 -0700 (PDT) Received: from anup-ubuntu64-vm.. ([171.76.82.68]) by smtp.gmail.com with ESMTPSA id h26-20020a9d641a000000b00636faf5e2d9sm1661098otl.39.2022.08.19.23.56.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Aug 2022 23:56:13 -0700 (PDT) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Marc Zyngier , Daniel Lezcano Cc: Atish Patra , Alistair Francis , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH v8 6/7] RISC-V: Use IPIs for remote TLB flush when possible Date: Sat, 20 Aug 2022 12:24:45 +0530 Message-Id: <20220820065446.389788-7-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220820065446.389788-1-apatel@ventanamicro.com> References: <20220820065446.389788-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" If we have specialized interrupt controller (such as AIA IMSIC) which allows supervisor mode to directly inject IPIs without any assistance from M-mode or HS-mode then using such specialized interrupt controller, we can do remote TLB flushes directly from supervisor mode instead of using the SBI RFENCE calls. This patch extends remote TLB flush functions to use supervisor mode IPIs whenever direct supervisor mode IPIs.are supported by interrupt controller. Signed-off-by: Anup Patel --- arch/riscv/mm/tlbflush.c | 93 +++++++++++++++++++++++++++++++++------- 1 file changed, 78 insertions(+), 15 deletions(-) diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c index 37ed760d007c..27a7db8eb2c4 100644 --- a/arch/riscv/mm/tlbflush.c +++ b/arch/riscv/mm/tlbflush.c @@ -23,14 +23,62 @@ static inline void local_flush_tlb_page_asid(unsigned l= ong addr, : "memory"); } =20 +static inline void local_flush_tlb_range(unsigned long start, + unsigned long size, unsigned long stride) +{ + if (size <=3D stride) + local_flush_tlb_page(start); + else + local_flush_tlb_all(); +} + +static inline void local_flush_tlb_range_asid(unsigned long start, + unsigned long size, unsigned long stride, unsigned long asid) +{ + if (size <=3D stride) + local_flush_tlb_page_asid(start, asid); + else + local_flush_tlb_all_asid(asid); +} + +static void __ipi_flush_tlb_all(void *info) +{ + local_flush_tlb_all(); +} + void flush_tlb_all(void) { - sbi_remote_sfence_vma(NULL, 0, -1); + if (riscv_use_ipi_for_rfence()) + on_each_cpu(__ipi_flush_tlb_all, NULL, 1); + else + sbi_remote_sfence_vma(NULL, 0, -1); +} + +struct flush_tlb_range_data { + unsigned long asid; + unsigned long start; + unsigned long size; + unsigned long stride; +}; + +static void __ipi_flush_tlb_range_asid(void *info) +{ + struct flush_tlb_range_data *d =3D info; + + local_flush_tlb_range_asid(d->start, d->size, d->stride, d->asid); +} + +static void __ipi_flush_tlb_range(void *info) +{ + struct flush_tlb_range_data *d =3D info; + + local_flush_tlb_range(d->start, d->size, d->stride); } =20 -static void __sbi_tlb_flush_range(struct mm_struct *mm, unsigned long star= t, - unsigned long size, unsigned long stride) +static void __flush_tlb_range(struct mm_struct *mm, unsigned long start, + unsigned long size, unsigned long stride) { + struct flush_tlb_range_data ftd; struct cpumask *cmask =3D mm_cpumask(mm); unsigned int cpuid; bool broadcast; @@ -45,19 +93,34 @@ static void __sbi_tlb_flush_range(struct mm_struct *mm,= unsigned long start, unsigned long asid =3D atomic_long_read(&mm->context.id); =20 if (broadcast) { - sbi_remote_sfence_vma_asid(cmask, start, size, asid); - } else if (size <=3D stride) { - local_flush_tlb_page_asid(start, asid); + if (riscv_use_ipi_for_rfence()) { + ftd.asid =3D asid; + ftd.start =3D start; + ftd.size =3D size; + ftd.stride =3D stride; + on_each_cpu_mask(cmask, + __ipi_flush_tlb_range_asid, + &ftd, 1); + } else + sbi_remote_sfence_vma_asid(cmask, + start, size, asid); } else { - local_flush_tlb_all_asid(asid); + local_flush_tlb_range_asid(start, size, stride, asid); } } else { if (broadcast) { - sbi_remote_sfence_vma(cmask, start, size); - } else if (size <=3D stride) { - local_flush_tlb_page(start); + if (riscv_use_ipi_for_rfence()) { + ftd.asid =3D 0; + ftd.start =3D start; + ftd.size =3D size; + ftd.stride =3D stride; + on_each_cpu_mask(cmask, + __ipi_flush_tlb_range, + &ftd, 1); + } else + sbi_remote_sfence_vma(cmask, start, size); } else { - local_flush_tlb_all(); + local_flush_tlb_range(start, size, stride); } } =20 @@ -66,23 +129,23 @@ static void __sbi_tlb_flush_range(struct mm_struct *mm= , unsigned long start, =20 void flush_tlb_mm(struct mm_struct *mm) { - __sbi_tlb_flush_range(mm, 0, -1, PAGE_SIZE); + __flush_tlb_range(mm, 0, -1, PAGE_SIZE); } =20 void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr) { - __sbi_tlb_flush_range(vma->vm_mm, addr, PAGE_SIZE, PAGE_SIZE); + __flush_tlb_range(vma->vm_mm, addr, PAGE_SIZE, PAGE_SIZE); } =20 void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end) { - __sbi_tlb_flush_range(vma->vm_mm, start, end - start, PAGE_SIZE); + __flush_tlb_range(vma->vm_mm, start, end - start, PAGE_SIZE); } #ifdef CONFIG_TRANSPARENT_HUGEPAGE void flush_pmd_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end) { - __sbi_tlb_flush_range(vma->vm_mm, start, end - start, PMD_SIZE); + __flush_tlb_range(vma->vm_mm, start, end - start, PMD_SIZE); } #endif --=20 2.34.1 From nobody Fri Apr 10 18:34:52 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 381C9C32772 for ; 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([171.76.82.68]) by smtp.gmail.com with ESMTPSA id h26-20020a9d641a000000b00636faf5e2d9sm1661098otl.39.2022.08.19.23.56.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Aug 2022 23:56:18 -0700 (PDT) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Marc Zyngier , Daniel Lezcano Cc: Atish Patra , Alistair Francis , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH v8 7/7] RISC-V: Use IPIs for remote icache flush when possible Date: Sat, 20 Aug 2022 12:24:46 +0530 Message-Id: <20220820065446.389788-8-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220820065446.389788-1-apatel@ventanamicro.com> References: <20220820065446.389788-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" If we have specialized interrupt controller (such as AIA IMSIC) which allows supervisor mode to directly inject IPIs without any assistance from M-mode or HS-mode then using such specialized interrupt controller, we can do remote icache flushe directly from supervisor mode instead of using the SBI RFENCE calls. This patch extends remote icache flush functions to use supervisor mode IPIs whenever direct supervisor mode IPIs.are supported by interrupt controller. Signed-off-by: Anup Patel --- arch/riscv/mm/cacheflush.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/riscv/mm/cacheflush.c b/arch/riscv/mm/cacheflush.c index 6cb7d96ad9c7..7c7e44aaf791 100644 --- a/arch/riscv/mm/cacheflush.c +++ b/arch/riscv/mm/cacheflush.c @@ -18,7 +18,7 @@ void flush_icache_all(void) { local_flush_icache_all(); =20 - if (IS_ENABLED(CONFIG_RISCV_SBI)) + if (IS_ENABLED(CONFIG_RISCV_SBI) && !riscv_use_ipi_for_rfence()) sbi_remote_fence_i(NULL); else on_each_cpu(ipi_remote_fence_i, NULL, 1); @@ -66,7 +66,8 @@ void flush_icache_mm(struct mm_struct *mm, bool local) * with flush_icache_deferred(). */ smp_mb(); - } else if (IS_ENABLED(CONFIG_RISCV_SBI)) { + } else if (IS_ENABLED(CONFIG_RISCV_SBI) && + !riscv_use_ipi_for_rfence()) { sbi_remote_fence_i(&others); } else { on_each_cpu_mask(&others, ipi_remote_fence_i, NULL, 1); --=20 2.34.1