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[31.30.173.67]) by smtp.gmail.com with ESMTPSA id b9-20020a17090630c900b0073c9d68ca0dsm1434287ejb.133.2022.08.19.07.02.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Aug 2022 07:02:56 -0700 (PDT) From: Andrew Jones To: linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org Cc: linux-kernel@vger.kernel.org, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, anup@brainfault.org, mchitale@ventanamicro.com, heiko@sntech.de Subject: [PATCH 3/4] riscv: KVM: Apply insn-def to hfence encodings Date: Fri, 19 Aug 2022 16:02:49 +0200 Message-Id: <20220819140250.3892995-4-ajones@ventanamicro.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220819140250.3892995-1-ajones@ventanamicro.com> References: <20220819140250.3892995-1-ajones@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Introduce hfence instruction encodings and apply them to KVM's use. With the self-documenting nature of the instruction encoding macros, and a spec always within arm's reach, it's safe to remove the comments, so we do that too. Signed-off-by: Andrew Jones Reviewed-by: Anup Patel --- arch/riscv/include/asm/insn-def.h | 8 ++ arch/riscv/kvm/tlb.c | 117 ++++-------------------------- 2 files changed, 21 insertions(+), 104 deletions(-) diff --git a/arch/riscv/include/asm/insn-def.h b/arch/riscv/include/asm/ins= n-def.h index 4cd0208068dd..cd1c0d365f47 100644 --- a/arch/riscv/include/asm/insn-def.h +++ b/arch/riscv/include/asm/insn-def.h @@ -79,4 +79,12 @@ #define RS1(v) __REG(v) #define RS2(v) __REG(v) =20 +#define OPCODE_SYSTEM OPCODE(115) + +#define HFENCE_VVMA(vaddr, asid) \ + INSN_R(OPCODE_SYSTEM, FUNC3(0), FUNC7(17), RD(0), vaddr, asid) + +#define HFENCE_GVMA(gaddr, vmid) \ + INSN_R(OPCODE_SYSTEM, FUNC3(0), FUNC7(49), RD(0), gaddr, vmid) + #endif /* __ASM_INSN_DEF_H */ diff --git a/arch/riscv/kvm/tlb.c b/arch/riscv/kvm/tlb.c index 1a76d0b1907d..f742a0d888e1 100644 --- a/arch/riscv/kvm/tlb.c +++ b/arch/riscv/kvm/tlb.c @@ -12,22 +12,7 @@ #include #include #include - -/* - * Instruction encoding of hfence.gvma is: - * HFENCE.GVMA rs1, rs2 - * HFENCE.GVMA zero, rs2 - * HFENCE.GVMA rs1 - * HFENCE.GVMA - * - * rs1!=3Dzero and rs2!=3Dzero =3D=3D> HFENCE.GVMA rs1, rs2 - * rs1=3D=3Dzero and rs2!=3Dzero =3D=3D> HFENCE.GVMA zero, rs2 - * rs1!=3Dzero and rs2=3D=3Dzero =3D=3D> HFENCE.GVMA rs1 - * rs1=3D=3Dzero and rs2=3D=3Dzero =3D=3D> HFENCE.GVMA - * - * Instruction encoding of HFENCE.GVMA is: - * 0110001 rs2(5) rs1(5) 000 00000 1110011 - */ +#include =20 void kvm_riscv_local_hfence_gvma_vmid_gpa(unsigned long vmid, gpa_t gpa, gpa_t gpsz, @@ -41,31 +26,14 @@ void kvm_riscv_local_hfence_gvma_vmid_gpa(unsigned long= vmid, } =20 for (pos =3D gpa; pos < (gpa + gpsz); pos +=3D BIT(order)) { - /* - * rs1 =3D a0 (GPA >> 2) - * rs2 =3D a1 (VMID) - * HFENCE.GVMA a0, a1 - * 0110001 01011 01010 000 00000 1110011 - */ - asm volatile ("srli a0, %0, 2\n" - "add a1, %1, zero\n" - ".word 0x62b50073\n" - :: "r" (pos), "r" (vmid) - : "a0", "a1", "memory"); + asm volatile (HFENCE_GVMA("%0", "%1") + : : "r" (pos >> 2), "r" (vmid) : "memory"); } } =20 void kvm_riscv_local_hfence_gvma_vmid_all(unsigned long vmid) { - /* - * rs1 =3D zero - * rs2 =3D a0 (VMID) - * HFENCE.GVMA zero, a0 - * 0110001 01010 00000 000 00000 1110011 - */ - asm volatile ("add a0, %0, zero\n" - ".word 0x62a00073\n" - :: "r" (vmid) : "a0", "memory"); + asm volatile(HFENCE_GVMA("zero", "%0") : : "r" (vmid) : "memory"); } =20 void kvm_riscv_local_hfence_gvma_gpa(gpa_t gpa, gpa_t gpsz, @@ -79,45 +47,16 @@ void kvm_riscv_local_hfence_gvma_gpa(gpa_t gpa, gpa_t g= psz, } =20 for (pos =3D gpa; pos < (gpa + gpsz); pos +=3D BIT(order)) { - /* - * rs1 =3D a0 (GPA >> 2) - * rs2 =3D zero - * HFENCE.GVMA a0 - * 0110001 00000 01010 000 00000 1110011 - */ - asm volatile ("srli a0, %0, 2\n" - ".word 0x62050073\n" - :: "r" (pos) : "a0", "memory"); + asm volatile(HFENCE_GVMA("%0", "zero") + : : "r" (pos >> 2) : "memory"); } } =20 void kvm_riscv_local_hfence_gvma_all(void) { - /* - * rs1 =3D zero - * rs2 =3D zero - * HFENCE.GVMA - * 0110001 00000 00000 000 00000 1110011 - */ - asm volatile (".word 0x62000073" ::: "memory"); + asm volatile(HFENCE_GVMA("zero", "zero") : : : "memory"); } =20 -/* - * Instruction encoding of hfence.gvma is: - * HFENCE.VVMA rs1, rs2 - * HFENCE.VVMA zero, rs2 - * HFENCE.VVMA rs1 - * HFENCE.VVMA - * - * rs1!=3Dzero and rs2!=3Dzero =3D=3D> HFENCE.VVMA rs1, rs2 - * rs1=3D=3Dzero and rs2!=3Dzero =3D=3D> HFENCE.VVMA zero, rs2 - * rs1!=3Dzero and rs2=3D=3Dzero =3D=3D> HFENCE.VVMA rs1 - * rs1=3D=3Dzero and rs2=3D=3Dzero =3D=3D> HFENCE.VVMA - * - * Instruction encoding of HFENCE.VVMA is: - * 0010001 rs2(5) rs1(5) 000 00000 1110011 - */ - void kvm_riscv_local_hfence_vvma_asid_gva(unsigned long vmid, unsigned long asid, unsigned long gva, @@ -134,17 +73,8 @@ void kvm_riscv_local_hfence_vvma_asid_gva(unsigned long= vmid, hgatp =3D csr_swap(CSR_HGATP, vmid << HGATP_VMID_SHIFT); =20 for (pos =3D gva; pos < (gva + gvsz); pos +=3D BIT(order)) { - /* - * rs1 =3D a0 (GVA) - * rs2 =3D a1 (ASID) - * HFENCE.VVMA a0, a1 - * 0010001 01011 01010 000 00000 1110011 - */ - asm volatile ("add a0, %0, zero\n" - "add a1, %1, zero\n" - ".word 0x22b50073\n" - :: "r" (pos), "r" (asid) - : "a0", "a1", "memory"); + asm volatile(HFENCE_VVMA("%0", "%1") + : : "r" (pos), "r" (asid) : "memory"); } =20 csr_write(CSR_HGATP, hgatp); @@ -157,15 +87,7 @@ void kvm_riscv_local_hfence_vvma_asid_all(unsigned long= vmid, =20 hgatp =3D csr_swap(CSR_HGATP, vmid << HGATP_VMID_SHIFT); =20 - /* - * rs1 =3D zero - * rs2 =3D a0 (ASID) - * HFENCE.VVMA zero, a0 - * 0010001 01010 00000 000 00000 1110011 - */ - asm volatile ("add a0, %0, zero\n" - ".word 0x22a00073\n" - :: "r" (asid) : "a0", "memory"); + asm volatile(HFENCE_VVMA("zero", "%0") : : "r" (asid) : "memory"); =20 csr_write(CSR_HGATP, hgatp); } @@ -184,15 +106,8 @@ void kvm_riscv_local_hfence_vvma_gva(unsigned long vmi= d, hgatp =3D csr_swap(CSR_HGATP, vmid << HGATP_VMID_SHIFT); =20 for (pos =3D gva; pos < (gva + gvsz); pos +=3D BIT(order)) { - /* - * rs1 =3D a0 (GVA) - * rs2 =3D zero - * HFENCE.VVMA a0 - * 0010001 00000 01010 000 00000 1110011 - */ - asm volatile ("add a0, %0, zero\n" - ".word 0x22050073\n" - :: "r" (pos) : "a0", "memory"); + asm volatile(HFENCE_VVMA("%0", "zero") + : : "r" (pos) : "memory"); } =20 csr_write(CSR_HGATP, hgatp); @@ -204,13 +119,7 @@ void kvm_riscv_local_hfence_vvma_all(unsigned long vmi= d) =20 hgatp =3D csr_swap(CSR_HGATP, vmid << HGATP_VMID_SHIFT); =20 - /* - * rs1 =3D zero - * rs2 =3D zero - * HFENCE.VVMA - * 0010001 00000 00000 000 00000 1110011 - */ - asm volatile (".word 0x22000073" ::: "memory"); + asm volatile(HFENCE_VVMA("zero", "zero") : : : "memory"); =20 csr_write(CSR_HGATP, hgatp); } --=20 2.37.1