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[31.30.173.67]) by smtp.gmail.com with ESMTPSA id q15-20020a170906360f00b00730a73cbe08sm2383101ejb.169.2022.08.19.07.02.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Aug 2022 07:02:53 -0700 (PDT) From: Andrew Jones To: linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org Cc: linux-kernel@vger.kernel.org, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, anup@brainfault.org, mchitale@ventanamicro.com, heiko@sntech.de Subject: [PATCH 1/4] riscv: Add X register names to gpr-nums Date: Fri, 19 Aug 2022 16:02:47 +0200 Message-Id: <20220819140250.3892995-2-ajones@ventanamicro.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220819140250.3892995-1-ajones@ventanamicro.com> References: <20220819140250.3892995-1-ajones@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" When encoding instructions it's sometimes necessary to set a register field to a precise number. This is easiest to do using the x naming. Signed-off-by: Andrew Jones Reviewed-by: Anup Patel --- arch/riscv/include/asm/gpr-num.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/riscv/include/asm/gpr-num.h b/arch/riscv/include/asm/gpr-= num.h index dfee2829fc7c..efeb5edf8a3a 100644 --- a/arch/riscv/include/asm/gpr-num.h +++ b/arch/riscv/include/asm/gpr-num.h @@ -3,6 +3,11 @@ #define __ASM_GPR_NUM_H =20 #ifdef __ASSEMBLY__ + + .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24= ,25,26,27,28,29,30,31 + .equ .L__gpr_num_x\num, \num + .endr + .equ .L__gpr_num_zero, 0 .equ .L__gpr_num_ra, 1 .equ .L__gpr_num_sp, 2 @@ -39,6 +44,9 @@ #else /* __ASSEMBLY__ */ =20 #define __DEFINE_ASM_GPR_NUMS \ +" .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,2= 4,25,26,27,28,29,30,31\n" \ +" .equ .L__gpr_num_x\\num, \\num\n" \ +" .endr\n" \ " .equ .L__gpr_num_zero, 0\n" \ " .equ .L__gpr_num_ra, 1\n" \ " .equ .L__gpr_num_sp, 2\n" \ --=20 2.37.1 From nobody Wed Apr 8 12:10:59 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 51E65C32771 for ; Fri, 19 Aug 2022 14:03:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349181AbiHSODB (ORCPT ); Fri, 19 Aug 2022 10:03:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52336 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1349211AbiHSOC5 (ORCPT ); Fri, 19 Aug 2022 10:02:57 -0400 Received: from mail-ej1-x62c.google.com (mail-ej1-x62c.google.com [IPv6:2a00:1450:4864:20::62c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 763F1100F14 for ; Fri, 19 Aug 2022 07:02:56 -0700 (PDT) Received: by mail-ej1-x62c.google.com with SMTP id w19so8981851ejc.7 for ; Fri, 19 Aug 2022 07:02:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=CdNbn84TYwncfTBJxPnu/xlRdTtMM/NuV6HASL/Mh8E=; b=lCh+9pdG34gjrDI076GzFZVpx4/E/qseWgm+HgMbNq2MJQd10BIiZcZdGdBHg2oLKZ ISmjzidGOhYrdfOo6qHCZfYXuFcgY6XL2uMjXhIvjRYQY5iPjSyiQjXeGii7ikG5o7ht Z+tDTkMiBnbcfOGQ6iKUSxpBiEenHq0FTDRv3NZmCDv8q8vsrcM4JDnwTemeUHM3KcNi 56JMnKkv5L8w+1zEEjRpK9FEwGf6FmiaNHSG0AWQvK/SVPoGwCRzSbNZoBwVE9ch40IE O9focsaqJKTW1OZ7+nztPgHJMcBAVe516VIg0e+d3kZDVylLrPMggLO0DHkaj7fcbJpk +heQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=CdNbn84TYwncfTBJxPnu/xlRdTtMM/NuV6HASL/Mh8E=; b=wA8xtFZ8sYxrgGrWmwrmJJsWOrLOiXbP0MwHpFdDwrWl1DZVrteHl/XYbfCQIJoJg7 0zVueZ/qIxWA4eCI4VVJ6TFca6v7qaTO+kjsCzbkdTEH1nTYtPZYI5EZPhUeBCczQy2Z ZY50OvGIU/49pCRl28wsNGkLwvqhmjIji0zLvLjAUecTNWkQZlxJH/dFZlhVAkUMNGUE XGiPIp+t84wFT98l92M3sWFN56jAO93QOq+ScbS0m4TtQGFvmJn12nQu1q/Kt15+jcAP 5vOIqKVRRZO8DSMxoIZGGihbdId98coepW/6H2pznQwFfqSQ/wZWEFpSu1Mv2HUvwv0I HRZw== X-Gm-Message-State: ACgBeo1ZvAKt7qDeJGMXIXFaLTFiQcSLAIpntwBfEQG+fOlbxSPp3pQy WGpLB95xKnA2mETT0PaFDcbYBA== X-Google-Smtp-Source: AA6agR7kgjM4XbdNJobWB0KnpsIFG/X1o3vSDdu6NBsYc6JLV3lBrWSwPSJXqdHEA4IO0NWpQIhINQ== X-Received: by 2002:a17:906:93e8:b0:730:9e5c:b45a with SMTP id yl8-20020a17090693e800b007309e5cb45amr4819450ejb.530.1660917775017; Fri, 19 Aug 2022 07:02:55 -0700 (PDT) Received: from localhost (cst2-173-67.cust.vodafone.cz. [31.30.173.67]) by smtp.gmail.com with ESMTPSA id r17-20020aa7cfd1000000b0043ba7df7a42sm3147053edy.26.2022.08.19.07.02.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Aug 2022 07:02:54 -0700 (PDT) From: Andrew Jones To: linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org Cc: linux-kernel@vger.kernel.org, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, anup@brainfault.org, mchitale@ventanamicro.com, heiko@sntech.de Subject: [PATCH 2/4] riscv: Introduce support for defining instructions Date: Fri, 19 Aug 2022 16:02:48 +0200 Message-Id: <20220819140250.3892995-3-ajones@ventanamicro.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220819140250.3892995-1-ajones@ventanamicro.com> References: <20220819140250.3892995-1-ajones@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" When compiling with toolchains that haven't yet been taught about new instructions we need to encode them ourselves. Create a new file where support for instruction definitions will evolve. We initiate the file with a macro called INSN_R(), which implements the R-type instruction encoding. INSN_R() will use the assembler's .insn directive when available, which should give the assembler a chance to do some validation. When .insn is not available we fall back to manual encoding. Not only should using instruction encoding macros improve readability and maintainability of code over the alternative of inserting instructions directly (e.g. '.word 0xc0de'), but we should also gain potential for more optimized code after compilation because the compiler will have control over the input and output registers used. Signed-off-by: Andrew Jones Reviewed-by: Anup Patel --- arch/riscv/Kconfig | 3 ++ arch/riscv/include/asm/insn-def.h | 82 +++++++++++++++++++++++++++++++ 2 files changed, 85 insertions(+) create mode 100644 arch/riscv/include/asm/insn-def.h diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index ed66c31e4655..f8f3b316b838 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -227,6 +227,9 @@ config RISCV_DMA_NONCOHERENT select ARCH_HAS_SETUP_DMA_OPS select DMA_DIRECT_REMAP =20 +config AS_HAS_INSN + def_bool $(as-instr,.insn r 51$(comma) 0$(comma) 0$(comma) t0$(comma) t0$= (comma) zero) + source "arch/riscv/Kconfig.socs" source "arch/riscv/Kconfig.erratas" =20 diff --git a/arch/riscv/include/asm/insn-def.h b/arch/riscv/include/asm/ins= n-def.h new file mode 100644 index 000000000000..4cd0208068dd --- /dev/null +++ b/arch/riscv/include/asm/insn-def.h @@ -0,0 +1,82 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __ASM_INSN_DEF_H +#define __ASM_INSN_DEF_H +#include + +#define INSN_R_FUNC7_SHIFT 25 +#define INSN_R_RS2_SHIFT 20 +#define INSN_R_RS1_SHIFT 15 +#define INSN_R_FUNC3_SHIFT 12 +#define INSN_R_RD_SHIFT 7 +#define INSN_R_OPCODE_SHIFT 0 + +#ifdef __ASSEMBLY__ + +#ifdef CONFIG_AS_HAS_INSN + + .macro insn_r, opcode, func3, func7, rd, rs1, rs2 + .insn r \opcode, \func3, \func7, \rd, \rs1, \rs2 + .endm + +#else + +#include + + .macro insn_r, opcode, func3, func7, rd, rs1, rs2 + .4byte ((\opcode << INSN_R_OPCODE_SHIFT) | \ + (\func3 << INSN_R_FUNC3_SHIFT) | \ + (\func7 << INSN_R_FUNC7_SHIFT) | \ + (.L__gpr_num_\rd << INSN_R_RD_SHIFT) | \ + (.L__gpr_num_\rs1 << INSN_R_RS1_SHIFT) | \ + (.L__gpr_num_\rs2 << INSN_R_RS2_SHIFT)) + .endm + +#endif + +#define INSN_R(...) insn_r __VA_ARGS__ + +#else /* ! __ASSEMBLY__ */ + +#ifdef CONFIG_AS_HAS_INSN + +#define INSN_R(opcode, func3, func7, rd, rs1, rs2) \ + ".insn r " opcode ", " func3 ", " func7 ", " rd ", " rs1 ", " rs2 "\n" + +#else + +#include +#include + +#define DEFINE_INSN_R \ + __DEFINE_ASM_GPR_NUMS \ +" .macro insn_r, opcode, func3, func7, rd, rs1, rs2\n" \ +" .4byte ((\\opcode << " __stringify(INSN_R_OPCODE_SHIFT) ") |" \ +" (\\func3 << " __stringify(INSN_R_FUNC3_SHIFT) ") |" \ +" (\\func7 << " __stringify(INSN_R_FUNC7_SHIFT) ") |" \ +" (.L__gpr_num_\\rd << " __stringify(INSN_R_RD_SHIFT) ") |" \ +" (.L__gpr_num_\\rs1 << " __stringify(INSN_R_RS1_SHIFT) ") |" \ +" (.L__gpr_num_\\rs2 << " __stringify(INSN_R_RS2_SHIFT) "))\n" \ +" .endm\n" + +#define UNDEFINE_INSN_R \ +" .purgem insn_r\n" + +#define INSN_R(opcode, func3, func7, rd, rs1, rs2) \ + DEFINE_INSN_R \ + "insn_r " opcode ", " func3 ", " func7 ", " rd ", " rs1 ", " rs2 "\n" \ + UNDEFINE_INSN_R + +#endif + +#endif /* ! __ASSEMBLY__ */ + +#define OPCODE(v) __ASM_STR(v) +#define FUNC3(v) __ASM_STR(v) +#define FUNC7(v) __ASM_STR(v) +#define __REG(v) __ASM_STR(x ## v) +#define RD(v) __REG(v) +#define RS1(v) __REG(v) +#define RS2(v) __REG(v) + +#endif /* __ASM_INSN_DEF_H */ --=20 2.37.1 From nobody Wed Apr 8 12:10:59 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 536ECC32773 for ; Fri, 19 Aug 2022 14:03:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349331AbiHSODH (ORCPT ); Fri, 19 Aug 2022 10:03:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52348 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1349328AbiHSOC7 (ORCPT ); Fri, 19 Aug 2022 10:02:59 -0400 Received: from mail-ed1-x52f.google.com (mail-ed1-x52f.google.com [IPv6:2a00:1450:4864:20::52f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E0EEE100F0E for ; Fri, 19 Aug 2022 07:02:57 -0700 (PDT) Received: by mail-ed1-x52f.google.com with SMTP id s11so5760038edd.13 for ; Fri, 19 Aug 2022 07:02:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=eHs+z8DwNs709gkux1J21T7x+ZKZRefKINTUPP0jqqE=; b=MiVkDd4ypsClXPfrJblJPX1o05V2XlMgkABPNa+ANz5bpPHj3bz+KUWKPLbj4eMh2e Rf+Yfig8Yqutna/Gl1ZlvDAYMbONm2a1faNbFHIgth+0jnO5iCoOoiGUO2cdhbMbPcoX NMC2DiHTYwuBlGQ0fm+hNXHeNI+FOZwopJW5bb9kQ/vLNIsHRnM3VsLkUoUfyPkguFPn DdTu45vwCCHA2KHOEW12+Ilk7iklf/ig1tuAmHI2WDQHVgWZwZRBHOq+P9Rx6AdrUeSA /uUw748nFBk8M/HHgh89LcniBs/ZOywQ1MUrAVWqnhGA8R57j5Uu3Etgfl+IUxWQLBCC crfQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=eHs+z8DwNs709gkux1J21T7x+ZKZRefKINTUPP0jqqE=; b=F16PfevaaFS1p57HJl4m9zhnjgpJ/BH+ZEPhh4kRV4/C1z49fpO7Tlrez+WH3BcSix z71Ads+AgOf49tjJ70H/2CEGz4dSQJf2rqpA2/X0UCPI7T+lNUTQNWaMbFKZAYyJtUsg Dl6HQyecAV/wZS+dZ0oUV16dE2Trc0ebVvL89jHmTn9Om5b5/6cGcURL3nB59o2EhNZ8 7g4HQtZyMwHgCBXe48VUNgfGi+h+2PCyX2ykn1BtsBw8IANPwG/UTtLSBMqpi4aK4nDu 3OTCOwTQdeslIaxE3KVv+XyTVKJKj5lUSZpyKx+yqL4WSUXzDbqgn61cFSXL3UPetgS3 V1AQ== X-Gm-Message-State: ACgBeo28MKf7vVU8ouH8nJAYB2UkYI105XtJBE33CLFiPwMeFP65v3xE JGtQ0o2vd/rUraDOFOhyo+22fQ== X-Google-Smtp-Source: AA6agR63VI1qC3a/Avg6iK+EkZbCELYZLImNqOEsToeYNls3s6oXmzXpKEmehFYJbdsLBfBuKZi0RQ== X-Received: by 2002:a05:6402:1044:b0:446:27c1:49a4 with SMTP id e4-20020a056402104400b0044627c149a4mr4331991edu.53.1660917776492; Fri, 19 Aug 2022 07:02:56 -0700 (PDT) Received: from localhost (cst2-173-67.cust.vodafone.cz. [31.30.173.67]) by smtp.gmail.com with ESMTPSA id b9-20020a17090630c900b0073c9d68ca0dsm1434287ejb.133.2022.08.19.07.02.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Aug 2022 07:02:56 -0700 (PDT) From: Andrew Jones To: linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org Cc: linux-kernel@vger.kernel.org, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, anup@brainfault.org, mchitale@ventanamicro.com, heiko@sntech.de Subject: [PATCH 3/4] riscv: KVM: Apply insn-def to hfence encodings Date: Fri, 19 Aug 2022 16:02:49 +0200 Message-Id: <20220819140250.3892995-4-ajones@ventanamicro.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220819140250.3892995-1-ajones@ventanamicro.com> References: <20220819140250.3892995-1-ajones@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Introduce hfence instruction encodings and apply them to KVM's use. With the self-documenting nature of the instruction encoding macros, and a spec always within arm's reach, it's safe to remove the comments, so we do that too. Signed-off-by: Andrew Jones Reviewed-by: Anup Patel --- arch/riscv/include/asm/insn-def.h | 8 ++ arch/riscv/kvm/tlb.c | 117 ++++-------------------------- 2 files changed, 21 insertions(+), 104 deletions(-) diff --git a/arch/riscv/include/asm/insn-def.h b/arch/riscv/include/asm/ins= n-def.h index 4cd0208068dd..cd1c0d365f47 100644 --- a/arch/riscv/include/asm/insn-def.h +++ b/arch/riscv/include/asm/insn-def.h @@ -79,4 +79,12 @@ #define RS1(v) __REG(v) #define RS2(v) __REG(v) =20 +#define OPCODE_SYSTEM OPCODE(115) + +#define HFENCE_VVMA(vaddr, asid) \ + INSN_R(OPCODE_SYSTEM, FUNC3(0), FUNC7(17), RD(0), vaddr, asid) + +#define HFENCE_GVMA(gaddr, vmid) \ + INSN_R(OPCODE_SYSTEM, FUNC3(0), FUNC7(49), RD(0), gaddr, vmid) + #endif /* __ASM_INSN_DEF_H */ diff --git a/arch/riscv/kvm/tlb.c b/arch/riscv/kvm/tlb.c index 1a76d0b1907d..f742a0d888e1 100644 --- a/arch/riscv/kvm/tlb.c +++ b/arch/riscv/kvm/tlb.c @@ -12,22 +12,7 @@ #include #include #include - -/* - * Instruction encoding of hfence.gvma is: - * HFENCE.GVMA rs1, rs2 - * HFENCE.GVMA zero, rs2 - * HFENCE.GVMA rs1 - * HFENCE.GVMA - * - * rs1!=3Dzero and rs2!=3Dzero =3D=3D> HFENCE.GVMA rs1, rs2 - * rs1=3D=3Dzero and rs2!=3Dzero =3D=3D> HFENCE.GVMA zero, rs2 - * rs1!=3Dzero and rs2=3D=3Dzero =3D=3D> HFENCE.GVMA rs1 - * rs1=3D=3Dzero and rs2=3D=3Dzero =3D=3D> HFENCE.GVMA - * - * Instruction encoding of HFENCE.GVMA is: - * 0110001 rs2(5) rs1(5) 000 00000 1110011 - */ +#include =20 void kvm_riscv_local_hfence_gvma_vmid_gpa(unsigned long vmid, gpa_t gpa, gpa_t gpsz, @@ -41,31 +26,14 @@ void kvm_riscv_local_hfence_gvma_vmid_gpa(unsigned long= vmid, } =20 for (pos =3D gpa; pos < (gpa + gpsz); pos +=3D BIT(order)) { - /* - * rs1 =3D a0 (GPA >> 2) - * rs2 =3D a1 (VMID) - * HFENCE.GVMA a0, a1 - * 0110001 01011 01010 000 00000 1110011 - */ - asm volatile ("srli a0, %0, 2\n" - "add a1, %1, zero\n" - ".word 0x62b50073\n" - :: "r" (pos), "r" (vmid) - : "a0", "a1", "memory"); + asm volatile (HFENCE_GVMA("%0", "%1") + : : "r" (pos >> 2), "r" (vmid) : "memory"); } } =20 void kvm_riscv_local_hfence_gvma_vmid_all(unsigned long vmid) { - /* - * rs1 =3D zero - * rs2 =3D a0 (VMID) - * HFENCE.GVMA zero, a0 - * 0110001 01010 00000 000 00000 1110011 - */ - asm volatile ("add a0, %0, zero\n" - ".word 0x62a00073\n" - :: "r" (vmid) : "a0", "memory"); + asm volatile(HFENCE_GVMA("zero", "%0") : : "r" (vmid) : "memory"); } =20 void kvm_riscv_local_hfence_gvma_gpa(gpa_t gpa, gpa_t gpsz, @@ -79,45 +47,16 @@ void kvm_riscv_local_hfence_gvma_gpa(gpa_t gpa, gpa_t g= psz, } =20 for (pos =3D gpa; pos < (gpa + gpsz); pos +=3D BIT(order)) { - /* - * rs1 =3D a0 (GPA >> 2) - * rs2 =3D zero - * HFENCE.GVMA a0 - * 0110001 00000 01010 000 00000 1110011 - */ - asm volatile ("srli a0, %0, 2\n" - ".word 0x62050073\n" - :: "r" (pos) : "a0", "memory"); + asm volatile(HFENCE_GVMA("%0", "zero") + : : "r" (pos >> 2) : "memory"); } } =20 void kvm_riscv_local_hfence_gvma_all(void) { - /* - * rs1 =3D zero - * rs2 =3D zero - * HFENCE.GVMA - * 0110001 00000 00000 000 00000 1110011 - */ - asm volatile (".word 0x62000073" ::: "memory"); + asm volatile(HFENCE_GVMA("zero", "zero") : : : "memory"); } =20 -/* - * Instruction encoding of hfence.gvma is: - * HFENCE.VVMA rs1, rs2 - * HFENCE.VVMA zero, rs2 - * HFENCE.VVMA rs1 - * HFENCE.VVMA - * - * rs1!=3Dzero and rs2!=3Dzero =3D=3D> HFENCE.VVMA rs1, rs2 - * rs1=3D=3Dzero and rs2!=3Dzero =3D=3D> HFENCE.VVMA zero, rs2 - * rs1!=3Dzero and rs2=3D=3Dzero =3D=3D> HFENCE.VVMA rs1 - * rs1=3D=3Dzero and rs2=3D=3Dzero =3D=3D> HFENCE.VVMA - * - * Instruction encoding of HFENCE.VVMA is: - * 0010001 rs2(5) rs1(5) 000 00000 1110011 - */ - void kvm_riscv_local_hfence_vvma_asid_gva(unsigned long vmid, unsigned long asid, unsigned long gva, @@ -134,17 +73,8 @@ void kvm_riscv_local_hfence_vvma_asid_gva(unsigned long= vmid, hgatp =3D csr_swap(CSR_HGATP, vmid << HGATP_VMID_SHIFT); =20 for (pos =3D gva; pos < (gva + gvsz); pos +=3D BIT(order)) { - /* - * rs1 =3D a0 (GVA) - * rs2 =3D a1 (ASID) - * HFENCE.VVMA a0, a1 - * 0010001 01011 01010 000 00000 1110011 - */ - asm volatile ("add a0, %0, zero\n" - "add a1, %1, zero\n" - ".word 0x22b50073\n" - :: "r" (pos), "r" (asid) - : "a0", "a1", "memory"); + asm volatile(HFENCE_VVMA("%0", "%1") + : : "r" (pos), "r" (asid) : "memory"); } =20 csr_write(CSR_HGATP, hgatp); @@ -157,15 +87,7 @@ void kvm_riscv_local_hfence_vvma_asid_all(unsigned long= vmid, =20 hgatp =3D csr_swap(CSR_HGATP, vmid << HGATP_VMID_SHIFT); =20 - /* - * rs1 =3D zero - * rs2 =3D a0 (ASID) - * HFENCE.VVMA zero, a0 - * 0010001 01010 00000 000 00000 1110011 - */ - asm volatile ("add a0, %0, zero\n" - ".word 0x22a00073\n" - :: "r" (asid) : "a0", "memory"); + asm volatile(HFENCE_VVMA("zero", "%0") : : "r" (asid) : "memory"); =20 csr_write(CSR_HGATP, hgatp); } @@ -184,15 +106,8 @@ void kvm_riscv_local_hfence_vvma_gva(unsigned long vmi= d, hgatp =3D csr_swap(CSR_HGATP, vmid << HGATP_VMID_SHIFT); =20 for (pos =3D gva; pos < (gva + gvsz); pos +=3D BIT(order)) { - /* - * rs1 =3D a0 (GVA) - * rs2 =3D zero - * HFENCE.VVMA a0 - * 0010001 00000 01010 000 00000 1110011 - */ - asm volatile ("add a0, %0, zero\n" - ".word 0x22050073\n" - :: "r" (pos) : "a0", "memory"); + asm volatile(HFENCE_VVMA("%0", "zero") + : : "r" (pos) : "memory"); } =20 csr_write(CSR_HGATP, hgatp); @@ -204,13 +119,7 @@ void kvm_riscv_local_hfence_vvma_all(unsigned long vmi= d) =20 hgatp =3D csr_swap(CSR_HGATP, vmid << HGATP_VMID_SHIFT); =20 - /* - * rs1 =3D zero - * rs2 =3D zero - * HFENCE.VVMA - * 0010001 00000 00000 000 00000 1110011 - */ - asm volatile (".word 0x22000073" ::: "memory"); + asm volatile(HFENCE_VVMA("zero", "zero") : : : "memory"); =20 csr_write(CSR_HGATP, hgatp); } --=20 2.37.1 From nobody Wed Apr 8 12:10:59 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A2C8FC32771 for ; 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[31.30.173.67]) by smtp.gmail.com with ESMTPSA id p4-20020a17090653c400b0073bdb2f6f28sm2271393ejo.217.2022.08.19.07.02.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Aug 2022 07:02:57 -0700 (PDT) From: Andrew Jones To: linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org Cc: linux-kernel@vger.kernel.org, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, anup@brainfault.org, mchitale@ventanamicro.com, heiko@sntech.de Subject: [PATCH 4/4] riscv: KVM: Apply insn-def to hlv encodings Date: Fri, 19 Aug 2022 16:02:50 +0200 Message-Id: <20220819140250.3892995-5-ajones@ventanamicro.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220819140250.3892995-1-ajones@ventanamicro.com> References: <20220819140250.3892995-1-ajones@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Introduce hlv instruction encodings and apply them to KVM's use. We're careful not to introduce hlv.d to 32-bit builds. Indeed, we ensure the build fails if someone tries to use it. Signed-off-by: Andrew Jones Reviewed-by: Anup Patel --- arch/riscv/include/asm/insn-def.h | 14 ++++++++++++++ arch/riscv/kvm/vcpu_exit.c | 29 +++++------------------------ 2 files changed, 19 insertions(+), 24 deletions(-) diff --git a/arch/riscv/include/asm/insn-def.h b/arch/riscv/include/asm/ins= n-def.h index cd1c0d365f47..c66d5745c5b4 100644 --- a/arch/riscv/include/asm/insn-def.h +++ b/arch/riscv/include/asm/insn-def.h @@ -87,4 +87,18 @@ #define HFENCE_GVMA(gaddr, vmid) \ INSN_R(OPCODE_SYSTEM, FUNC3(0), FUNC7(49), RD(0), gaddr, vmid) =20 +#define HLVX_HU(dest, addr) \ + INSN_R(OPCODE_SYSTEM, FUNC3(4), FUNC7(50), dest, addr, RS2(3)) + +#define HLV_W(dest, addr) \ + INSN_R(OPCODE_SYSTEM, FUNC3(4), FUNC7(52), dest, addr, RS2(0)) + +#ifdef CONFIG_64BIT +#define HLV_D(dest, addr) \ + INSN_R(OPCODE_SYSTEM, FUNC3(4), FUNC7(54), dest, addr, RS2(0)) +#else +#define HLV_D(dest, addr) \ + __ASM_STR(.error "hlv.d requires 64-bit support") +#endif + #endif /* __ASM_INSN_DEF_H */ diff --git a/arch/riscv/kvm/vcpu_exit.c b/arch/riscv/kvm/vcpu_exit.c index d5c36386878a..9cb075e72799 100644 --- a/arch/riscv/kvm/vcpu_exit.c +++ b/arch/riscv/kvm/vcpu_exit.c @@ -8,6 +8,7 @@ =20 #include #include +#include =20 static int gstage_page_fault(struct kvm_vcpu *vcpu, struct kvm_run *run, struct kvm_cpu_trap *trap) @@ -82,22 +83,12 @@ unsigned long kvm_riscv_vcpu_unpriv_read(struct kvm_vcp= u *vcpu, ".option push\n" ".option norvc\n" "add %[ttmp], %[taddr], 0\n" - /* - * HLVX.HU %[val], (%[addr]) - * HLVX.HU t0, (t2) - * 0110010 00011 00111 100 00101 1110011 - */ - ".word 0x6433c2f3\n" + HLVX_HU("%[val]", "%[addr]") "andi %[tmp], %[val], 3\n" "addi %[tmp], %[tmp], -3\n" "bne %[tmp], zero, 2f\n" "addi %[addr], %[addr], 2\n" - /* - * HLVX.HU %[tmp], (%[addr]) - * HLVX.HU t1, (t2) - * 0110010 00011 00111 100 00110 1110011 - */ - ".word 0x6433c373\n" + HLVX_HU("%[tmp]", "%[addr]") "sll %[tmp], %[tmp], 16\n" "add %[val], %[val], %[tmp]\n" "2:\n" @@ -121,19 +112,9 @@ unsigned long kvm_riscv_vcpu_unpriv_read(struct kvm_vc= pu *vcpu, ".option norvc\n" "add %[ttmp], %[taddr], 0\n" #ifdef CONFIG_64BIT - /* - * HLV.D %[val], (%[addr]) - * HLV.D t0, (t2) - * 0110110 00000 00111 100 00101 1110011 - */ - ".word 0x6c03c2f3\n" + HLV_D("%[val]", "%[addr]") #else - /* - * HLV.W %[val], (%[addr]) - * HLV.W t0, (t2) - * 0110100 00000 00111 100 00101 1110011 - */ - ".word 0x6803c2f3\n" + HLV_W("%[val]", "%[addr]") #endif ".option pop" : [val] "=3D&r" (val), --=20 2.37.1