From nobody Fri Apr 10 21:55:16 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AF806C00140 for ; Thu, 18 Aug 2022 16:50:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345055AbiHRQun (ORCPT ); Thu, 18 Aug 2022 12:50:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45404 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345087AbiHRQuW (ORCPT ); Thu, 18 Aug 2022 12:50:22 -0400 Received: from NAM11-CO1-obe.outbound.protection.outlook.com (mail-co1nam11on2042.outbound.protection.outlook.com [40.107.220.42]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0F2BADFC8 for ; Thu, 18 Aug 2022 09:50:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Tkf27MGOsfSl3o4nlKMoQt4JG5ecK3TGGftAu2UEBHc7BaLAgedrVnvUUpPoGYpBy2QfZ/woWXKH8pZPk5Q//wBnVBzAyu9qJXZ/npMevp6WNdGZkGB1Tp8yqJkjGta2hKLiKxUJuYYToWgH56mz14bsegS1b6yZwGK8s0amPSTa9FybBAA8fAroPI/oqLP8ixRZVNV3yiqrTtQ9HSkr31dd1c6X8KoblCE/V1EXIWLZe2ysYLcMccCNHZJEgSVl5hxUO7yClu3tf8/xMYL7Iu1BcnMA/rJSDx0uFhkQiVzFykVx/5ab00yc/ciBhfrj/azNPt/pl/6CCijPFoz7Dw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=PjcZNZoSSnwPw2aU/t2SfKERFw+eYc/AXI0WutQOFXQ=; b=E+Z12DmY/2A8xhMkVNzqlqpUoLAbiv7IN7c9pzWH+uqjQgaKZFUbLhCzUzsGUDSIjkR0aydprrrV3eF/OUJFlVaou7tEAkvCKhx3tlLf3D//oXLeaDk5pviNz00M4/s0CG99CJcIv61w1Q7dsPMIoDma54lU20kg+HdYdWHkMpROZO8+KgTN5B3r/EdaA17vsyD0QE6Vl3Hwcco9gaJhwL/DjRrxkq4+d8X2NxPy9fGOy7I5CGu7XDocNZjcuBT1yUQZfSo2anBAK0bR/cvpwbO/fQgGTMJplbE/VnuEvv7REAtHgnR6UOSx3BE/JL2+kFjgfSot7r0Mx7bWm0Ynmg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=vger.kernel.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=PjcZNZoSSnwPw2aU/t2SfKERFw+eYc/AXI0WutQOFXQ=; b=15Z9dddzz6CGsO5pokvDJn2yrTGn6Jd0tRCBBE167dTGLcqCHFC0LRqYKZFhuCtvEFDwyz5HO4si2KAzqSBarkAppbbUjDY3GcJfghznv6PT3ZSr19DEs+mrfuZx2wjqZArcWYYNMiiZslvmGdW8dnOZ7e7kRVxwTFFxhg8cDL8= Received: from DS7PR05CA0057.namprd05.prod.outlook.com (2603:10b6:8:2f::21) by MN2PR12MB3022.namprd12.prod.outlook.com (2603:10b6:208:ce::32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5525.10; Thu, 18 Aug 2022 16:49:56 +0000 Received: from DM6NAM11FT066.eop-nam11.prod.protection.outlook.com (2603:10b6:8:2f:cafe::34) by DS7PR05CA0057.outlook.office365.com (2603:10b6:8:2f::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5566.4 via Frontend Transport; Thu, 18 Aug 2022 16:49:55 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DM6NAM11FT066.mail.protection.outlook.com (10.13.173.179) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5546.15 via Frontend Transport; Thu, 18 Aug 2022 16:49:55 +0000 Received: from hamza-pc.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.28; Thu, 18 Aug 2022 11:49:53 -0500 From: Hamza Mahfooz To: CC: Nathan Chancellor , Hamza Mahfooz , Harry Wentland , Leo Li , Rodrigo Siqueira , "Alex Deucher" , =?UTF-8?q?Christian=20K=C3=B6nig?= , "Pan, Xinhui" , David Airlie , Daniel Vetter , Aurabindo Pillai , =?UTF-8?q?Ma=C3=ADra=20Canal?= , =?UTF-8?q?Andr=C3=A9=20Almeida?= , Bing Guo , Nicholas Kazlauskas , , Subject: [PATCH] drm/amd/display: fix i386 frame size warning Date: Thu, 18 Aug 2022 12:48:47 -0400 Message-ID: <20220818164848.68729-1-hamza.mahfooz@amd.com> X-Mailer: git-send-email 2.37.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 107670bc-3afd-46ac-68f4-08da8139ae05 X-MS-TrafficTypeDiagnostic: MN2PR12MB3022:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: w3zIfZ2Z36pVV00KOzl8/hfUVfmPpn+kPRSOwPwxUfO0p06wiA7Zc5zzpfbycXUDPB3vL5SDWdGkpzUErfeRJSheu8LaQTexwcjzBuZYmt7trkUM3DAJd/i17ZXhMB5xJ86e6RJjro4jxF2cr/IFP6nGrgKzfDfEpp0j2hHbbcfhEdmlKwf6SxRyrT3iT4BbsFiuRo6MUhmawItVT9tIUYqpolw13IYF4AsNLHMaRPSUKF5aLT8QdSzPDmL4zryKGjfEo4RGo0noI2LTBx3lJRA4o3Wae+FuulzJGSzv7llnwcXhvYyjUyxK+qo7up5A/MlddTB4YHIqgAWZMcIAn9H4a8EeUThpkLK3cNviO5C3EdCpRqE0A88BQBl+dX0J8XAucjovXmCs9uc5JtI9l0IK3bXAqAZFd3RNq9kBv/pcrTHLXD6vxr4aywqExMqOcT/0SkxXJeZpOxwYHg/f3DvXwF9GsQ273qyYxxDHpJAacwxliw820FNDaO6e8EbNxloMoLNIwbA47bz2H6pW/ambcNCJzrdkHzzpaDt/FdExr73lbES1UIh/Pw6fOkCF72vxG06wNbPRawLC9zq2JoX9ePrfeSGV7h8o0zGFsX7c9sWyZQvCaxIIVaKt/fm3F6aGPkqgKMeNr1q2VJy5DqdnzZcp/kuekPEI180DxFFtLbRD02hDjR9lIkNwCkF8yK7Z4I7CMhqLOzt7GUvXEVUp3ycKgGQIaGVefj8rUo0xmcKkahf3fEO7XMqIX9gi+SUDWMzYjAhPjPFBMRFCbyEtF//iRhTbKLRGVoZThUJO2/e/8VZeVFtfHMSy1btY6ZlRuYps8DPjJdWJR3PnsdULUuNSPgOj6iyi9IImKDU= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230016)(4636009)(376002)(346002)(396003)(39860400002)(136003)(36840700001)(40470700004)(46966006)(426003)(8676002)(356005)(7696005)(36756003)(47076005)(83380400001)(36860700001)(82740400003)(6916009)(82310400005)(40460700003)(54906003)(1076003)(19627235002)(40480700001)(478600001)(26005)(336012)(186003)(6666004)(316002)(41300700001)(16526019)(2616005)(81166007)(30864003)(2906002)(44832011)(86362001)(4326008)(5660300002)(70206006)(8936002)(70586007)(36900700001)(16060500005)(44824005);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Aug 2022 16:49:55.8118 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 107670bc-3afd-46ac-68f4-08da8139ae05 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT066.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB3022 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Addresses the following warning: drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn30/display_mode_vba_30.c:35= 96:6: error: stack frame size (2092) exceeds limit (2048) in 'dml30_ModeSup= portAndSystemConfigurationFull' [-Werror,-Wframe-larger-than] void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *m= ode_lib) ^ UseMinimumDCFCLK() is eating away at dml30_ModeSupportAndSystemConfigurationFull()'s stack space, so use a pointer to struct vba_vars_st instead of passing lots of large arrays as parameters by value. Signed-off-by: Hamza Mahfooz Reviewed-by: Aurabindo Pillai --- .../dc/dml/dcn30/display_mode_vba_30.c | 295 ++++-------------- 1 file changed, 63 insertions(+), 232 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c= b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c index 876b321b30ca..b7fa003ffe06 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c @@ -396,64 +396,10 @@ static void CalculateUrgentBurstFactor( =20 static void UseMinimumDCFCLK( struct display_mode_lib *mode_lib, - int MaxInterDCNTileRepeaters, + struct vba_vars_st *v, int MaxPrefetchMode, - double FinalDRAMClockChangeLatency, - double SREnterPlusExitTime, - int ReturnBusWidth, - int RoundTripPingLatencyCycles, - int ReorderingBytes, - int PixelChunkSizeInKByte, - int MetaChunkSize, - bool GPUVMEnable, - int GPUVMMaxPageTableLevels, - bool HostVMEnable, - int NumberOfActivePlanes, - double HostVMMinPageSize, - int HostVMMaxNonCachedPageTableLevels, - bool DynamicMetadataVMEnabled, - enum immediate_flip_requirement ImmediateFlipRequirement, - bool ProgressiveToInterlaceUnitInOPP, - double MaxAveragePercentOfIdealSDPPortBWDisplayCanUseInNormalSystemOpera= tion, - double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelM= ixedWithVMData, - double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMData= Only, - double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelD= ataOnly, - int VTotal[], - int VActive[], - int DynamicMetadataTransmittedBytes[], - int DynamicMetadataLinesBeforeActiveRequired[], - bool Interlace[], - double RequiredDPPCLK[][2][DC__NUM_DPP__MAX], - double RequiredDISPCLK[][2], - double UrgLatency[], - unsigned int NoOfDPP[][2][DC__NUM_DPP__MAX], - double ProjectedDCFCLKDeepSleep[][2], - double MaximumVStartup[][2][DC__NUM_DPP__MAX], - double TotalVActivePixelBandwidth[][2], - double TotalVActiveCursorBandwidth[][2], - double TotalMetaRowBandwidth[][2], - double TotalDPTERowBandwidth[][2], - unsigned int TotalNumberOfActiveDPP[][2], - unsigned int TotalNumberOfDCCActiveDPP[][2], - int dpte_group_bytes[], - double PrefetchLinesY[][2][DC__NUM_DPP__MAX], - double PrefetchLinesC[][2][DC__NUM_DPP__MAX], - unsigned int swath_width_luma_ub_all_states[][2][DC__NUM_DPP__MAX], - unsigned int swath_width_chroma_ub_all_states[][2][DC__NUM_DPP__MAX], - int BytePerPixelY[], - int BytePerPixelC[], - int HTotal[], - double PixelClock[], - double PDEAndMetaPTEBytesPerFrame[][2][DC__NUM_DPP__MAX], - double DPTEBytesPerRow[][2][DC__NUM_DPP__MAX], - double MetaRowBytes[][2][DC__NUM_DPP__MAX], - bool DynamicMetadataEnable[], - double VActivePixelBandwidth[][2][DC__NUM_DPP__MAX], - double VActiveCursorBandwidth[][2][DC__NUM_DPP__MAX], - double ReadBandwidthLuma[], - double ReadBandwidthChroma[], - double DCFCLKPerState[], - double DCFCLKState[][2]); + int ReorderingBytes); + static void CalculatePixelDeliveryTimes( unsigned int NumberOfActivePlanes, double VRatio[], @@ -4692,66 +4638,7 @@ void dml30_ModeSupportAndSystemConfigurationFull(str= uct display_mode_lib *mode_l } =20 if (v->UseMinimumRequiredDCFCLK =3D=3D true) { - UseMinimumDCFCLK( - mode_lib, - v->MaxInterDCNTileRepeaters, - MaxPrefetchMode, - v->FinalDRAMClockChangeLatency, - v->SREnterPlusExitTime, - v->ReturnBusWidth, - v->RoundTripPingLatencyCycles, - ReorderingBytes, - v->PixelChunkSizeInKByte, - v->MetaChunkSize, - v->GPUVMEnable, - v->GPUVMMaxPageTableLevels, - v->HostVMEnable, - v->NumberOfActivePlanes, - v->HostVMMinPageSize, - v->HostVMMaxNonCachedPageTableLevels, - v->DynamicMetadataVMEnabled, - v->ImmediateFlipRequirement[0], - v->ProgressiveToInterlaceUnitInOPP, - v->MaxAveragePercentOfIdealSDPPortBWDisplayCanUseInNormalSystemOperati= on, - v->PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMix= edWithVMData, - v->PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOn= ly, - v->PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelDat= aOnly, - v->VTotal, - v->VActive, - v->DynamicMetadataTransmittedBytes, - v->DynamicMetadataLinesBeforeActiveRequired, - v->Interlace, - v->RequiredDPPCLK, - v->RequiredDISPCLK, - v->UrgLatency, - v->NoOfDPP, - v->ProjectedDCFCLKDeepSleep, - v->MaximumVStartup, - v->TotalVActivePixelBandwidth, - v->TotalVActiveCursorBandwidth, - v->TotalMetaRowBandwidth, - v->TotalDPTERowBandwidth, - v->TotalNumberOfActiveDPP, - v->TotalNumberOfDCCActiveDPP, - v->dpte_group_bytes, - v->PrefetchLinesY, - v->PrefetchLinesC, - v->swath_width_luma_ub_all_states, - v->swath_width_chroma_ub_all_states, - v->BytePerPixelY, - v->BytePerPixelC, - v->HTotal, - v->PixelClock, - v->PDEAndMetaPTEBytesPerFrame, - v->DPTEBytesPerRow, - v->MetaRowBytes, - v->DynamicMetadataEnable, - v->VActivePixelBandwidth, - v->VActiveCursorBandwidth, - v->ReadBandwidthLuma, - v->ReadBandwidthChroma, - v->DCFCLKPerState, - v->DCFCLKState); + UseMinimumDCFCLK(mode_lib, v, MaxPrefetchMode, ReorderingBytes); =20 if (v->ClampMinDCFCLK) { /* Clamp calculated values to actual minimum */ @@ -6610,77 +6497,21 @@ static double CalculateUrgentLatency( return ret; } =20 - static void UseMinimumDCFCLK( struct display_mode_lib *mode_lib, - int MaxInterDCNTileRepeaters, + struct vba_vars_st *v, int MaxPrefetchMode, - double FinalDRAMClockChangeLatency, - double SREnterPlusExitTime, - int ReturnBusWidth, - int RoundTripPingLatencyCycles, - int ReorderingBytes, - int PixelChunkSizeInKByte, - int MetaChunkSize, - bool GPUVMEnable, - int GPUVMMaxPageTableLevels, - bool HostVMEnable, - int NumberOfActivePlanes, - double HostVMMinPageSize, - int HostVMMaxNonCachedPageTableLevels, - bool DynamicMetadataVMEnabled, - enum immediate_flip_requirement ImmediateFlipRequirement, - bool ProgressiveToInterlaceUnitInOPP, - double MaxAveragePercentOfIdealSDPPortBWDisplayCanUseInNormalSystemOpera= tion, - double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelM= ixedWithVMData, - double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMData= Only, - double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelD= ataOnly, - int VTotal[], - int VActive[], - int DynamicMetadataTransmittedBytes[], - int DynamicMetadataLinesBeforeActiveRequired[], - bool Interlace[], - double RequiredDPPCLK[][2][DC__NUM_DPP__MAX], - double RequiredDISPCLK[][2], - double UrgLatency[], - unsigned int NoOfDPP[][2][DC__NUM_DPP__MAX], - double ProjectedDCFCLKDeepSleep[][2], - double MaximumVStartup[][2][DC__NUM_DPP__MAX], - double TotalVActivePixelBandwidth[][2], - double TotalVActiveCursorBandwidth[][2], - double TotalMetaRowBandwidth[][2], - double TotalDPTERowBandwidth[][2], - unsigned int TotalNumberOfActiveDPP[][2], - unsigned int TotalNumberOfDCCActiveDPP[][2], - int dpte_group_bytes[], - double PrefetchLinesY[][2][DC__NUM_DPP__MAX], - double PrefetchLinesC[][2][DC__NUM_DPP__MAX], - unsigned int swath_width_luma_ub_all_states[][2][DC__NUM_DPP__MAX], - unsigned int swath_width_chroma_ub_all_states[][2][DC__NUM_DPP__MAX], - int BytePerPixelY[], - int BytePerPixelC[], - int HTotal[], - double PixelClock[], - double PDEAndMetaPTEBytesPerFrame[][2][DC__NUM_DPP__MAX], - double DPTEBytesPerRow[][2][DC__NUM_DPP__MAX], - double MetaRowBytes[][2][DC__NUM_DPP__MAX], - bool DynamicMetadataEnable[], - double VActivePixelBandwidth[][2][DC__NUM_DPP__MAX], - double VActiveCursorBandwidth[][2][DC__NUM_DPP__MAX], - double ReadBandwidthLuma[], - double ReadBandwidthChroma[], - double DCFCLKPerState[], - double DCFCLKState[][2]) + int ReorderingBytes) { double NormalEfficiency =3D 0; double PTEEfficiency =3D 0; double TotalMaxPrefetchFlipDPTERowBandwidth[DC__VOLTAGE_STATES][2] =3D = { { 0 } }; unsigned int i, j, k; =20 - NormalEfficiency =3D (HostVMEnable =3D=3D true ? PercentOfIdealDRAMFabri= cAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData - : PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelDataO= nly) / 100.0; - PTEEfficiency =3D (HostVMEnable =3D=3D true ? PercentOfIdealDRAMFabricAn= dSDPPortBWReceivedAfterUrgLatencyVMDataOnly - / PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixed= WithVMData : 1.0); + NormalEfficiency =3D (v->HostVMEnable =3D=3D true ? v->PercentOfIdealDRA= MFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData + : v->PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelDa= taOnly) / 100.0; + PTEEfficiency =3D (v->HostVMEnable =3D=3D true ? v->PercentOfIdealDRAMFa= bricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly + / v->PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMi= xedWithVMData : 1.0); for (i =3D 0; i < mode_lib->soc.num_states; ++i) { for (j =3D 0; j <=3D 1; ++j) { double PixelDCFCLKCyclesRequiredInPrefetch[DC__NUM_DPP__MAX] =3D { 0 }; @@ -6698,58 +6529,58 @@ static void UseMinimumDCFCLK( double MinimumTvmPlus2Tr0 =3D 0; =20 TotalMaxPrefetchFlipDPTERowBandwidth[i][j] =3D 0; - for (k =3D 0; k < NumberOfActivePlanes; ++k) { + for (k =3D 0; k < v->NumberOfActivePlanes; ++k) { TotalMaxPrefetchFlipDPTERowBandwidth[i][j] =3D TotalMaxPrefetchFlipDPT= ERowBandwidth[i][j] - + NoOfDPP[i][j][k] * DPTEBytesPerRow[i][j][k] / (15.75 * HTotal[k] / = PixelClock[k]); + + v->NoOfDPP[i][j][k] * v->DPTEBytesPerRow[i][j][k] / (15.75 * v->HTo= tal[k] / v->PixelClock[k]); } =20 - for (k =3D 0; k <=3D NumberOfActivePlanes - 1; ++k) { - NoOfDPPState[k] =3D NoOfDPP[i][j][k]; + for (k =3D 0; k <=3D v->NumberOfActivePlanes - 1; ++k) { + NoOfDPPState[k] =3D v->NoOfDPP[i][j][k]; } =20 - MinimumTWait =3D CalculateTWait(MaxPrefetchMode, FinalDRAMClockChangeLa= tency, UrgLatency[i], SREnterPlusExitTime); - NonDPTEBandwidth =3D TotalVActivePixelBandwidth[i][j] + TotalVActiveCur= sorBandwidth[i][j] + TotalMetaRowBandwidth[i][j]; - DPTEBandwidth =3D (HostVMEnable =3D=3D true || ImmediateFlipRequiremen= t =3D=3D dm_immediate_flip_required) ? - TotalMaxPrefetchFlipDPTERowBandwidth[i][j] : TotalDPTERowBandwidth[i]= [j]; - DCFCLKRequiredForAverageBandwidth =3D dml_max3(ProjectedDCFCLKDeepSleep= [i][j], - (NonDPTEBandwidth + TotalDPTERowBandwidth[i][j]) / ReturnBusWidth / (= MaxAveragePercentOfIdealSDPPortBWDisplayCanUseInNormalSystemOperation / 100= ), - (NonDPTEBandwidth + DPTEBandwidth / PTEEfficiency) / NormalEfficiency= / ReturnBusWidth); - - ExtraLatencyBytes =3D CalculateExtraLatencyBytes(ReorderingBytes, Total= NumberOfActiveDPP[i][j], PixelChunkSizeInKByte, TotalNumberOfDCCActiveDPP[i= ][j], - MetaChunkSize, GPUVMEnable, HostVMEnable, NumberOfActivePlanes, NoOfD= PPState, dpte_group_bytes, - PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixed= WithVMData, PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDa= taOnly, - HostVMMinPageSize, HostVMMaxNonCachedPageTableLevels); - ExtraLatencyCycles =3D RoundTripPingLatencyCycles + 32 + ExtraLatencyBy= tes / NormalEfficiency / ReturnBusWidth; - for (k =3D 0; k < NumberOfActivePlanes; ++k) { + MinimumTWait =3D CalculateTWait(MaxPrefetchMode, v->FinalDRAMClockChang= eLatency, v->UrgLatency[i], v->SREnterPlusExitTime); + NonDPTEBandwidth =3D v->TotalVActivePixelBandwidth[i][j] + v->TotalVAct= iveCursorBandwidth[i][j] + v->TotalMetaRowBandwidth[i][j]; + DPTEBandwidth =3D (v->HostVMEnable =3D=3D true || v->ImmediateFlipRequ= irement[0] =3D=3D dm_immediate_flip_required) ? + TotalMaxPrefetchFlipDPTERowBandwidth[i][j] : v->TotalDPTERowBandwidth= [i][j]; + DCFCLKRequiredForAverageBandwidth =3D dml_max3(v->ProjectedDCFCLKDeepSl= eep[i][j], + (NonDPTEBandwidth + v->TotalDPTERowBandwidth[i][j]) / v->ReturnBusWid= th / (v->MaxAveragePercentOfIdealSDPPortBWDisplayCanUseInNormalSystemOperat= ion / 100), + (NonDPTEBandwidth + DPTEBandwidth / PTEEfficiency) / NormalEfficiency= / v->ReturnBusWidth); + + ExtraLatencyBytes =3D CalculateExtraLatencyBytes(ReorderingBytes, v->To= talNumberOfActiveDPP[i][j], v->PixelChunkSizeInKByte, v->TotalNumberOfDCCAc= tiveDPP[i][j], + v->MetaChunkSize, v->GPUVMEnable, v->HostVMEnable, v->NumberOfActiveP= lanes, NoOfDPPState, v->dpte_group_bytes, + v->PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMi= xedWithVMData, v->PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLaten= cyVMDataOnly, + v->HostVMMinPageSize, v->HostVMMaxNonCachedPageTableLevels); + ExtraLatencyCycles =3D v->RoundTripPingLatencyCycles + 32 + ExtraLatenc= yBytes / NormalEfficiency / v->ReturnBusWidth; + for (k =3D 0; k < v->NumberOfActivePlanes; ++k) { double DCFCLKCyclesRequiredInPrefetch =3D { 0 }; double ExpectedPrefetchBWAcceleration =3D { 0 }; double PrefetchTime =3D { 0 }; =20 - PixelDCFCLKCyclesRequiredInPrefetch[k] =3D (PrefetchLinesY[i][j][k] * = swath_width_luma_ub_all_states[i][j][k] * BytePerPixelY[k] - + PrefetchLinesC[i][j][k] * swath_width_chroma_ub_all_states[i][j][k]= * BytePerPixelC[k]) / NormalEfficiency / ReturnBusWidth; - DCFCLKCyclesRequiredInPrefetch =3D 2 * ExtraLatencyCycles / NoOfDPPSta= te[k] + PDEAndMetaPTEBytesPerFrame[i][j][k] / PTEEfficiency - / NormalEfficiency / ReturnBusWidth * (GPUVMMaxPageTableLevels > 2 ?= 1 : 0) + 2 * DPTEBytesPerRow[i][j][k] / PTEEfficiency - / NormalEfficiency / ReturnBusWidth + 2 * MetaRowBytes[i][j][k] / Nor= malEfficiency / ReturnBusWidth + PixelDCFCLKCyclesRequiredInPrefetch[k]; - PrefetchPixelLinesTime[k] =3D dml_max(PrefetchLinesY[i][j][k], Prefetc= hLinesC[i][j][k]) * HTotal[k] / PixelClock[k]; - ExpectedPrefetchBWAcceleration =3D (VActivePixelBandwidth[i][j][k] + V= ActiveCursorBandwidth[i][j][k]) / (ReadBandwidthLuma[k] + ReadBandwidthChro= ma[k]); - DynamicMetadataVMExtraLatency[k] =3D (GPUVMEnable =3D=3D true && Dynam= icMetadataEnable[k] =3D=3D true && DynamicMetadataVMEnabled =3D=3D true) ? - UrgLatency[i] * GPUVMMaxPageTableLevels * (HostVMEnable =3D=3D true= ? HostVMMaxNonCachedPageTableLevels + 1 : 1) : 0; - PrefetchTime =3D (MaximumVStartup[i][j][k] - 1) * HTotal[k] / PixelClo= ck[k] - MinimumTWait - UrgLatency[i] * ((GPUVMMaxPageTableLevels <=3D 2 ? G= PUVMMaxPageTableLevels - : GPUVMMaxPageTableLevels - 2) * (HostVMEnable =3D=3D true ? HostVMM= axNonCachedPageTableLevels + 1 : 1) - 1) - DynamicMetadataVMExtraLatency[k]; + PixelDCFCLKCyclesRequiredInPrefetch[k] =3D (v->PrefetchLinesY[i][j][k]= * v->swath_width_luma_ub_all_states[i][j][k] * v->BytePerPixelY[k] + + v->PrefetchLinesC[i][j][k] * v->swath_width_chroma_ub_all_states[i]= [j][k] * v->BytePerPixelC[k]) / NormalEfficiency / v->ReturnBusWidth; + DCFCLKCyclesRequiredInPrefetch =3D 2 * ExtraLatencyCycles / NoOfDPPSta= te[k] + v->PDEAndMetaPTEBytesPerFrame[i][j][k] / PTEEfficiency + / NormalEfficiency / v->ReturnBusWidth * (v->GPUVMMaxPageTableLevels= > 2 ? 1 : 0) + 2 * v->DPTEBytesPerRow[i][j][k] / PTEEfficiency + / NormalEfficiency / v->ReturnBusWidth + 2 * v->MetaRowBytes[i][j][k]= / NormalEfficiency / v->ReturnBusWidth + PixelDCFCLKCyclesRequiredInPrefet= ch[k]; + PrefetchPixelLinesTime[k] =3D dml_max(v->PrefetchLinesY[i][j][k], v->P= refetchLinesC[i][j][k]) * v->HTotal[k] / v->PixelClock[k]; + ExpectedPrefetchBWAcceleration =3D (v->VActivePixelBandwidth[i][j][k] = + v->VActiveCursorBandwidth[i][j][k]) / (v->ReadBandwidthLuma[k] + v->ReadB= andwidthChroma[k]); + DynamicMetadataVMExtraLatency[k] =3D (v->GPUVMEnable =3D=3D true && v-= >DynamicMetadataEnable[k] =3D=3D true && v->DynamicMetadataVMEnabled =3D=3D= true) ? + v->UrgLatency[i] * v->GPUVMMaxPageTableLevels * (v->HostVMEnable = =3D=3D true ? v->HostVMMaxNonCachedPageTableLevels + 1 : 1) : 0; + PrefetchTime =3D (v->MaximumVStartup[i][j][k] - 1) * v->HTotal[k] / v-= >PixelClock[k] - MinimumTWait - v->UrgLatency[i] * ((v->GPUVMMaxPageTableLe= vels <=3D 2 ? v->GPUVMMaxPageTableLevels + : v->GPUVMMaxPageTableLevels - 2) * (v->HostVMEnable =3D=3D true ? v= ->HostVMMaxNonCachedPageTableLevels + 1 : 1) - 1) - DynamicMetadataVMExtraL= atency[k]; =20 if (PrefetchTime > 0) { double ExpectedVRatioPrefetch =3D { 0 }; ExpectedVRatioPrefetch =3D PrefetchPixelLinesTime[k] / (PrefetchTime = * PixelDCFCLKCyclesRequiredInPrefetch[k] / DCFCLKCyclesRequiredInPrefetch); DCFCLKRequiredForPeakBandwidthPerPlane[k] =3D NoOfDPPState[k] * Pixel= DCFCLKCyclesRequiredInPrefetch[k] / PrefetchPixelLinesTime[k] * dml_max(1.0, ExpectedVRatioPrefetch) * dml_max(1.0, ExpectedVRatio= Prefetch / 4) * ExpectedPrefetchBWAcceleration; - if (HostVMEnable =3D=3D true || ImmediateFlipRequirement =3D=3D dm_im= mediate_flip_required) { + if (v->HostVMEnable =3D=3D true || v->ImmediateFlipRequirement[0] =3D= =3D dm_immediate_flip_required) { DCFCLKRequiredForPeakBandwidthPerPlane[k] =3D DCFCLKRequiredForPeakB= andwidthPerPlane[k] - + NoOfDPPState[k] * DPTEBandwidth / PTEEfficiency / NormalEfficienc= y / ReturnBusWidth; + + NoOfDPPState[k] * DPTEBandwidth / PTEEfficiency / NormalEfficienc= y / v->ReturnBusWidth; } } else { - DCFCLKRequiredForPeakBandwidthPerPlane[k] =3D DCFCLKPerState[i]; + DCFCLKRequiredForPeakBandwidthPerPlane[k] =3D v->DCFCLKPerState[i]; } - if (DynamicMetadataEnable[k] =3D=3D true) { + if (v->DynamicMetadataEnable[k] =3D=3D true) { double TsetupPipe =3D { 0 }; double TdmbfPipe =3D { 0 }; double TdmsksPipe =3D { 0 }; @@ -6757,49 +6588,49 @@ static void UseMinimumDCFCLK( double AllowedTimeForUrgentExtraLatency =3D { 0 }; =20 CalculateDynamicMetadataParameters( - MaxInterDCNTileRepeaters, - RequiredDPPCLK[i][j][k], - RequiredDISPCLK[i][j], - ProjectedDCFCLKDeepSleep[i][j], - PixelClock[k], - HTotal[k], - VTotal[k] - VActive[k], - DynamicMetadataTransmittedBytes[k], - DynamicMetadataLinesBeforeActiveRequired[k], - Interlace[k], - ProgressiveToInterlaceUnitInOPP, + v->MaxInterDCNTileRepeaters, + v->RequiredDPPCLK[i][j][k], + v->RequiredDISPCLK[i][j], + v->ProjectedDCFCLKDeepSleep[i][j], + v->PixelClock[k], + v->HTotal[k], + v->VTotal[k] - v->VActive[k], + v->DynamicMetadataTransmittedBytes[k], + v->DynamicMetadataLinesBeforeActiveRequired[k], + v->Interlace[k], + v->ProgressiveToInterlaceUnitInOPP, &TsetupPipe, &TdmbfPipe, &TdmecPipe, &TdmsksPipe); - AllowedTimeForUrgentExtraLatency =3D MaximumVStartup[i][j][k] * HTota= l[k] / PixelClock[k] - MinimumTWait - TsetupPipe + AllowedTimeForUrgentExtraLatency =3D v->MaximumVStartup[i][j][k] * v-= >HTotal[k] / v->PixelClock[k] - MinimumTWait - TsetupPipe - TdmbfPipe - TdmecPipe - TdmsksPipe - DynamicMetadataVMExtraLatenc= y[k]; if (AllowedTimeForUrgentExtraLatency > 0) { DCFCLKRequiredForPeakBandwidthPerPlane[k] =3D dml_max(DCFCLKRequired= ForPeakBandwidthPerPlane[k], ExtraLatencyCycles / AllowedTimeForUrgentExtraLatency); } else { - DCFCLKRequiredForPeakBandwidthPerPlane[k] =3D DCFCLKPerState[i]; + DCFCLKRequiredForPeakBandwidthPerPlane[k] =3D v->DCFCLKPerState[i]; } } } DCFCLKRequiredForPeakBandwidth =3D 0; - for (k =3D 0; k <=3D NumberOfActivePlanes - 1; ++k) { + for (k =3D 0; k <=3D v->NumberOfActivePlanes - 1; ++k) { DCFCLKRequiredForPeakBandwidth =3D DCFCLKRequiredForPeakBandwidth + DC= FCLKRequiredForPeakBandwidthPerPlane[k]; } - MinimumTvmPlus2Tr0 =3D UrgLatency[i] * (GPUVMEnable =3D=3D true ? (Host= VMEnable =3D=3D true ? - (GPUVMMaxPageTableLevels + 2) * (HostVMMaxNonCachedPageTableLevels + = 1) - 1 : GPUVMMaxPageTableLevels + 1) : 0); - for (k =3D 0; k < NumberOfActivePlanes; ++k) { + MinimumTvmPlus2Tr0 =3D v->UrgLatency[i] * (v->GPUVMEnable =3D=3D true ?= (v->HostVMEnable =3D=3D true ? + (v->GPUVMMaxPageTableLevels + 2) * (v->HostVMMaxNonCachedPageTableLev= els + 1) - 1 : v->GPUVMMaxPageTableLevels + 1) : 0); + for (k =3D 0; k < v->NumberOfActivePlanes; ++k) { double MaximumTvmPlus2Tr0PlusTsw =3D { 0 }; - MaximumTvmPlus2Tr0PlusTsw =3D (MaximumVStartup[i][j][k] - 2) * HTotal[= k] / PixelClock[k] - MinimumTWait - DynamicMetadataVMExtraLatency[k]; + MaximumTvmPlus2Tr0PlusTsw =3D (v->MaximumVStartup[i][j][k] - 2) * v->H= Total[k] / v->PixelClock[k] - MinimumTWait - DynamicMetadataVMExtraLatency[= k]; if (MaximumTvmPlus2Tr0PlusTsw <=3D MinimumTvmPlus2Tr0 + PrefetchPixelL= inesTime[k] / 4) { - DCFCLKRequiredForPeakBandwidth =3D DCFCLKPerState[i]; + DCFCLKRequiredForPeakBandwidth =3D v->DCFCLKPerState[i]; } else { DCFCLKRequiredForPeakBandwidth =3D dml_max3(DCFCLKRequiredForPeakBand= width, 2 * ExtraLatencyCycles / (MaximumTvmPlus2Tr0PlusTsw - MinimumTvmPlus2Tr0 - PrefetchPixelLi= nesTime[k] / 4), (2 * ExtraLatencyCycles + PixelDCFCLKCyclesRequiredInPrefetch[k]) / = (MaximumTvmPlus2Tr0PlusTsw - MinimumTvmPlus2Tr0)); } } - DCFCLKState[i][j] =3D dml_min(DCFCLKPerState[i], 1.05 * (1 + mode_lib->= vba.PercentMarginOverMinimumRequiredDCFCLK / 100) + v->DCFCLKState[i][j] =3D dml_min(v->DCFCLKPerState[i], 1.05 * (1 + mode= _lib->vba.PercentMarginOverMinimumRequiredDCFCLK / 100) * dml_max(DCFCLKRequiredForAverageBandwidth, DCFCLKRequiredForPeakBan= dwidth)); } } --=20 2.37.1