From nobody Sat Apr 11 00:48:18 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2DFCDC25B08 for ; Wed, 17 Aug 2022 20:26:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241934AbiHQU0O (ORCPT ); Wed, 17 Aug 2022 16:26:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39612 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241908AbiHQU0F (ORCPT ); Wed, 17 Aug 2022 16:26:05 -0400 Received: from inva021.nxp.com (inva021.nxp.com [92.121.34.21]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2AE84A9278; Wed, 17 Aug 2022 13:25:58 -0700 (PDT) Received: from inva021.nxp.com (localhost [127.0.0.1]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 3CE8720022E; Wed, 17 Aug 2022 22:25:56 +0200 (CEST) Received: from smtp.na-rdc02.nxp.com (usphx01srsp001v.us-phx01.nxp.com [134.27.49.11]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id C8A8E200240; Wed, 17 Aug 2022 22:25:55 +0200 (CEST) Received: from right.am.freescale.net (right.am.freescale.net [10.81.116.134]) by usphx01srsp001v.us-phx01.nxp.com (Postfix) with ESMTP id 802EB4060D; Wed, 17 Aug 2022 13:25:54 -0700 (MST) From: Li Yang To: shawnguo@kernel.org, devicetree@vger.kernel.org Cc: robh+dt@kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Li Yang , Hou Zhiqiang Subject: [PATCH v4 1/2] arm64: dts: lx2160a: update PCIe nodes to match rev2 silicon Date: Wed, 17 Aug 2022 15:25:37 -0500 Message-Id: <20220817202538.21493-2-leoyang.li@nxp.com> X-Mailer: git-send-email 2.25.1.377.g2d2118b In-Reply-To: <20220817202538.21493-1-leoyang.li@nxp.com> References: <20220817202538.21493-1-leoyang.li@nxp.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Virus-Scanned: ClamAV using ClamSMTP Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The original dts was created based on the non-production rev1 silicon which was only used for evaluation. Update the PCIe nodes to align with the different controller used in production rev2 silicon. Signed-off-by: Li Yang Reviewed-by: Hou Zhiqiang --- .../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 96 +++++++++---------- 1 file changed, 48 insertions(+), 48 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/bo= ot/dts/freescale/fsl-lx2160a.dtsi index 6680fb2a6dc9..a7c549277dcc 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi @@ -1104,10 +1104,10 @@ sata3: sata@3230000 { }; =20 pcie1: pcie@3400000 { - compatible =3D "fsl,lx2160a-pcie"; - reg =3D <0x00 0x03400000 0x0 0x00100000>, /* controller registers */ - <0x80 0x00000000 0x0 0x00002000>; /* configuration space */ - reg-names =3D "csr_axi_slave", "config_axi_slave"; + compatible =3D "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie"; + reg =3D <0x00 0x03400000 0x0 0x00100000 /* controller registers */ + 0x80 0x00000000 0x0 0x00002000>; /* configuration space */ + reg-names =3D "regs", "config"; interrupts =3D , /* AER interrupt */ , /* PME interrupt */ ; /* controller interrupt */ @@ -1116,26 +1116,26 @@ pcie1: pcie@3400000 { #size-cells =3D <2>; device_type =3D "pci"; dma-coherent; - apio-wins =3D <8>; - ppio-wins =3D <8>; + num-viewport =3D <8>; bus-range =3D <0x0 0xff>; - ranges =3D <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; = /* non-prefetchable memory */ + ranges =3D <0x81000000 0x0 0x00000000 0x80 0x00010000 0x0 0x00010000 + 0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-pr= efetchable memory */ msi-parent =3D <&its>; + iommu-map =3D <0 &smmu 0 1>; /* This is fixed-up by u-boot */ #interrupt-cells =3D <1>; interrupt-map-mask =3D <0 0 0 7>; interrupt-map =3D <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; - iommu-map =3D <0 &smmu 0 1>; /* Fixed-up by bootloader */ status =3D "disabled"; }; =20 pcie2: pcie@3500000 { - compatible =3D "fsl,lx2160a-pcie"; - reg =3D <0x00 0x03500000 0x0 0x00100000>, /* controller registers */ - <0x88 0x00000000 0x0 0x00002000>; /* configuration space */ - reg-names =3D "csr_axi_slave", "config_axi_slave"; + compatible =3D "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie"; + reg =3D <0x00 0x03500000 0x0 0x00100000 /* controller registers */ + 0x88 0x00000000 0x0 0x00002000>; /* configuration space */ + reg-names =3D "regs", "config"; interrupts =3D , /* AER interrupt */ , /* PME interrupt */ ; /* controller interrupt */ @@ -1144,26 +1144,26 @@ pcie2: pcie@3500000 { #size-cells =3D <2>; device_type =3D "pci"; dma-coherent; - apio-wins =3D <8>; - ppio-wins =3D <8>; + num-viewport =3D <8>; bus-range =3D <0x0 0xff>; - ranges =3D <0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; = /* non-prefetchable memory */ + ranges =3D <0x81000000 0x0 0x00000000 0x88 0x00010000 0x0 0x00010000 + 0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-pr= efetchable memory */ msi-parent =3D <&its>; + iommu-map =3D <0 &smmu 0 1>; /* This is fixed-up by u-boot */ #interrupt-cells =3D <1>; interrupt-map-mask =3D <0 0 0 7>; interrupt-map =3D <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; - iommu-map =3D <0 &smmu 0 1>; /* Fixed-up by bootloader */ status =3D "disabled"; }; =20 pcie3: pcie@3600000 { - compatible =3D "fsl,lx2160a-pcie"; - reg =3D <0x00 0x03600000 0x0 0x00100000>, /* controller registers */ - <0x90 0x00000000 0x0 0x00002000>; /* configuration space */ - reg-names =3D "csr_axi_slave", "config_axi_slave"; + compatible =3D "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie"; + reg =3D <0x00 0x03600000 0x0 0x00100000 /* controller registers */ + 0x90 0x00000000 0x0 0x00002000>; /* configuration space */ + reg-names =3D "regs", "config"; interrupts =3D , /* AER interrupt */ , /* PME interrupt */ ; /* controller interrupt */ @@ -1172,26 +1172,26 @@ pcie3: pcie@3600000 { #size-cells =3D <2>; device_type =3D "pci"; dma-coherent; - apio-wins =3D <256>; - ppio-wins =3D <24>; + num-viewport =3D <256>; bus-range =3D <0x0 0xff>; - ranges =3D <0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>; = /* non-prefetchable memory */ + ranges =3D <0x81000000 0x0 0x00000000 0x90 0x00010000 0x0 0x00010000 + 0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>; /* non-pr= efetchable memory */ msi-parent =3D <&its>; + iommu-map =3D <0 &smmu 0 1>; /* This is fixed-up by u-boot */ #interrupt-cells =3D <1>; interrupt-map-mask =3D <0 0 0 7>; interrupt-map =3D <0000 0 0 1 &gic 0 0 GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 2 &gic 0 0 GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 3 &gic 0 0 GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 4 &gic 0 0 GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; - iommu-map =3D <0 &smmu 0 1>; /* Fixed-up by bootloader */ status =3D "disabled"; }; =20 pcie4: pcie@3700000 { - compatible =3D "fsl,lx2160a-pcie"; - reg =3D <0x00 0x03700000 0x0 0x00100000>, /* controller registers */ - <0x98 0x00000000 0x0 0x00002000>; /* configuration space */ - reg-names =3D "csr_axi_slave", "config_axi_slave"; + compatible =3D "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie"; + reg =3D <0x00 0x03700000 0x0 0x00100000 /* controller registers */ + 0x98 0x00000000 0x0 0x00002000>; /* configuration space */ + reg-names =3D "regs", "config"; interrupts =3D , /* AER interrupt */ , /* PME interrupt */ ; /* controller interrupt */ @@ -1200,26 +1200,26 @@ pcie4: pcie@3700000 { #size-cells =3D <2>; device_type =3D "pci"; dma-coherent; - apio-wins =3D <8>; - ppio-wins =3D <8>; + num-viewport =3D <8>; bus-range =3D <0x0 0xff>; - ranges =3D <0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>; = /* non-prefetchable memory */ + ranges =3D <0x81000000 0x0 0x00000000 0x98 0x00010000 0x0 0x00010000 + 0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>; /* non-pr= efetchable memory */ msi-parent =3D <&its>; + iommu-map =3D <0 &smmu 0 1>; /* This is fixed-up by u-boot */ #interrupt-cells =3D <1>; interrupt-map-mask =3D <0 0 0 7>; interrupt-map =3D <0000 0 0 1 &gic 0 0 GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 2 &gic 0 0 GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 3 &gic 0 0 GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 4 &gic 0 0 GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; - iommu-map =3D <0 &smmu 0 1>; /* Fixed-up by bootloader */ status =3D "disabled"; }; =20 pcie5: pcie@3800000 { - compatible =3D "fsl,lx2160a-pcie"; - reg =3D <0x00 0x03800000 0x0 0x00100000>, /* controller registers */ - <0xa0 0x00000000 0x0 0x00002000>; /* configuration space */ - reg-names =3D "csr_axi_slave", "config_axi_slave"; + compatible =3D "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie"; + reg =3D <0x00 0x03800000 0x0 0x00100000 /* controller registers */ + 0xa0 0x00000000 0x0 0x00002000>; /* configuration space */ + reg-names =3D "regs", "config"; interrupts =3D , /* AER interrupt */ , /* PME interrupt */ ; /* controller interrupt */ @@ -1228,26 +1228,26 @@ pcie5: pcie@3800000 { #size-cells =3D <2>; device_type =3D "pci"; dma-coherent; - apio-wins =3D <256>; - ppio-wins =3D <24>; + num-viewport =3D <256>; bus-range =3D <0x0 0xff>; - ranges =3D <0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>; = /* non-prefetchable memory */ + ranges =3D <0x81000000 0x0 0x00000000 0xa0 0x00010000 0x0 0x00010000 + 0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>; /* non-pr= efetchable memory */ msi-parent =3D <&its>; + iommu-map =3D <0 &smmu 0 1>; /* This is fixed-up by u-boot */ #interrupt-cells =3D <1>; interrupt-map-mask =3D <0 0 0 7>; interrupt-map =3D <0000 0 0 1 &gic 0 0 GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 2 &gic 0 0 GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 3 &gic 0 0 GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 4 &gic 0 0 GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; - iommu-map =3D <0 &smmu 0 1>; /* Fixed-up by bootloader */ status =3D "disabled"; }; =20 pcie6: pcie@3900000 { - compatible =3D "fsl,lx2160a-pcie"; - reg =3D <0x00 0x03900000 0x0 0x00100000>, /* controller registers */ - <0xa8 0x00000000 0x0 0x00002000>; /* configuration space */ - reg-names =3D "csr_axi_slave", "config_axi_slave"; + compatible =3D "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie"; + reg =3D <0x00 0x03900000 0x0 0x00100000 /* controller registers */ + 0xa8 0x00000000 0x0 0x00002000>; /* configuration space */ + reg-names =3D "regs", "config"; interrupts =3D , /* AER interrupt */ , /* PME interrupt */ ; /* controller interrupt */ @@ -1256,18 +1256,18 @@ pcie6: pcie@3900000 { #size-cells =3D <2>; device_type =3D "pci"; dma-coherent; - apio-wins =3D <8>; - ppio-wins =3D <8>; + num-viewport =3D <8>; bus-range =3D <0x0 0xff>; - ranges =3D <0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>; = /* non-prefetchable memory */ + ranges =3D <0x81000000 0x0 0x00000000 0xa8 0x00010000 0x0 0x00010000 + 0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>; /* non-pr= efetchable memory */ msi-parent =3D <&its>; + iommu-map =3D <0 &smmu 0 1>; /* This is fixed-up by u-boot */ #interrupt-cells =3D <1>; interrupt-map-mask =3D <0 0 0 7>; interrupt-map =3D <0000 0 0 1 &gic 0 0 GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 2 &gic 0 0 GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 3 &gic 0 0 GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 4 &gic 0 0 GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; - iommu-map =3D <0 &smmu 0 1>; /* Fixed-up by bootloader */ status =3D "disabled"; }; =20 --=20 2.37.1 From nobody Sat Apr 11 00:48:18 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 32A7FC25B08 for ; Wed, 17 Aug 2022 20:26:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241970AbiHQU0W (ORCPT ); Wed, 17 Aug 2022 16:26:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40002 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241953AbiHQU0H (ORCPT ); Wed, 17 Aug 2022 16:26:07 -0400 Received: from inva021.nxp.com (inva021.nxp.com [92.121.34.21]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D31EEA98E6; Wed, 17 Aug 2022 13:25:59 -0700 (PDT) Received: from inva021.nxp.com (localhost [127.0.0.1]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id E238420024C; Wed, 17 Aug 2022 22:25:57 +0200 (CEST) Received: from smtp.na-rdc02.nxp.com (usphx01srsp001v.us-phx01.nxp.com [134.27.49.11]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 7BC37200240; Wed, 17 Aug 2022 22:25:57 +0200 (CEST) Received: from right.am.freescale.net (right.am.freescale.net [10.81.116.134]) by usphx01srsp001v.us-phx01.nxp.com (Postfix) with ESMTP id 10B3F40AA2; Wed, 17 Aug 2022 13:25:55 -0700 (MST) From: Li Yang To: shawnguo@kernel.org, devicetree@vger.kernel.org Cc: robh+dt@kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Xiaowei Bao , Li Yang , Hou Zhiqiang Subject: [PATCH v4 2/2] arm64: dts: lx2160a: add pcie EP mode nodes Date: Wed, 17 Aug 2022 15:25:38 -0500 Message-Id: <20220817202538.21493-3-leoyang.li@nxp.com> X-Mailer: git-send-email 2.25.1.377.g2d2118b In-Reply-To: <20220817202538.21493-1-leoyang.li@nxp.com> References: <20220817202538.21493-1-leoyang.li@nxp.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Virus-Scanned: ClamAV using ClamSMTP Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Xiaowei Bao The LX2160A PCIe EP mode nodes based on controller used on lx2160a rev2. Signed-off-by: Xiaowei Bao Signed-off-by: Li Yang Reviewed-by: Hou Zhiqiang --- .../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 60 +++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/bo= ot/dts/freescale/fsl-lx2160a.dtsi index a7c549277dcc..97786b454ec7 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi @@ -1131,6 +1131,16 @@ pcie1: pcie@3400000 { status =3D "disabled"; }; =20 + pcie_ep1: pcie-ep@3400000 { + compatible =3D "fsl,lx2160ar2-pcie-ep", "fsl,ls-pcie-ep"; + reg =3D <0x00 0x03400000 0x0 0x00100000 + 0x80 0x00000000 0x8 0x00000000>; + reg-names =3D "regs", "addr_space"; + num-ob-windows =3D <8>; + num-ib-windows =3D <8>; + status =3D "disabled"; + }; + pcie2: pcie@3500000 { compatible =3D "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie"; reg =3D <0x00 0x03500000 0x0 0x00100000 /* controller registers */ @@ -1159,6 +1169,16 @@ pcie2: pcie@3500000 { status =3D "disabled"; }; =20 + pcie_ep2: pcie-ep@3500000 { + compatible =3D "fsl,lx2160ar2-pcie-ep", "fsl,ls-pcie-ep"; + reg =3D <0x00 0x03500000 0x0 0x00100000 + 0x88 0x00000000 0x8 0x00000000>; + reg-names =3D "regs", "addr_space"; + num-ob-windows =3D <8>; + num-ib-windows =3D <8>; + status =3D "disabled"; + }; + pcie3: pcie@3600000 { compatible =3D "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie"; reg =3D <0x00 0x03600000 0x0 0x00100000 /* controller registers */ @@ -1187,6 +1207,16 @@ pcie3: pcie@3600000 { status =3D "disabled"; }; =20 + pcie_ep3: pcie-ep@3600000 { + compatible =3D "fsl,lx2160ar2-pcie-ep", "fsl,ls-pcie-ep"; + reg =3D <0x00 0x03600000 0x0 0x00100000 + 0x90 0x00000000 0x8 0x00000000>; + reg-names =3D "regs", "addr_space"; + num-ob-windows =3D <256>; + num-ib-windows =3D <24>; + status =3D "disabled"; + }; + pcie4: pcie@3700000 { compatible =3D "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie"; reg =3D <0x00 0x03700000 0x0 0x00100000 /* controller registers */ @@ -1215,6 +1245,16 @@ pcie4: pcie@3700000 { status =3D "disabled"; }; =20 + pcie_ep4: pcie-ep@3700000 { + compatible =3D "fsl,lx2160ar2-pcie-ep", "fsl,ls-pcie-ep"; + reg =3D <0x00 0x03700000 0x0 0x00100000 + 0x98 0x00000000 0x8 0x00000000>; + reg-names =3D "regs", "addr_space"; + num-ob-windows =3D <8>; + num-ib-windows =3D <8>; + status =3D "disabled"; + }; + pcie5: pcie@3800000 { compatible =3D "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie"; reg =3D <0x00 0x03800000 0x0 0x00100000 /* controller registers */ @@ -1243,6 +1283,16 @@ pcie5: pcie@3800000 { status =3D "disabled"; }; =20 + pcie_ep5: pcie-ep@3800000 { + compatible =3D "fsl,lx2160ar2-pcie-ep", "fsl,ls-pcie-ep"; + reg =3D <0x00 0x03800000 0x0 0x00100000 + 0xa0 0x00000000 0x8 0x00000000>; + reg-names =3D "regs", "addr_space"; + num-ob-windows =3D <256>; + num-ib-windows =3D <24>; + status =3D "disabled"; + }; + pcie6: pcie@3900000 { compatible =3D "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie"; reg =3D <0x00 0x03900000 0x0 0x00100000 /* controller registers */ @@ -1271,6 +1321,16 @@ pcie6: pcie@3900000 { status =3D "disabled"; }; =20 + pcie_ep6: pcie-ep@3900000 { + compatible =3D "fsl,lx2160ar2-pcie-ep", "fsl,ls-pcie-ep"; + reg =3D <0x00 0x03900000 0x0 0x00100000 + 0xa8 0x00000000 0x8 0x00000000>; + reg-names =3D "regs", "addr_space"; + num-ob-windows =3D <8>; + num-ib-windows =3D <8>; + status =3D "disabled"; + }; + smmu: iommu@5000000 { compatible =3D "arm,mmu-500"; reg =3D <0 0x5000000 0 0x800000>; --=20 2.37.1