From nobody Sat Apr 11 00:49:39 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EB002C25B08 for ; Wed, 17 Aug 2022 20:12:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241498AbiHQUMm (ORCPT ); Wed, 17 Aug 2022 16:12:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34030 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240665AbiHQUMk (ORCPT ); Wed, 17 Aug 2022 16:12:40 -0400 Received: from mail-wm1-x330.google.com (mail-wm1-x330.google.com [IPv6:2a00:1450:4864:20::330]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 29A32A61DF for ; Wed, 17 Aug 2022 13:12:39 -0700 (PDT) Received: by mail-wm1-x330.google.com with SMTP id bd26-20020a05600c1f1a00b003a5e82a6474so1444501wmb.4 for ; Wed, 17 Aug 2022 13:12:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=conchuod.ie; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=1R6UrF0Wsbj6EmcSlPWRzTAwonFDames2nGAVyANWlQ=; b=PwR33To0N5ui/sX2vHA5vGOkVP5CwIp7cjsA3PN3/adE8gVsnwKwcA8MYb7gioCksg ahw0LIbslkzwkpF5jej+bp4Yf0eOt17d57rj6NZDdo2SwIe+S6QwHLjSHV2P1MzSZIBc SYx4JQvjJaj8YXXwnSVR4gMkDl8Q0JCp8oTckDnqWMsTdK5gI0pMdfXPPzjOTaFzzLMQ 12YILMe1gQQ55rA8mLmVO7Cvz9oVG8YaFarhPLW/UC6wwUTSAdaNVhcSQfB/LksZ2ARG 6gYZLDZVb5Wsbi12Ll5V36MnebMaEECTDL38Z4MC7mvuhjAl2WJjonXIZ/KRs1DxNILj o4YQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=1R6UrF0Wsbj6EmcSlPWRzTAwonFDames2nGAVyANWlQ=; b=Lvdb/iUMqW0JALRWzPVU6Cr/wSoI8soEoPR1WYCI2bPzY1GmklnFGYpWgquOHmmLfO tPoVAu1vR5nWC8p7u13a7Ez40keqGHYLPJoSoFL+nYUC6JcNgz0OEKguvvz/YFqwtHbC F2AM42BcFnXLyniHYD6YStR0HN1qYGw7IyHx/vHC1AQmN5oIliN/CkYqoRj7DCGexbpc 2cXS7dVSoqEtzhumQmUP9bvpXvRHbYlSYBuHRquMai+UIHWlDIdSUo0/qiZZP0KwKjWO 58LoFIIPlCnrYWRvR9uz2pimDCVrr7jjOaFlcauLMfxrUMbPtDBphM9Z1j5MZMhpI5FE iSNw== X-Gm-Message-State: ACgBeo1o2IiOvoyTC4Pgy3cVZX5H7imdcOw0lX//zUi+gwzf/XEEB2Yp LwCdy9+cOw8qA98kFhkWqea/Xg== X-Google-Smtp-Source: AA6agR6lJ1JCJSrjpa59CdkKTqHzSw7FSFRvF0du7bAKFhB5DFjPBDZy5X6POzzhjKmao4BdhzICzA== X-Received: by 2002:a05:600c:4f8f:b0:3a3:4612:6879 with SMTP id n15-20020a05600c4f8f00b003a346126879mr3121447wmq.84.1660767157797; Wed, 17 Aug 2022 13:12:37 -0700 (PDT) Received: from henark71.. ([109.76.58.63]) by smtp.gmail.com with ESMTPSA id i15-20020a05600c354f00b003a5dfd7e9eesm3029371wmq.44.2022.08.17.13.12.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Aug 2022 13:12:37 -0700 (PDT) From: Conor Dooley To: Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Palmer Dabbelt , Paul Walmsley , Albert Ou Cc: Daniel Lezcano , Anup Patel , Conor Dooley , Guo Ren , Sagar Kadam , Jessica Clarke , Andrew Jones , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, qemu-riscv@nongnu.org, Rob Herring Subject: [PATCH v3 1/4] dt-bindings: timer: sifive,clint: add legacy riscv compatible Date: Wed, 17 Aug 2022 21:12:10 +0100 Message-Id: <20220817201212.990712-2-mail@conchuod.ie> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220817201212.990712-1-mail@conchuod.ie> References: <20220817201212.990712-1-mail@conchuod.ie> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Conor Dooley While "real" hardware might not use the compatible string "riscv,clint0" it is present in the driver & QEMU uses it for automatically generated virt machine dtbs. To avoid dt-validate problems with QEMU produced dtbs, such as the following, add it to the binding. riscv-virt.dtb: clint@2000000: compatible:0: 'sifive,clint0' is not one of = ['sifive,fu540-c000-clint', 'starfive,jh7100-clint', 'canaan,k210-clint'] Reported-by: Rob Herring Link: https://lore.kernel.org/linux-riscv/20220803170552.GA2250266-robh@ker= nel.org/ Signed-off-by: Conor Dooley Reviewed-by: Rob Herring --- .../bindings/timer/sifive,clint.yaml | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Do= cumentation/devicetree/bindings/timer/sifive,clint.yaml index e64f46339079..bbad24165837 100644 --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml @@ -22,12 +22,18 @@ description: =20 properties: compatible: - items: - - enum: - - sifive,fu540-c000-clint - - starfive,jh7100-clint - - canaan,k210-clint - - const: sifive,clint0 + oneOf: + - items: + - enum: + - sifive,fu540-c000-clint + - starfive,jh7100-clint + - canaan,k210-clint + - const: sifive,clint0 + - items: + - const: sifive,clint0 + - const: riscv,clint0 + deprecated: true + description: For the QEMU virt machine only =20 description: Should be ",-clint" and "sifive,clint". --=20 2.37.1 From nobody Sat Apr 11 00:49:39 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E65FEC25B08 for ; Wed, 17 Aug 2022 20:12:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241538AbiHQUMq (ORCPT ); Wed, 17 Aug 2022 16:12:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34070 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241467AbiHQUMl (ORCPT ); Wed, 17 Aug 2022 16:12:41 -0400 Received: from mail-wm1-x331.google.com (mail-wm1-x331.google.com [IPv6:2a00:1450:4864:20::331]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8CE6666A4B for ; Wed, 17 Aug 2022 13:12:40 -0700 (PDT) Received: by mail-wm1-x331.google.com with SMTP id s23so7153266wmj.4 for ; Wed, 17 Aug 2022 13:12:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=conchuod.ie; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=vuO3cD7vHfOoM26qaFlIa3/qXvWH4JaTB3axSBEJPBw=; b=QNqHEQCbHfRVGS+tAMiAeZUZwHbBaHSl0+l3elr57UhAo9n9y5kVxNnKfpGR3/bFaK +0au1CDmSpQEpc+SU4gk9DT+bLflPHiKU7I8q8oQr7K+iXIJMVRPppzrl+EdG1CICueI mETGyBRKdR/0jUMOQefFZwBRXS0F6IVfTdGwBMcn+/W4tOLw5o3k++yjoq0kYu6PUOu8 zPeHvkIN/+xOD7MPCo5mJihWLZw9Ayb2dZz9D3SYCFb7mSsm+ctbY/v+37Sk2BkryeRN +keBV6AYTGq3C5eSUKwO2Ih+l7MLpNlzPwmWLNs+G4q0F/Ce1V4BLVEMj+kApmgnT9U8 jwKw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=vuO3cD7vHfOoM26qaFlIa3/qXvWH4JaTB3axSBEJPBw=; b=7XhQVlrMXqnpPFvl60lfO/k9H4JW3Ak16q5XCjsMlkPUgBuIdoSS8dPPdxLMnqhuWJ BSARKZz2RpBfEtgHh7fjbTkY8yFrE/6e+S1wqyJvQXtdADzU+H5l+zGtw4en/SgA+w34 jlVy0tu2CLjD905Qo5+69QsSaff6WrtEe+6jaq5+klpmE9nJcMH6t7c9f6j5tzI9rsDE 7a5+25JZP4wCN6gZ/D/S8qXA50yH7GvsVKm4VyJtsdg4eWjVULvzSnx1jac7NtuMuGg2 z11Rd07f55RtqsCP42W5dIkOdnm/TGJ9qXoIuM6bfS25sMglQUEzKXiuS33SZHuHSlZu bFiw== X-Gm-Message-State: ACgBeo2JVSitQNgTqWcIpamjK0HayL+9FrNpVmrTk/bpv5QVSAHoq03l hSsTIKBgurIhQ1xehQ6v3HWNMg== X-Google-Smtp-Source: AA6agR4uxolucIHZMbESqZVNmKY0bzNzoYEESejDuTjDSWvejaLJaV19DGDusJCVom1LcN9XAiM6Ow== X-Received: by 2002:a1c:7407:0:b0:3a5:b81b:c5c5 with SMTP id p7-20020a1c7407000000b003a5b81bc5c5mr3038616wmc.144.1660767160200; Wed, 17 Aug 2022 13:12:40 -0700 (PDT) Received: from henark71.. ([109.76.58.63]) by smtp.gmail.com with ESMTPSA id i15-20020a05600c354f00b003a5dfd7e9eesm3029371wmq.44.2022.08.17.13.12.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Aug 2022 13:12:39 -0700 (PDT) From: Conor Dooley To: Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Palmer Dabbelt , Paul Walmsley , Albert Ou Cc: Daniel Lezcano , Anup Patel , Conor Dooley , Guo Ren , Sagar Kadam , Jessica Clarke , Andrew Jones , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, qemu-riscv@nongnu.org, Rob Herring Subject: [PATCH v3 2/4] dt-bindings: interrupt-controller: sifive,plic: add legacy riscv compatible Date: Wed, 17 Aug 2022 21:12:11 +0100 Message-Id: <20220817201212.990712-3-mail@conchuod.ie> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220817201212.990712-1-mail@conchuod.ie> References: <20220817201212.990712-1-mail@conchuod.ie> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Conor Dooley While "real" hardware might not use the compatible string "riscv,plic0" it is present in the driver & QEMU uses it for automatically generated virt machine dtbs. To avoid dt-validate problems with QEMU produced dtbs, such as the following, add it to the binding. riscv-virt.dtb: plic@c000000: compatible: 'oneOf' conditional failed, one m= ust be fixed: 'sifive,plic-1.0.0' is not one of ['sifive,fu540-c000-plic', 'starf= ive,jh7100-plic', 'canaan,k210-plic'] 'sifive,plic-1.0.0' is not one of ['allwinner,sun20i-d1-plic'] 'sifive,plic-1.0.0' was expected 'thead,c900-plic' was expected riscv-virt.dtb: plic@c000000: '#address-cells' is a required property Reported-by: Rob Herring Link: https://lore.kernel.org/linux-riscv/20220803170552.GA2250266-robh@ker= nel.org/ Signed-off-by: Conor Dooley Reviewed-by: Rob Herring --- .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,= plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/si= five,plic-1.0.0.yaml index 92e0f8c3eff2..99e01f4d0a69 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.= 0.0.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.= 0.0.yaml @@ -66,6 +66,11 @@ properties: - enum: - allwinner,sun20i-d1-plic - const: thead,c900-plic + - items: + - const: sifive,plic-1.0.0 + - const: riscv,plic0 + deprecated: true + description: For the QEMU virt machine only =20 reg: maxItems: 1 --=20 2.37.1 From nobody Sat Apr 11 00:49:39 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 16A0EC25B08 for ; Wed, 17 Aug 2022 20:13:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241781AbiHQUM6 (ORCPT ); Wed, 17 Aug 2022 16:12:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34150 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241519AbiHQUMr (ORCPT ); Wed, 17 Aug 2022 16:12:47 -0400 Received: from mail-wm1-x330.google.com (mail-wm1-x330.google.com [IPv6:2a00:1450:4864:20::330]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DAE49A6C2C for ; Wed, 17 Aug 2022 13:12:45 -0700 (PDT) Received: by mail-wm1-x330.google.com with SMTP id c187-20020a1c35c4000000b003a30d88fe8eso1569346wma.2 for ; Wed, 17 Aug 2022 13:12:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=conchuod.ie; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=De0s+s/D2rq5b1W85sP7P0sadpD1tyl+4KZh5xfCdFc=; b=VoUCelW9ATsck56Z8Vshz+e5skJfqAaLWP0HlwFo7La/BTrmJH5e8zjyqLvEREwsny wivfEbQBCbsuAwXFwnaTCReVWo48k1o/9NHZ6uWUyyb1QcRZaacS8eYKfW160GvNgdRl tERNO6oWhTlIwX2AAbAEDn9M5mRMpl16CQcmPD1jWSFcupCT4CmqBFX72IKxsy5HNvI6 1ofx3JTRa4Gz5oJXqe8j7aHCHkdofi+lsc4O68CTHYD7rM2Dd+IYZB4Y1c4bvN760fwl mqGvxbSv/gH2QOynns+PpVsW5V8qUj2oLo3HbjL3PbdYC6gjSc78t0dyQeNKj8aE5M8n wMLQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=De0s+s/D2rq5b1W85sP7P0sadpD1tyl+4KZh5xfCdFc=; b=hKa4vXMuq76OzDdwuGp0TB9c2OK/gnZSzpFaJH0lf6JGkAq8s8jHiYwgHuE2shvpnm alZJyqVsna8GmOyTfMOP1UGgsN8GFLeS+L2SUOPx8ntJw6HRyR5R96tdjbUyRrRFhbaa BjemcYs6o3TCHWOLXZNdbUzHlBqDeAOJT8+CEe1cTXlEevNRWB/miBJ5XN9ie7tfKKWu IsvtCpaiackQWB/mcBqldbP15Jfr73jjIKylI87nZeZe0JGti7SnUgF6N4TJo4ON0kAT g5grC9j5t0kC28MVjlTE0j6rKBWzDG6d1cf+Pg7Ru0pJJ3rDM61uSZPIPIDoH/zsQwpr 9SQA== X-Gm-Message-State: ACgBeo0H81763rpStZ/IpV+wdc9J60oZ1D4k1VPvSGY1rMyuqt6iL1UY ZBh4j8rEK98k8xQWP8c3golmSg== X-Google-Smtp-Source: AA6agR5fECZky51OLxj7IyiHwCUh5pSaXNngYTDHiSH2lpDG7XCOjdR0BjCA3TzdeYNFfoayKbBkfg== X-Received: by 2002:a05:600c:4f05:b0:3a5:ffec:b6b with SMTP id l5-20020a05600c4f0500b003a5ffec0b6bmr3007577wmq.199.1660767164394; Wed, 17 Aug 2022 13:12:44 -0700 (PDT) Received: from henark71.. ([109.76.58.63]) by smtp.gmail.com with ESMTPSA id i15-20020a05600c354f00b003a5dfd7e9eesm3029371wmq.44.2022.08.17.13.12.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Aug 2022 13:12:43 -0700 (PDT) From: Conor Dooley To: Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Palmer Dabbelt , Paul Walmsley , Albert Ou Cc: Daniel Lezcano , Anup Patel , Conor Dooley , Guo Ren , Sagar Kadam , Jessica Clarke , Andrew Jones , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, qemu-riscv@nongnu.org, Rob Herring Subject: [PATCH v3 3/4] dt-bindings: riscv: add new riscv,isa strings for emulators Date: Wed, 17 Aug 2022 21:12:12 +0100 Message-Id: <20220817201212.990712-4-mail@conchuod.ie> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220817201212.990712-1-mail@conchuod.ie> References: <20220817201212.990712-1-mail@conchuod.ie> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Conor Dooley The QEMU virt and spike machines currently export a riscv,isa string of "rv64imafdcsuh", While the RISC-V foundation has been ratifying a bunch of extenstions etc, the kernel has remained relatively static with what hardware is supported - but the same is not true of QEMU. Using the virt machine and running dt-validate on the dumped dtb fails, partly due to the unexpected isa string. Rather than enumerate the many many possbilities, change the pattern to a regex, with the following assumptions: - the single letter order is fixed & we don't care about things that can't even do "ima" - the standard multi letter extensions are all in a "_z" format where the first letter of is a valid single letter extension - _s & _h are used for supervisor and hyper visor extensions. - after the first two chars, a standard multi letter extension name could be an english word (ifencei anyone?) so it's not worth restricting the charset - vendor ISA extensions begind with _x and have no charset restrictions - we don't care about an e extension from an OS pov - that attempting to validate the contents of the multiletter extensions with dt-validate beyond the formatting is a futile, massively verbose or unwieldy exercise at best. - ima are required The following limitations also apply: - multi letter extension ordering is not enforced. dt-schema does not appear to allow for named match groups, so the resulting regex would be even more of a headache. - ditto for the numbered extensions. Finally, add me as a maintainer of the binding so that when it breaks in the future, I can be held responsible! Reported-by: Rob Herring Link: https://lore.kernel.org/linux-riscv/20220803170552.GA2250266-robh@ker= nel.org/ Signed-off-by: Conor Dooley Acked-by: Guo Ren Reviewed-by: Andrew Jones --- Palmer, feel free to drop the maintainer addition. I just mostly want to clean up my own mess on this when they decide to ratify more extensions & this comes back up again. --- Documentation/devicetree/bindings/riscv/cpus.yaml | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentat= ion/devicetree/bindings/riscv/cpus.yaml index 873dd12f6e89..c0e0bc5dce04 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -9,6 +9,7 @@ title: RISC-V bindings for 'cpus' DT nodes maintainers: - Paul Walmsley - Palmer Dabbelt + - Conor Dooley =20 description: | This document uses some terminology common to the RISC-V community @@ -79,9 +80,7 @@ properties: insensitive, letters in the riscv,isa string must be all lowercase to simplify parsing. $ref: "/schemas/types.yaml#/definitions/string" - enum: - - rv64imac - - rv64imafdc + pattern: ^rv(?:64|32)imaf?d?q?c?b?v?k?h?(?:(?:_[zsh][imafdqcbvksh]|_x)= (?:[a-z])+)*$ =20 # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here timebase-frequency: false --=20 2.37.1 From nobody Sat Apr 11 00:49:39 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 15377C25B08 for ; Wed, 17 Aug 2022 20:13:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241770AbiHQUNL (ORCPT ); Wed, 17 Aug 2022 16:13:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34178 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241783AbiHQUNH (ORCPT ); Wed, 17 Aug 2022 16:13:07 -0400 Received: from mail-wm1-x334.google.com (mail-wm1-x334.google.com [IPv6:2a00:1450:4864:20::334]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B6ABDA720A for ; Wed, 17 Aug 2022 13:12:49 -0700 (PDT) Received: by mail-wm1-x334.google.com with SMTP id ay39-20020a05600c1e2700b003a5503a80cfso1453035wmb.2 for ; Wed, 17 Aug 2022 13:12:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=conchuod.ie; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=bxRxSRmrcbs0t6BbgHEjmeEJnj5+oLNwKov9kosBFsg=; b=bCrCj8WGt3a7+JPz4Wr2qZDF5Ihib0g+F+IXH5UFuOmbFTl/2ohBvo+eaBcG5rFYcE JeBp5CrNuRVupkpwchSLqzMMinELgmyHdlG7Gby4T2KNUmmwkmY7XUGYNJiVa/TD597A NR9XTujvKalhqDbu1Jp4hY/ljxWSHtxlA0sp2QW4RYb2fYdpSN5uFQ9tbNbEHHxHhJER 3Dln3DsYHqEvlP6GfiVTVMoP4zR0gzA1F7aJ2ljUx5qSlse+xdciWu7oepRlc27TE07U dPla87qdJukDzfaHBgoyR2rEm4dwdJKxYv2vTJJ/0FlbjQwTvqJM+tRh0qStUKldpQZ8 sALg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=bxRxSRmrcbs0t6BbgHEjmeEJnj5+oLNwKov9kosBFsg=; b=b4idFoXznCz37TC6LnZMpPFYBEgEfyPUcHD5OBXXcTRaMHZy5Gka0iDbpxsaAOy8Ou BrIr1vFLTTXv6BlTrfAMz9wPstXVrG6q2nkZPGSMD4wwGZrp/Sc6qwknkcUAJ/zeEm0H 9oWnNmO6RUi8OvtIpou5Eg4XAMvhOWmxvfBastdIMwz5phk1g01icvrQAtCgN+TNFoo6 Tk6+8VUZWNJIHNIn+OyNXS740sHmSAHO8KOF4LqbRyZFYS/Sz05aURPRaYrRGMj/+6t1 9TzELOYQZCrtapTJhlfVN5Tkz7LH+xce46uuZtkOJiejiUIzlnXlDmPW01uEyc9+oMVX oOpw== X-Gm-Message-State: ACgBeo3FD6O7c/vXtEKQzRLpA9AEnKyIvNc7EyCpG145WlFYRMtutLy7 kW7uC103V1B2+Hj9kaLXM2Fm6Q== X-Google-Smtp-Source: AA6agR74aNlPfmPJlKcC05Y6jx7zXOmB8kg1e0yHZoCDAb3lYxnfuQYXfqqonf1zKIGzDxzQd1NAnQ== X-Received: by 2002:a7b:c402:0:b0:3a5:3c7:9741 with SMTP id k2-20020a7bc402000000b003a503c79741mr3131497wmi.72.1660767168134; Wed, 17 Aug 2022 13:12:48 -0700 (PDT) Received: from henark71.. ([109.76.58.63]) by smtp.gmail.com with ESMTPSA id i15-20020a05600c354f00b003a5dfd7e9eesm3029371wmq.44.2022.08.17.13.12.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Aug 2022 13:12:47 -0700 (PDT) From: Conor Dooley To: Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Palmer Dabbelt , Paul Walmsley , Albert Ou Cc: Daniel Lezcano , Anup Patel , Conor Dooley , Guo Ren , Sagar Kadam , Jessica Clarke , Andrew Jones , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, qemu-riscv@nongnu.org Subject: [NOT FOR INCLUSION v3 4/4] dt-bindings: riscv: isa string bonus content Date: Wed, 17 Aug 2022 21:12:13 +0100 Message-Id: <20220817201212.990712-5-mail@conchuod.ie> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220817201212.990712-1-mail@conchuod.ie> References: <20220817201212.990712-1-mail@conchuod.ie> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Conor Dooley **NOT FOR INCLUSION** I figured, sure why not add the strings for version number validation, just in case we need them in the future. The commented out string is considered by dt-schema to be "not a regex", but regex101 thinks it is... Maybe dt-schema does not support named match groups, but they are the only way that I could trivially find to make this somewhat manageable. Either way, it is permissive so it allows combinations of "M", "MpM" & no number. Not-signed-off-by: Conor Dooley --- Documentation/devicetree/bindings/riscv/cpus.yaml | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentat= ion/devicetree/bindings/riscv/cpus.yaml index c0e0bc5dce04..38a824453012 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -80,7 +80,11 @@ properties: insensitive, letters in the riscv,isa string must be all lowercase to simplify parsing. $ref: "/schemas/types.yaml#/definitions/string" - pattern: ^rv(?:64|32)imaf?d?q?c?b?v?k?h?(?:(?:_[zsh][imafdqcbvksh]|_x)= (?:[a-z])+)*$ + oneOf: + - pattern: ^rv(?:64|32)imaf?d?q?c?b?v?k?h?(?:(?:_[zsh][imafdqcbvksh]= |_x)(?:[a-z])+)*$ + - pattern: ^rv(?:64|32)(?:i\d+)(?:m\d+)(?:a\d+)(?:f\d+)?(?:d\d+)?(?:= q\d+)?(?:c\d+)?(?:b\d+)?(?:v\d+)?(?:k\d+)?(?:h\d+)?(?:(?:_[zsh][imafdqcbvks= h]|_x)(?:[a-z])+\d+)*$ + - pattern: ^rv(?:64|32)(?:i\d+p\d+)(?:m\d+p\d+)(?:a\d+p\d+)(?:f\d+p\= d+)?(?:d\d+p\d+)?(?:q\d+p\d+)?(?:c\d+p\d+)?(?:b\d+p\d+)?(?:v\d+p\d+)?(?:k\d= +p\d+)?(?:h\d+p\d+)?(?:(?:_[zsh][imafdqcbvksh]|_x)(?:[a-z])+(?:\d+p\d+))*$ +# - pattern: ^rv(?:64|32)(?:i(?(?:\d+|\d+p\d+)?)?)(?:m(?:\k= )?)(?:a(?:\k)?)(?:f(?:\k)?)?(?:d(?:\k)?)?(?:q(?:\k)?)?(= ?:c(?:\k)?)?(?:b(?:\k)?)?(?:v(?:\k)?)?(?:k(?:\k)?)?(?:h= (?:\k)?)?(?:(?:_[zsh][imafdqcbvksh]|_x)(?:[a-z])*(?:\d+|\d+p\d+)?)+$ =20 # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here timebase-frequency: false --=20 2.37.1