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[79.87.205.120]) by smtp.gmail.com with ESMTPSA id k40-20020a05600c1ca800b003a5f3de6fddsm2416533wms.25.2022.08.17.07.16.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Aug 2022 07:16:31 -0700 (PDT) From: Julien Panis To: william.gray@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, mranostay@ti.com, Julien Panis , Krzysztof Kozlowski Subject: [PATCH v5 1/3] dt-bindings: counter: add ti,am62-ecap-capture.yaml Date: Wed, 17 Aug 2022 16:16:18 +0200 Message-Id: <20220817141620.256481-2-jpanis@baylibre.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220817141620.256481-1-jpanis@baylibre.com> References: <20220817141620.256481-1-jpanis@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This commit adds a YAML binding for TI ECAP used in capture operating mode. Signed-off-by: Julien Panis Reviewed-by: Krzysztof Kozlowski --- .../counter/ti,am62-ecap-capture.yaml | 61 +++++++++++++++++++ 1 file changed, 61 insertions(+) create mode 100644 Documentation/devicetree/bindings/counter/ti,am62-ecap-= capture.yaml diff --git a/Documentation/devicetree/bindings/counter/ti,am62-ecap-capture= .yaml b/Documentation/devicetree/bindings/counter/ti,am62-ecap-capture.yaml new file mode 100644 index 000000000000..4e0b2d2b303e --- /dev/null +++ b/Documentation/devicetree/bindings/counter/ti,am62-ecap-capture.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/counter/ti,am62-ecap-capture.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments Enhanced Capture (eCAP) Module + +maintainers: + - Julien Panis + +description: | + The eCAP module resources can be used to capture timestamps + on input signal events (falling/rising edges). + +properties: + compatible: + const: ti,am62-ecap-capture + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + const: fck + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + #include + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + capture@23100000 { /* eCAP in capture mode on am62x */ + compatible =3D "ti,am62-ecap-capture"; + reg =3D <0x00 0x23100000 0x00 0x100>; + interrupts =3D ; + power-domains =3D <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 51 0>; + clock-names =3D "fck"; + }; + }; --=20 2.25.1 From nobody Sat Apr 11 02:18:40 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 457E8C25B08 for ; Wed, 17 Aug 2022 14:16:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236286AbiHQOQp (ORCPT ); Wed, 17 Aug 2022 10:16:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50310 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237302AbiHQOQi (ORCPT ); Wed, 17 Aug 2022 10:16:38 -0400 Received: from mail-wm1-x32f.google.com (mail-wm1-x32f.google.com [IPv6:2a00:1450:4864:20::32f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 10C5F5F980 for ; Wed, 17 Aug 2022 07:16:35 -0700 (PDT) Received: by mail-wm1-x32f.google.com with SMTP id c187-20020a1c35c4000000b003a30d88fe8eso1082803wma.2 for ; Wed, 17 Aug 2022 07:16:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=EnCQXIgNjt6cA5rnmWMREUxDAgbBiGVYT5YSsOL2zmY=; b=SgaTLiUsCLYvcdypKjacFEQ5CZB/2F0beLesU0gunTgGaR47x+9UoEBQHRHGKlmrtl 2dxqUzoxswuZ1SO3IW4xv7eIyG8soY9tKGU1pfYkMFoSRWZZUSbTbJp3ZAoxYo8O/2hz y7+hMjSQYd6GW8n3YR/1wzb5efO0bJSOmmsRwOs9hCjB0rWvQqeNuaO4+D7NoM5tu7hF gE1NrvNb1oc1+C2he2DTMZKPOxbqsP0mox/4tUbog18wIpUWfzNXEou+5+FVtIJZR24n jNqyMVWwQCZ3y6sFR1xlzUfHORjAoA/1hnLZTUuHi+Hb7SiEnJn4J4nETMywVTMNQtaY Qp2g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=EnCQXIgNjt6cA5rnmWMREUxDAgbBiGVYT5YSsOL2zmY=; b=2ajFpphoUZ2zQHSaNJOx7U/19q9UI3abW0+hmLwYcVnVzhQPmEkgCRoLEr3XcfeAF9 myA/Spnl7umaCDgEunzCTwojhIQtJV7DMxCs7hhhlot7SxvEP7VKLu2U8ajC/nIAKrNt w7IPI9GHT6JVp0LbfjzE3yR2ibwWyhlX77EbdAdfkrxezmOoFaw9/6Ix/1hQE6g5fKnR amfgi31f+nuxeWN7h5QoHrnq1Wd3SBkWa2+C7101uasnkeWWXUwY2IbQ5/eNfi63hz9B n2FzYjLLZ10UIy1X4tFpwWQMAyOEoXShDA1C/DaER5AjuONf/jQ34+3ACrz1b8MOezu6 12Zg== X-Gm-Message-State: ACgBeo1mHKbO079EU++LKcrUAO+T8XYOeeUiKl18Dz7PplHRipP09TMU ZYjRuAdBrvS9ZwTEhObn9b46Cw== X-Google-Smtp-Source: AA6agR44v3ca+iM7s/1610FvreyfjJ7wxkSmjn0583Ztd6iehD28eRNDX+OwmyvSeyaS6PUFnkUR4A== X-Received: by 2002:a05:600c:1e10:b0:3a5:4f31:3064 with SMTP id ay16-20020a05600c1e1000b003a54f313064mr2254190wmb.136.1660745793544; Wed, 17 Aug 2022 07:16:33 -0700 (PDT) Received: from localhost.localdomain (120.205.87.79.rev.sfr.net. [79.87.205.120]) by smtp.gmail.com with ESMTPSA id k40-20020a05600c1ca800b003a5f3de6fddsm2416533wms.25.2022.08.17.07.16.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Aug 2022 07:16:32 -0700 (PDT) From: Julien Panis To: william.gray@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, mranostay@ti.com, Julien Panis Subject: [PATCH v5 2/3] Documentation: ABI: sysfs-bus-counter: add capture items Date: Wed, 17 Aug 2022 16:16:19 +0200 Message-Id: <20220817141620.256481-3-jpanis@baylibre.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220817141620.256481-1-jpanis@baylibre.com> References: <20220817141620.256481-1-jpanis@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This commit adds capture items to counter ABI file (e.g. TI ECAP used in capture operating mode). Signed-off-by: Julien Panis --- Documentation/ABI/testing/sysfs-bus-counter | 49 +++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-bus-counter b/Documentation/AB= I/testing/sysfs-bus-counter index 06c2b3e27e0b..52ddec7cc76a 100644 --- a/Documentation/ABI/testing/sysfs-bus-counter +++ b/Documentation/ABI/testing/sysfs-bus-counter @@ -203,6 +203,24 @@ Description: both edges: Any state transition. =20 +What: /sys/bus/counter/devices/counterX/countY/count_cumul +KernelVersion: 6.0 +Contact: jpanis@baylibre.com +Description: + Read-only attribute that indicates the raw cumulated count + since count Y start, computed as follow: + count_cumul =3D (max_counter_val + 1) * nb_counter_overflows + +What: /sys/bus/counter/devices/counterX/countY/captureZ +KernelVersion: 6.0 +Contact: jpanis@baylibre.com +Description: + Read-only attributes that indicate the last raw timestamp captured + for the respective capture Z register. + Raw timestamp can be converted to nanoseconds as follow: + time_ns =3D 10^9 * (captureZ + count_cumul) / frequency + count_cumul and frequency parameters are described in this document. + What: /sys/bus/counter/devices/counterX/countY/ceiling_component_id What: /sys/bus/counter/devices/counterX/countY/floor_component_id What: /sys/bus/counter/devices/counterX/countY/count_mode_component_id @@ -213,6 +231,8 @@ What: /sys/bus/counter/devices/counterX/countY/prescal= er_component_id What: /sys/bus/counter/devices/counterX/countY/preset_component_id What: /sys/bus/counter/devices/counterX/countY/preset_enable_component_id What: /sys/bus/counter/devices/counterX/countY/signalZ_action_component_id +What: /sys/bus/counter/devices/counterX/countY/count_cumul_component_id +What: /sys/bus/counter/devices/counterX/countY/captureZ_component_id What: /sys/bus/counter/devices/counterX/signalY/cable_fault_component_id What: /sys/bus/counter/devices/counterX/signalY/cable_fault_enable_compon= ent_id What: /sys/bus/counter/devices/counterX/signalY/filter_clock_prescaler_co= mponent_id @@ -345,3 +365,32 @@ Description: via index_polarity. The index function (as enabled via preset_enable) is performed synchronously with the quadrature clock on the active level of the index input. + +What: /sys/bus/counter/devices/counterX/signalY/polarityZ +KernelVersion: 6.0 +Contact: jpanis@baylibre.com +Description: + Capture modules include N timestamp capture registers. + For all N sequenced timestamp capture events + (1->2->3->...->N->1->...), edge polarity can be selected. + The following polarities are available: + + rising edge: + Low state transitions to high state. + + falling edge: + High state transitions to low state. + +What: /sys/bus/counter/devices/counterX/signalY/polarityZ_available +KernelVersion: 6.0 +Contact: jpanis@baylibre.com +Description: + Discrete set of available values for the respective polarity Z + configuration are listed in this file. Values are delimited by + newline characters. + +What: /sys/bus/counter/devices/counterX/signalY/frequency +KernelVersion: 6.0 +Contact: jpanis@baylibre.com +Description: + Read-only attribute that indicates the signal Y frequency, in Hz. --=20 2.25.1 From nobody Sat Apr 11 02:18:40 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 427D9C25B08 for ; Wed, 17 Aug 2022 14:16:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240085AbiHQOQu (ORCPT ); Wed, 17 Aug 2022 10:16:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50310 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240051AbiHQOQj (ORCPT ); Wed, 17 Aug 2022 10:16:39 -0400 Received: from mail-wm1-x335.google.com (mail-wm1-x335.google.com [IPv6:2a00:1450:4864:20::335]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A27795F9BB for ; Wed, 17 Aug 2022 07:16:36 -0700 (PDT) Received: by mail-wm1-x335.google.com with SMTP id ay39-20020a05600c1e2700b003a5503a80cfso1013087wmb.2 for ; Wed, 17 Aug 2022 07:16:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=3OHZoQAWriB0EYCBRV+lZ+7h9MLE8qNIp+Fsdg0OJk4=; b=vwPmRRvl9TW4P+CpmKNlG5J677BN+gOy4339Wgp9XgFGI9CXrl1YUqc+wKl9USr/OK vMseQcS/0DYyQcAS357eDZXphcTcpUGUiuYW2vRMI/m0cP72pRRRRzafMUKCcAJRHK/V 8iRPstqDktcE1tx4iEKqfr8Z9xuJsrDb9n1SmkC5YlbvP+1cBiBCiGVVBhGh1MyP9jgS ZGaZhMeE4ZlY4AKp92XZXzeuK5L2801CBTOs6Kf0MhTIHWXYOG/uUJD6BVqXHIYqSlwH 9mTWmExvZHEYWFgiOADsZ3kHN3ooks59uqkNZB/IxVsOEBO/h0xajhy1X25sEOIgzXOk HDHw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=3OHZoQAWriB0EYCBRV+lZ+7h9MLE8qNIp+Fsdg0OJk4=; b=ofLPZ8mYp2HJBMTs4NMbhyzJ571m4Ak9K2C5Pn8U/6EwKpfEDq84UILoX72iLwiIQD IARq8O6/MDRxRH+gVcdX2cXAYUvufLrfOpiyo0MgPSNX5R2nk6wVemDFxXAc/KuF4wCk oGL0MZFoKPVjRzH1SBL1V1NuQl8EEK4PiCevwrZoWBWfjMc1vJ3PybD0usgG5s3OiTmW frrQIhHWnjFQtb1QpzGgUwLAz0HoiR7P1fIYhR8cUUENrj3MjDrBHlCJmdmwHby98p7K H26dDFQhsfgY7xeS6Ku+smZbOWVnmAic3oeaNHvkfwpdbwnrWza11F/k/0vmSvm1cFsB LoSQ== X-Gm-Message-State: ACgBeo2GutXewv1vEUZlUqeIMrVG51cm0CvL2xpMxP1razJW7qzi1j8e OWRRU8kbZRRRUCIWoX311tO9QzWKDAlqeQ== X-Google-Smtp-Source: AA6agR6GGZhpS+UhHy1CIghQQ8FI65FPMIEY3Jg88sr6MepDNtiQ4KxG2JVUZIFI7xfLr/A6pLuRCg== X-Received: by 2002:a1c:f209:0:b0:3a4:f42c:9ffb with SMTP id s9-20020a1cf209000000b003a4f42c9ffbmr2344739wmc.62.1660745794959; Wed, 17 Aug 2022 07:16:34 -0700 (PDT) Received: from localhost.localdomain (120.205.87.79.rev.sfr.net. [79.87.205.120]) by smtp.gmail.com with ESMTPSA id k40-20020a05600c1ca800b003a5f3de6fddsm2416533wms.25.2022.08.17.07.16.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Aug 2022 07:16:34 -0700 (PDT) From: Julien Panis To: william.gray@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, mranostay@ti.com, Julien Panis Subject: [PATCH v5 3/3] counter: ti-ecap-capture: capture driver support for ECAP Date: Wed, 17 Aug 2022 16:16:20 +0200 Message-Id: <20220817141620.256481-4-jpanis@baylibre.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220817141620.256481-1-jpanis@baylibre.com> References: <20220817141620.256481-1-jpanis@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" ECAP hardware on TI AM62x SoC supports capture feature. It can be used to timestamp events (falling/rising edges) detected on signal input pin. This commit adds capture driver support for ECAP hardware on AM62x SoC. In the ECAP hardware, capture pin can also be configured to be in PWM mode. Current implementation only supports capture operating mode. Hardware also supports timebase sync between multiple instances, but this driver supports simple independent capture functionality. Signed-off-by: Julien Panis --- drivers/counter/Kconfig | 15 + drivers/counter/Makefile | 1 + drivers/counter/ti-ecap-capture.c | 624 ++++++++++++++++++++++++++++++ include/uapi/linux/counter.h | 2 + 4 files changed, 642 insertions(+) create mode 100644 drivers/counter/ti-ecap-capture.c diff --git a/drivers/counter/Kconfig b/drivers/counter/Kconfig index 5edd155f1911..08235268af0b 100644 --- a/drivers/counter/Kconfig +++ b/drivers/counter/Kconfig @@ -101,4 +101,19 @@ config INTEL_QEP To compile this driver as a module, choose M here: the module will be called intel-qep. =20 +config TI_ECAP_CAPTURE + tristate "TI eCAP capture driver" + depends on ARCH_OMAP2PLUS || ARCH_DAVINCI_DA8XX || ARCH_KEYSTONE || ARCH_= K3 || COMPILE_TEST + depends on HAS_IOMEM + select REGMAP_MMIO + help + Select this option to enable the Texas Instruments Enhanced Capture + (eCAP) driver in input mode. + + It can be used to timestamp events (falling/rising edges) detected + on signal input pin. + + To compile this driver as a module, choose M here: the module + will be called ti-ecap-capture. + endif # COUNTER diff --git a/drivers/counter/Makefile b/drivers/counter/Makefile index 8fde6c100ebc..b9a369e0d4fc 100644 --- a/drivers/counter/Makefile +++ b/drivers/counter/Makefile @@ -14,3 +14,4 @@ obj-$(CONFIG_TI_EQEP) +=3D ti-eqep.o obj-$(CONFIG_FTM_QUADDEC) +=3D ftm-quaddec.o obj-$(CONFIG_MICROCHIP_TCB_CAPTURE) +=3D microchip-tcb-capture.o obj-$(CONFIG_INTEL_QEP) +=3D intel-qep.o +obj-$(CONFIG_TI_ECAP_CAPTURE) +=3D ti-ecap-capture.o diff --git a/drivers/counter/ti-ecap-capture.c b/drivers/counter/ti-ecap-ca= pture.c new file mode 100644 index 000000000000..b00ddf122bbd --- /dev/null +++ b/drivers/counter/ti-ecap-capture.c @@ -0,0 +1,624 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * ECAP Capture driver + * + * Copyright (C) 2022 Julien Panis + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define ECAP_DRV_NAME "ecap" + +/* ECAP event IDs */ +enum ecap_event_id { + /* Capture events */ + ECAP_CEVT1, + ECAP_CEVT2, + ECAP_CEVT3, + ECAP_CEVT4, + /* Counter overflow event */ + ECAP_CNTOVF, + /* Helpers for capture events */ + ECAP_CEVT_LAST =3D ECAP_CEVT4, + ECAP_NB_CEVT =3D ECAP_CEVT_LAST + 1, + /* Helpers for all events */ + ECAP_EVT_LAST =3D ECAP_CNTOVF, + ECAP_NB_EVT =3D ECAP_EVT_LAST + 1, +}; + +/* Registers */ +#define ECAP_NB_CAP ECAP_NB_CEVT + +#define ECAP_TSCNT_REG 0x00 + +#define ECAP_CAP_REG(i) (((i) << 2) + 0x08) + +#define ECAP_ECCTL_REG 0x28 +#define ECAP_CAPPOL_BIT(i) BIT((i) << 1) +#define ECAP_EV_MODE_MASK GENMASK(7, 0) +#define ECAP_CAPLDEN_BIT BIT(8) +#define ECAP_CONT_ONESHT_BIT BIT(16) +#define ECAP_STOPVALUE_MASK GENMASK(18, 17) +#define ECAP_REARM_RESET_BIT BIT(19) +#define ECAP_TSCNTSTP_BIT BIT(20) +#define ECAP_SYNCO_DIS_MASK GENMASK(23, 22) +#define ECAP_CAP_APWM_BIT BIT(25) +#define ECAP_ECCTL_EN_MASK (ECAP_CAPLDEN_BIT | ECAP_TSCNTSTP_BIT) +#define ECAP_ECCTL_CFG_MASK (ECAP_SYNCO_DIS_MASK | ECAP_STOPVALUE_MASK \ + | ECAP_ECCTL_EN_MASK | ECAP_REARM_RESET_BIT \ + | ECAP_CAP_APWM_BIT | ECAP_CONT_ONESHT_BIT) + +#define ECAP_ECINT_EN_FLG_REG 0x2c +#define ECAP_EVT_EN_MASK GENMASK(ECAP_NB_EVT, ECAP_NB_CEVT) +#define ECAP_EVT_FLG_BIT(i) BIT((i) + 17) + +#define ECAP_ECINT_CLR_FRC_REG 0x30 +#define ECAP_INT_CLR_BIT BIT(0) +#define ECAP_EVT_CLR_BIT(i) BIT((i) + 1) +#define ECAP_EVT_CLR_MASK GENMASK(ECAP_NB_EVT, 0) + +#define ECAP_PID_REG 0x5c + +/* + * Event modes + * One bit for each CAPx register : 1 =3D falling edge / 0 =3D rising edge + * e.g. mode =3D 13 =3D 0xd =3D 0b1101 + * -> falling edge for CAP1-3-4 / rising edge for CAP2 + */ +#define ECAP_EV_MODE_BIT(i) BIT(i) + +/* ECAP signals */ +#define ECAP_INPUT_SIG 0 +#define ECAP_CLOCK_SIG 1 + +#define ECAP_CHAN 0 + +static const struct regmap_config ecap_cnt_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D ECAP_PID_REG, +}; + +/** + * struct ecap_cnt_dev - device private data structure + * @enabled: device state + * @clk: device clock + * @clk_rate: device clock rate + * @regmap: device register map + * @nb_ovf: number of overflows since capture start + * @pm_ctx: device context for PM operations + */ +struct ecap_cnt_dev { + bool enabled; + struct clk *clk; + unsigned long clk_rate; + struct regmap *regmap; + atomic_t nb_ovf; + struct { + u8 ev_mode; + unsigned int time_cntr; + } pm_ctx; +}; + +static u8 ecap_cnt_capture_get_evmode(struct counter_device *counter) +{ + struct ecap_cnt_dev *ecap_dev =3D counter_priv(counter); + u8 ev_mode =3D 0; + unsigned int regval; + int i; + + pm_runtime_get_sync(counter->parent); + regmap_read(ecap_dev->regmap, ECAP_ECCTL_REG, ®val); + pm_runtime_put_sync(counter->parent); + + for (i =3D 0 ; i < ECAP_NB_CAP ; i++) { + if (regval & ECAP_CAPPOL_BIT(i)) + ev_mode |=3D ECAP_EV_MODE_BIT(i); + } + + return ev_mode; +} + +static void ecap_cnt_capture_set_evmode(struct counter_device *counter, u8= ev_mode) +{ + struct ecap_cnt_dev *ecap_dev =3D counter_priv(counter); + unsigned int regval =3D 0; + int i; + + for (i =3D 0 ; i < ECAP_NB_CAP ; i++) { + if (ev_mode & ECAP_EV_MODE_BIT(i)) + regval |=3D ECAP_CAPPOL_BIT(i); + } + + pm_runtime_get_sync(counter->parent); + regmap_update_bits(ecap_dev->regmap, ECAP_ECCTL_REG, ECAP_EV_MODE_MASK, r= egval); + pm_runtime_put_sync(counter->parent); +} + +static void ecap_cnt_capture_enable(struct counter_device *counter, bool r= earm) +{ + struct ecap_cnt_dev *ecap_dev =3D counter_priv(counter); + unsigned int regval; + + pm_runtime_get_sync(counter->parent); + + /* Enable interrupts on events */ + regmap_update_bits(ecap_dev->regmap, ECAP_ECINT_EN_FLG_REG, + ECAP_EVT_EN_MASK, ECAP_EVT_EN_MASK); + + /* Run counter */ + regval =3D ECAP_SYNCO_DIS_MASK | ECAP_STOPVALUE_MASK | ECAP_ECCTL_EN_MASK; + if (rearm) { + atomic_set(&ecap_dev->nb_ovf, 0); + regmap_write(ecap_dev->regmap, ECAP_TSCNT_REG, 0); + regval |=3D ECAP_REARM_RESET_BIT; + } + regmap_update_bits(ecap_dev->regmap, ECAP_ECCTL_REG, ECAP_ECCTL_CFG_MASK,= regval); +} + +static void ecap_cnt_capture_disable(struct counter_device *counter) +{ + struct ecap_cnt_dev *ecap_dev =3D counter_priv(counter); + + /* Disable interrupts on events */ + regmap_update_bits(ecap_dev->regmap, ECAP_ECINT_EN_FLG_REG, ECAP_EVT_EN_M= ASK, 0); + + /* Stop counter */ + regmap_update_bits(ecap_dev->regmap, ECAP_ECCTL_REG, ECAP_ECCTL_EN_MASK, = 0); + + pm_runtime_put_sync(counter->parent); +} + +static int ecap_cnt_count_get_val(struct counter_device *counter, unsigned= int reg, u64 *val) +{ + struct ecap_cnt_dev *ecap_dev =3D counter_priv(counter); + unsigned int regval; + + pm_runtime_get_sync(counter->parent); + regmap_read(ecap_dev->regmap, reg, ®val); + pm_runtime_put_sync(counter->parent); + + *val =3D regval; + + return 0; +} + +static inline int ecap_cnt_count_read(struct counter_device *counter, + struct counter_count *count, + u64 *val) +{ + return ecap_cnt_count_get_val(counter, ECAP_TSCNT_REG, val); +} + +static int ecap_cnt_function_read(struct counter_device *counter, + struct counter_count *count, + enum counter_function *function) +{ + *function =3D COUNTER_FUNCTION_INCREASE; + + return 0; +} + +static int ecap_cnt_action_read(struct counter_device *counter, + struct counter_count *count, + struct counter_synapse *synapse, + enum counter_synapse_action *action) +{ + *action =3D COUNTER_SYNAPSE_ACTION_NONE; + + return 0; +} + +static int ecap_cnt_watch_validate(struct counter_device *counter, + const struct counter_watch *watch) +{ + return (watch->channel =3D=3D ECAP_CHAN && + (watch->event =3D=3D COUNTER_EVENT_CAPTURE || + watch->event =3D=3D COUNTER_EVENT_OVERFLOW)) ? 0 : -EINVAL; +} + +static int ecap_cnt_enable_read(struct counter_device *counter, + struct counter_count *count, + u8 *enable) +{ + struct ecap_cnt_dev *ecap_dev =3D counter_priv(counter); + + *enable =3D ecap_dev->enabled; + + return 0; +} + +static int ecap_cnt_enable_write(struct counter_device *counter, + struct counter_count *count, + u8 enable) +{ + struct ecap_cnt_dev *ecap_dev =3D counter_priv(counter); + + if (enable =3D=3D ecap_dev->enabled) + return 0; + if (enable) + ecap_cnt_capture_enable(counter, true); + else + ecap_cnt_capture_disable(counter); + ecap_dev->enabled =3D enable; + + return 0; +} + +static int ecap_cnt_cap_get_pol(struct counter_device *counter, + struct counter_signal *signal, + u8 inst, u32 *pol) +{ + struct ecap_cnt_dev *ecap_dev =3D counter_priv(counter); + + pm_runtime_get_sync(counter->parent); + *pol =3D regmap_test_bits(ecap_dev->regmap, ECAP_ECCTL_REG, ECAP_CAPPOL_B= IT(inst)); + pm_runtime_put_sync(counter->parent); + + return 0; +} + +static int ecap_cnt_cap_set_pol(struct counter_device *counter, + struct counter_signal *signal, + u8 inst, u32 pol) +{ + struct ecap_cnt_dev *ecap_dev =3D counter_priv(counter); + + if (ecap_dev->enabled) + return -EBUSY; + if (pol > 1) + return -EINVAL; + + pm_runtime_get_sync(counter->parent); + if (pol) + regmap_set_bits(ecap_dev->regmap, ECAP_ECCTL_REG, ECAP_CAPPOL_BIT(inst)); + else + regmap_clear_bits(ecap_dev->regmap, ECAP_ECCTL_REG, ECAP_CAPPOL_BIT(inst= )); + pm_runtime_put_sync(counter->parent); + + return 0; +} + +static inline int ecap_cnt_cap_read(struct counter_device *counter, + struct counter_count *count, + u8 inst, u64 *cap) +{ + return ecap_cnt_count_get_val(counter, ECAP_CAP_REG(inst), cap); +} + +#define ECAP_CAP_GET_POL(i) int ecap_cnt_cap##i##_get_pol(struct counter_d= evice *counter, \ + struct counter_signal *signal, \ + u32 *pol) \ +{ \ + return ecap_cnt_cap_get_pol(counter, signal, (i) - 1, pol); \ +} + +#define ECAP_CAP_SET_POL(i) int ecap_cnt_cap##i##_set_pol(struct counter_d= evice *counter, \ + struct counter_signal *signal, \ + u32 pol) \ +{ \ + return ecap_cnt_cap_set_pol(counter, signal, (i) - 1, pol); \ +} + +#define ECAP_CAP_READ(i) int ecap_cnt_cap##i##_read(struct counter_device = *counter, \ + struct counter_count *count, \ + u64 *cap) \ +{ \ + return ecap_cnt_cap_read(counter, count, (i) - 1, cap); \ +} + +static inline ECAP_CAP_GET_POL(1) +static inline ECAP_CAP_GET_POL(2) +static inline ECAP_CAP_GET_POL(3) +static inline ECAP_CAP_GET_POL(4) +static inline ECAP_CAP_SET_POL(1) +static inline ECAP_CAP_SET_POL(2) +static inline ECAP_CAP_SET_POL(3) +static inline ECAP_CAP_SET_POL(4) +static inline ECAP_CAP_READ(1) +static inline ECAP_CAP_READ(2) +static inline ECAP_CAP_READ(3) +static inline ECAP_CAP_READ(4) + +static int ecap_cnt_count_cumul_read(struct counter_device *counter, + struct counter_count *count, u64 *val) +{ + struct ecap_cnt_dev *ecap_dev =3D counter_priv(counter); + + *val =3D ((u64)U32_MAX + 1) * atomic_read(&ecap_dev->nb_ovf); + + return 0; +} + +static int ecap_cnt_clk_get_freq(struct counter_device *counter, + struct counter_signal *signal, u64 *freq) +{ + struct ecap_cnt_dev *ecap_dev =3D counter_priv(counter); + + *freq =3D ecap_dev->clk_rate; + + return 0; +} + +static const struct counter_ops ecap_cnt_ops =3D { + .count_read =3D ecap_cnt_count_read, + .function_read =3D ecap_cnt_function_read, + .action_read =3D ecap_cnt_action_read, + .watch_validate =3D ecap_cnt_watch_validate, +}; + +static const enum counter_function ecap_cnt_functions[] =3D { + COUNTER_FUNCTION_INCREASE, +}; + +static const enum counter_synapse_action ecap_cnt_actions[] =3D { + COUNTER_SYNAPSE_ACTION_NONE, +}; + +static const char *const ecap_cnt_cap_polarities[] =3D { + "rising edge", + "falling edge", +}; + +static DEFINE_COUNTER_ENUM(ecap_cnt_cap_avail_pol, ecap_cnt_cap_polarities= ); + +static struct counter_comp ecap_cnt_signal_ext[] =3D { + COUNTER_COMP_SIGNAL_ENUM("polarity1", ecap_cnt_cap1_get_pol, + ecap_cnt_cap1_set_pol, ecap_cnt_cap_avail_pol), + COUNTER_COMP_SIGNAL_ENUM("polarity2", ecap_cnt_cap2_get_pol, + ecap_cnt_cap2_set_pol, ecap_cnt_cap_avail_pol), + COUNTER_COMP_SIGNAL_ENUM("polarity3", ecap_cnt_cap3_get_pol, + ecap_cnt_cap3_set_pol, ecap_cnt_cap_avail_pol), + COUNTER_COMP_SIGNAL_ENUM("polarity4", ecap_cnt_cap4_get_pol, + ecap_cnt_cap4_set_pol, ecap_cnt_cap_avail_pol), +}; + +static struct counter_comp ecap_cnt_clock_ext[] =3D { + COUNTER_COMP_SIGNAL_U64("frequency", ecap_cnt_clk_get_freq, NULL), +}; + +static struct counter_signal ecap_cnt_signals[] =3D { + { + .id =3D ECAP_INPUT_SIG, + .name =3D "ECAP Input Signal", + .ext =3D ecap_cnt_signal_ext, + .num_ext =3D ARRAY_SIZE(ecap_cnt_signal_ext), + }, + { + .id =3D ECAP_CLOCK_SIG, + .name =3D "ECAP Clock Signal", + .ext =3D ecap_cnt_clock_ext, + .num_ext =3D ARRAY_SIZE(ecap_cnt_clock_ext), + }, +}; + +static struct counter_synapse ecap_cnt_synapses[] =3D { + { + .actions_list =3D ecap_cnt_actions, + .num_actions =3D ARRAY_SIZE(ecap_cnt_actions), + .signal =3D &ecap_cnt_signals[ECAP_INPUT_SIG], + }, + { + .actions_list =3D ecap_cnt_actions, + .num_actions =3D ARRAY_SIZE(ecap_cnt_actions), + .signal =3D &ecap_cnt_signals[ECAP_CLOCK_SIG], + }, +}; + +static struct counter_comp ecap_cnt_count_ext[] =3D { + COUNTER_COMP_COUNT_U64("capture1", ecap_cnt_cap1_read, NULL), + COUNTER_COMP_COUNT_U64("capture2", ecap_cnt_cap2_read, NULL), + COUNTER_COMP_COUNT_U64("capture3", ecap_cnt_cap3_read, NULL), + COUNTER_COMP_COUNT_U64("capture4", ecap_cnt_cap4_read, NULL), + COUNTER_COMP_COUNT_U64("count_cumul", ecap_cnt_count_cumul_read, NULL), + COUNTER_COMP_ENABLE(ecap_cnt_enable_read, ecap_cnt_enable_write), +}; + +static struct counter_count ecap_cnt_counts[] =3D { + { + .id =3D 0, + .name =3D "ECAP Timestamp Counter", + .functions_list =3D ecap_cnt_functions, + .num_functions =3D ARRAY_SIZE(ecap_cnt_functions), + .synapses =3D ecap_cnt_synapses, + .num_synapses =3D ARRAY_SIZE(ecap_cnt_synapses), + .ext =3D ecap_cnt_count_ext, + .num_ext =3D ARRAY_SIZE(ecap_cnt_count_ext), + }, +}; + +static irqreturn_t ecap_cnt_isr(int irq, void *dev_id) +{ + struct counter_device *counter_dev =3D dev_id; + struct ecap_cnt_dev *ecap_dev =3D counter_priv(counter_dev); + unsigned int clr =3D 0; + unsigned int flg; + int i; + + regmap_read(ecap_dev->regmap, ECAP_ECINT_EN_FLG_REG, &flg); + + for (i =3D ECAP_CEVT_LAST ; i <=3D ECAP_EVT_LAST ; i++) { + if (flg & ECAP_EVT_FLG_BIT(i)) { + if (i !=3D ECAP_CNTOVF) { + /* Input signal edge detected on last CAP (CAP4) */ + counter_push_event(counter_dev, COUNTER_EVENT_CAPTURE, ECAP_CHAN); + } else { + /* Counter overflow */ + counter_push_event(counter_dev, COUNTER_EVENT_OVERFLOW, ECAP_CHAN); + atomic_inc(&ecap_dev->nb_ovf); + } + + clr |=3D ECAP_EVT_CLR_BIT(i); + } + } + + clr |=3D ECAP_INT_CLR_BIT; + regmap_update_bits(ecap_dev->regmap, ECAP_ECINT_CLR_FRC_REG, ECAP_EVT_CLR= _MASK, clr); + + return IRQ_HANDLED; +} + +static void ecap_cnt_pm_disable(void *dev) +{ + pm_runtime_disable(dev); +} + +static int ecap_cnt_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct ecap_cnt_dev *ecap_dev; + struct counter_device *counter_dev; + void __iomem *mmio_base; + int ret; + + counter_dev =3D devm_counter_alloc(dev, sizeof(*ecap_dev)); + if (IS_ERR(counter_dev)) + return PTR_ERR(counter_dev); + + counter_dev->name =3D ECAP_DRV_NAME; + counter_dev->parent =3D dev; + counter_dev->ops =3D &ecap_cnt_ops; + counter_dev->signals =3D ecap_cnt_signals; + counter_dev->num_signals =3D ARRAY_SIZE(ecap_cnt_signals); + counter_dev->counts =3D ecap_cnt_counts; + counter_dev->num_counts =3D ARRAY_SIZE(ecap_cnt_counts); + + ecap_dev =3D counter_priv(counter_dev); + + ecap_dev->clk =3D devm_clk_get_enabled(dev, "fck"); + if (IS_ERR(ecap_dev->clk)) + return dev_err_probe(dev, PTR_ERR(ecap_dev->clk), "failed to get clock\n= "); + + ecap_dev->clk_rate =3D clk_get_rate(ecap_dev->clk); + if (!ecap_dev->clk_rate) { + dev_err(dev, "failed to get clock rate\n"); + return -EINVAL; + } + + mmio_base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(mmio_base)) + return PTR_ERR(mmio_base); + + ecap_dev->regmap =3D devm_regmap_init_mmio(dev, mmio_base, &ecap_cnt_regm= ap_config); + if (IS_ERR(ecap_dev->regmap)) + return dev_err_probe(dev, PTR_ERR(ecap_dev->regmap), "failed to init reg= map\n"); + + ret =3D platform_get_irq(pdev, 0); + if (ret < 0) + return dev_err_probe(dev, ret, "failed to get irq\n"); + + ret =3D devm_request_irq(dev, ret, ecap_cnt_isr, 0, pdev->name, counter_d= ev); + if (ret) + return dev_err_probe(dev, ret, "failed to request irq\n"); + + platform_set_drvdata(pdev, counter_dev); + + pm_runtime_enable(dev); + + /* Register a cleanup callback to care for disabling PM */ + ret =3D devm_add_action_or_reset(dev, ecap_cnt_pm_disable, dev); + if (ret) + return dev_err_probe(dev, ret, "failed to add pm disable action\n"); + + ecap_dev->enabled =3D 0; + ecap_cnt_capture_set_evmode(counter_dev, 0); + + ret =3D devm_counter_add(dev, counter_dev); + if (ret) + return dev_err_probe(dev, ret, "failed to add counter\n"); + + return 0; +} + +static int ecap_cnt_remove(struct platform_device *pdev) +{ + struct counter_device *counter_dev =3D platform_get_drvdata(pdev); + struct ecap_cnt_dev *ecap_dev =3D counter_priv(counter_dev); + + if (ecap_dev->enabled) + ecap_cnt_capture_disable(counter_dev); + + return 0; +} + +static int ecap_cnt_suspend(struct device *dev) +{ + struct counter_device *counter_dev =3D dev_get_drvdata(dev); + struct ecap_cnt_dev *ecap_dev =3D counter_priv(counter_dev); + + /* If eCAP is running, stop capture then save timestamp counter */ + if (ecap_dev->enabled) { + /* + * Disabling capture has the following effects: + * - interrupts are disabled + * - loading of capture registers is disabled + * - timebase counter is stopped + */ + ecap_cnt_capture_disable(counter_dev); + + pm_runtime_get_sync(dev); + regmap_read(ecap_dev->regmap, ECAP_TSCNT_REG, &ecap_dev->pm_ctx.time_cnt= r); + pm_runtime_put_sync(dev); + } + + ecap_dev->pm_ctx.ev_mode =3D ecap_cnt_capture_get_evmode(counter_dev); + + clk_disable(ecap_dev->clk); + + return 0; +} + +static int ecap_cnt_resume(struct device *dev) +{ + struct counter_device *counter_dev =3D dev_get_drvdata(dev); + struct ecap_cnt_dev *ecap_dev =3D counter_priv(counter_dev); + + clk_enable(ecap_dev->clk); + + ecap_cnt_capture_set_evmode(counter_dev, ecap_dev->pm_ctx.ev_mode); + + /* If eCAP was running, restore timestamp counter then run capture */ + if (ecap_dev->enabled) { + pm_runtime_get_sync(dev); + regmap_write(ecap_dev->regmap, ECAP_TSCNT_REG, ecap_dev->pm_ctx.time_cnt= r); + pm_runtime_put_sync(dev); + + ecap_cnt_capture_enable(counter_dev, false); + } + + return 0; +} + +static DEFINE_SIMPLE_DEV_PM_OPS(ecap_cnt_pm_ops, ecap_cnt_suspend, ecap_cn= t_resume); + +static const struct of_device_id ecap_cnt_of_match[] =3D { + { .compatible =3D "ti,am62-ecap-capture" }, + {}, +}; +MODULE_DEVICE_TABLE(of, ecap_cnt_of_match); + +static struct platform_driver ecap_cnt_driver =3D { + .probe =3D ecap_cnt_probe, + .remove =3D ecap_cnt_remove, + .driver =3D { + .name =3D "ecap-capture", + .of_match_table =3D ecap_cnt_of_match, + .pm =3D pm_sleep_ptr(&ecap_cnt_pm_ops), + }, +}; +module_platform_driver(ecap_cnt_driver); + +MODULE_DESCRIPTION("ECAP Capture driver"); +MODULE_AUTHOR("Julien Panis "); +MODULE_LICENSE("GPL"); diff --git a/include/uapi/linux/counter.h b/include/uapi/linux/counter.h index 96c5ffd368ad..4c5372c6f2a3 100644 --- a/include/uapi/linux/counter.h +++ b/include/uapi/linux/counter.h @@ -63,6 +63,8 @@ enum counter_event_type { COUNTER_EVENT_INDEX, /* State of counter is changed */ COUNTER_EVENT_CHANGE_OF_STATE, + /* Count value is captured */ + COUNTER_EVENT_CAPTURE, }; =20 /** --=20 2.25.1