From nobody Sat Apr 11 00:43:19 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E0B51C25B08 for ; Wed, 17 Aug 2022 11:23:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239034AbiHQLXL (ORCPT ); Wed, 17 Aug 2022 07:23:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38850 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238472AbiHQLXI (ORCPT ); Wed, 17 Aug 2022 07:23:08 -0400 Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6B053B20 for ; Wed, 17 Aug 2022 04:23:06 -0700 (PDT) Received: from ip5b412258.dynamic.kabel-deutschland.de ([91.65.34.88] helo=phil.lan) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1oOH8X-000217-JK; Wed, 17 Aug 2022 13:23:01 +0200 From: Heiko Stuebner To: atishp@atishpatra.org, anup@brainfault.org, will@kernel.org, mark.rutland@arm.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, philipp.tomsich@vrull.eu, cmuellner@linux.com, samuel@sholland.org, guoren@kernel.org, Heiko Stuebner Subject: [PATCH RESEND] drivers/perf: riscv_pmu_sbi: add support for PMU variant on T-Head C9xx cores Date: Wed, 17 Aug 2022 13:22:59 +0200 Message-Id: <20220817112259.745877-1-heiko@sntech.de> X-Mailer: git-send-email 2.35.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" With the T-HEAD C9XX cores being designed before or during the ratification to the SSCOFPMF extension, they implement functionality very similar but not equal to it. So add some adaptions to allow the C9XX to still handle its PMU through the regular SBI PMU interface instead of defining new interfaces or drivers. To work properly, this requires a matching change in SBI, though the actual interface between kernel and SBI does not change. The main differences are a the overflow CSR and irq number. Signed-off-by: Heiko Stuebner --- Resend, because I missed two important people in my Cc list, sorry. openSBI-patch-series can be found on http://lists.infradead.org/pipermail/opensbi/2022-August/003259.html drivers/perf/riscv_pmu_sbi.c | 27 +++++++++++++++++++-------- 1 file changed, 19 insertions(+), 8 deletions(-) diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index 6f6681bbfd36..4589166e0de4 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -41,12 +41,17 @@ static const struct attribute_group *riscv_pmu_attr_gro= ups[] =3D { NULL, }; =20 +#define THEAD_C9XX_RV_IRQ_PMU 17 +#define THEAD_C9XX_CSR_SCOUNTEROF 0x5c5 + /* * RISC-V doesn't have hetergenous harts yet. This need to be part of * per_cpu in case of harts with different pmu counters */ static union sbi_pmu_ctr_info *pmu_ctr_list; +static unsigned int riscv_pmu_irq_num; static unsigned int riscv_pmu_irq; +static bool is_thead_c9xx; =20 struct sbi_pmu_event_data { union { @@ -575,7 +580,7 @@ static irqreturn_t pmu_sbi_ovf_handler(int irq, void *d= ev) fidx =3D find_first_bit(cpu_hw_evt->used_hw_ctrs, RISCV_MAX_COUNTERS); event =3D cpu_hw_evt->events[fidx]; if (!event) { - csr_clear(CSR_SIP, SIP_LCOFIP); + csr_clear(CSR_SIP, BIT(riscv_pmu_irq_num)); return IRQ_NONE; } =20 @@ -583,13 +588,14 @@ static irqreturn_t pmu_sbi_ovf_handler(int irq, void = *dev) pmu_sbi_stop_hw_ctrs(pmu); =20 /* Overflow status register should only be read after counter are stopped= */ - overflow =3D csr_read(CSR_SSCOUNTOVF); + overflow =3D !is_thead_c9xx ? csr_read(CSR_SSCOUNTOVF) + : csr_read(THEAD_C9XX_CSR_SCOUNTEROF); =20 /* * Overflow interrupt pending bit should only be cleared after stopping * all the counters to avoid any race condition. */ - csr_clear(CSR_SIP, SIP_LCOFIP); + csr_clear(CSR_SIP, BIT(riscv_pmu_irq_num)); =20 /* No overflow bit is set */ if (!overflow) @@ -653,8 +659,8 @@ static int pmu_sbi_starting_cpu(unsigned int cpu, struc= t hlist_node *node) =20 if (riscv_isa_extension_available(NULL, SSCOFPMF)) { cpu_hw_evt->irq =3D riscv_pmu_irq; - csr_clear(CSR_IP, BIT(RV_IRQ_PMU)); - csr_set(CSR_IE, BIT(RV_IRQ_PMU)); + csr_clear(CSR_IP, BIT(riscv_pmu_irq_num)); + csr_set(CSR_IE, BIT(riscv_pmu_irq_num)); enable_percpu_irq(riscv_pmu_irq, IRQ_TYPE_NONE); } =20 @@ -665,7 +671,7 @@ static int pmu_sbi_dying_cpu(unsigned int cpu, struct h= list_node *node) { if (riscv_isa_extension_available(NULL, SSCOFPMF)) { disable_percpu_irq(riscv_pmu_irq); - csr_clear(CSR_IE, BIT(RV_IRQ_PMU)); + csr_clear(CSR_IE, BIT(riscv_pmu_irq_num)); } =20 /* Disable all counters access for user mode now */ @@ -681,7 +687,11 @@ static int pmu_sbi_setup_irqs(struct riscv_pmu *pmu, s= truct platform_device *pde struct device_node *cpu, *child; struct irq_domain *domain =3D NULL; =20 - if (!riscv_isa_extension_available(NULL, SSCOFPMF)) + is_thead_c9xx =3D (sbi_get_mvendorid() =3D=3D THEAD_VENDOR_ID && + sbi_get_marchid() =3D=3D 0 && + sbi_get_mimpid() =3D=3D 0); + + if (!riscv_isa_extension_available(NULL, SSCOFPMF) && !is_thead_c9xx) return -EOPNOTSUPP; =20 for_each_of_cpu_node(cpu) { @@ -703,7 +713,8 @@ static int pmu_sbi_setup_irqs(struct riscv_pmu *pmu, st= ruct platform_device *pde return -ENODEV; } =20 - riscv_pmu_irq =3D irq_create_mapping(domain, RV_IRQ_PMU); + riscv_pmu_irq_num =3D !is_thead_c9xx ? RV_IRQ_PMU : THEAD_C9XX_RV_IRQ_PMU; + riscv_pmu_irq =3D irq_create_mapping(domain, riscv_pmu_irq_num); if (!riscv_pmu_irq) { pr_err("Failed to map PMU interrupt for node\n"); return -ENODEV; --=20 2.35.1