From nobody Sat Sep 21 17:02:23 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6B3B3C32773 for ; Wed, 17 Aug 2022 08:09:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233979AbiHQII5 (ORCPT ); Wed, 17 Aug 2022 04:08:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58164 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230201AbiHQIIp (ORCPT ); Wed, 17 Aug 2022 04:08:45 -0400 Received: from mail-wr1-x434.google.com (mail-wr1-x434.google.com [IPv6:2a00:1450:4864:20::434]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EB7AD4F6A4 for ; Wed, 17 Aug 2022 01:08:40 -0700 (PDT) Received: by mail-wr1-x434.google.com with SMTP id v3so15336250wrp.0 for ; Wed, 17 Aug 2022 01:08:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=LWK95oP5oKx5jLZsARdUZBbefoGwp+gOvhma7vrlCpI=; b=f0o8HbL81Cbajn0LlWxCI23dsDL/AOMSWSwK9bLg3BtFqxuu0TQnlZgMI7NIfD1j/x VONDXYw5T42+UTm7ljFx6jHpNiDCK6bfieHRhCGZ6WLnonO8sStKp2ASsUwYgTMEbiNl Afs4hhndKZkov9gggCnJYANns2YJByAxPRFXqkaQAfmPPCIyJ75jKKAqkRf6seXuFgjW Fp9w8Ia4eHjbHEAmhlmX9U/S2WHlRxof7+BEYGG4KB9UmHBZLCXv9vIRysONaywC7MlD UcNpYySrxUFzJQkidtCvuy3ozSDwb8ItzxUKCL4YwZuXP4v3fVyig5DM+bB2M2y694sQ XAcw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=LWK95oP5oKx5jLZsARdUZBbefoGwp+gOvhma7vrlCpI=; b=HoQj6YkExbCmJizSzGl2jkvWP+G211KL+vLkJ51I5hlHtPcKGO50kyTfTCQ6BstMEz etgC9mluqza92A3R/QTfLqO7tTuZtCdmfsV+wBkENQjNmtEZzwk0SuO3wGMsQZYvSLds HWh3GkRt4GUQqs9ioIxdjz+3iyRqF3rrR/G2jpHl17Y9fWZ1a5rA0KkLEQKC/Eoel2DV ixw7603cQmOCCm4YzuZX+gSJJY+thzsl6bqc7qtLbRqeN9ganmv1otVU6d14gbOQcGnW uNW6ql81GfazL+4veobBN4OgrtRsRkoOH+mQzmUFrbSSiqTnzSP1fV0jySSXYlh5XiBS ELnA== X-Gm-Message-State: ACgBeo2ilipbhkr7hNJEwVN3zi4VmuddcgIe0Apnr5tCxZfAc5/8J1iH 5xlrIyP9ClpSa1IwI1aE26XsNw== X-Google-Smtp-Source: AA6agR4nxG9zqxTof6Y+siXBdw1kqtlHb/D0yV1+6gVF3PSI/A35+NZWfSjXcxpiP1+cNMMLqFn9kQ== X-Received: by 2002:adf:de91:0:b0:225:2609:27c5 with SMTP id w17-20020adfde91000000b00225260927c5mr808023wrl.252.1660723719447; Wed, 17 Aug 2022 01:08:39 -0700 (PDT) Received: from Balsam-ThinkPad-T480.civfrance.com (58.188.158.77.rev.sfr.net. [77.158.188.58]) by smtp.gmail.com with ESMTPSA id u15-20020a05600c19cf00b003a54d610e5fsm1391992wmq.26.2022.08.17.01.08.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Aug 2022 01:08:39 -0700 (PDT) From: bchihi@baylibre.com To: rafael@kernel.org, rui.zhang@intel.com, daniel.lezcano@linaro.org, amitk@kernel.org Cc: linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, khilman@baylibre.com, mka@chromium.org, robh+dt@kernel.org, krzk+dt@kernel.org, matthias.bgg@gmail.com, p.zabel@pengutronix.de, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, james.lo@mediatek.com, fan.chen@mediatek.com, louis.yu@mediatek.com, rex-bc.chen@mediatek.com, abailon@baylibre.com Subject: [PATCH v9,3/7] arm64: dts: mt8192: Add thermal zones and thermal nodes Date: Wed, 17 Aug 2022 10:07:53 +0200 Message-Id: <20220817080757.352021-4-bchihi@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220817080757.352021-1-bchihi@baylibre.com> References: <20220817080757.352021-1-bchihi@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Balsam CHIHI Add thermal zones and thermal nodes for the mt8192. Signed-off-by: Balsam CHIHI --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 111 +++++++++++++++++++++++ 1 file changed, 111 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts= /mediatek/mt8192.dtsi index cbae5a5ee4a0..59ef4da06a70 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -12,6 +12,7 @@ #include #include #include +#include =20 / { compatible =3D "mediatek,mt8192"; @@ -599,6 +600,28 @@ spi0: spi@1100a000 { status =3D "disabled"; }; =20 + lvts_ap: thermal-sensor@1100b000 { + compatible =3D "mediatek,mt8192-lvts-ap"; + #thermal-sensor-cells =3D <1>; + reg =3D <0 0x1100b000 0 0x1000>; + interrupts =3D ; + clocks =3D <&infracfg CLK_INFRA_THERM>; + resets =3D <&infracfg MT8192_INFRA_RST0_THERM_CTRL_SWRST>; + nvmem-cells =3D <&lvts_e_data1>; + nvmem-cell-names =3D "lvts_calib_data1"; + }; + + lvts_mcu: thermal-sensor@11278000 { + compatible =3D "mediatek,mt8192-lvts-mcu"; + #thermal-sensor-cells =3D <1>; + reg =3D <0 0x11278000 0 0x1000>; + interrupts =3D ; + clocks =3D <&infracfg CLK_INFRA_THERM>; + resets =3D <&infracfg MT8192_INFRA_RST4_THERM_CTRL_MCU_SWRST>; + nvmem-cells =3D <&lvts_e_data1>; + nvmem-cell-names =3D "lvts_calib_data1"; + }; + spi1: spi@11010000 { compatible =3D "mediatek,mt8192-spi", "mediatek,mt6765-spi"; @@ -1457,4 +1480,92 @@ larb2: larb@1f002000 { power-domains =3D <&spm MT8192_POWER_DOMAIN_MDP>; }; }; + + thermal_zones: thermal-zones { + cpu0-thermal { + polling-delay =3D <0>; + polling-delay-passive =3D <0>; + thermal-sensors =3D <&lvts_mcu 0>; + }; + cpu1-thermal { + polling-delay =3D <0>; + polling-delay-passive =3D <0>; + thermal-sensors =3D <&lvts_mcu 1>; + }; + cpu2-thermal { + polling-delay =3D <0>; + polling-delay-passive =3D <0>; + thermal-sensors =3D <&lvts_mcu 2>; + }; + cpu3-thermal { + polling-delay =3D <0>; + polling-delay-passive =3D <0>; + thermal-sensors =3D <&lvts_mcu 3>; + }; + cpu4-thermal { + polling-delay =3D <0>; + polling-delay-passive =3D <0>; + thermal-sensors =3D <&lvts_mcu 4>; + }; + cpu5-thermal { + polling-delay =3D <0>; + polling-delay-passive =3D <0>; + thermal-sensors =3D <&lvts_mcu 5>; + }; + cpu6-thermal { + polling-delay =3D <0>; + polling-delay-passive =3D <0>; + thermal-sensors =3D <&lvts_mcu 6>; + }; + cpu7-thermal { + polling-delay =3D <0>; + polling-delay-passive =3D <0>; + thermal-sensors =3D <&lvts_mcu 7>; + }; + vpu1-thermal { + polling-delay =3D <0>; + polling-delay-passive =3D <0>; + thermal-sensors =3D <&lvts_ap 0>; + }; + vpu2-thermal { + polling-delay =3D <0>; + polling-delay-passive =3D <0>; + thermal-sensors =3D <&lvts_ap 1>; + }; + gpu1-thermal { + polling-delay =3D <0>; + polling-delay-passive =3D <0>; + thermal-sensors =3D <&lvts_ap 2>; + }; + gpu2-thermal { + polling-delay =3D <0>; + polling-delay-passive =3D <0>; + thermal-sensors =3D <&lvts_ap 3>; + }; + infra-thermal { + polling-delay =3D <0>; + polling-delay-passive =3D <0>; + thermal-sensors =3D <&lvts_ap 4>; + }; + cam-thermal { + polling-delay =3D <0>; + polling-delay-passive =3D <0>; + thermal-sensors =3D <&lvts_ap 5>; + }; + md1-thermal { + polling-delay =3D <0>; + polling-delay-passive =3D <0>; + thermal-sensors =3D <&lvts_ap 6>; + }; + md2-thermal { + polling-delay =3D <0>; + polling-delay-passive =3D <0>; + thermal-sensors =3D <&lvts_ap 7>; + }; + md3-thermal { + polling-delay =3D <0>; + polling-delay-passive =3D <0>; + thermal-sensors =3D <&lvts_ap 8>; + }; + }; }; --=20 2.34.1