From nobody Sat Apr 11 03:55:17 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7CC2DC25B08 for ; Wed, 17 Aug 2022 05:12:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229915AbiHQFMG (ORCPT ); Wed, 17 Aug 2022 01:12:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49422 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230131AbiHQFMB (ORCPT ); Wed, 17 Aug 2022 01:12:01 -0400 Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3184E6DFAB for ; Tue, 16 Aug 2022 22:12:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660713121; x=1692249121; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=i7pkxwVgmKuiNrs1UqKFz8MUN/cxAwQqnppeopXvGQs=; b=Jcgoegr2t1gt34QyOAwox/VX255Zz1pD4xfpdIiXJZZ6L0P3zqsUm0Id YAVupj1xecGPeN7Jzw61BDKbGx/JiKvWn77DAiJnZ4gSaFCDAGh8I6nPT aMCTxoswa0Uyy+9EdysOM3kFlPpNmusWC0F4fZWhoq50B5+QS3vhMrWqO P2SeSlzvgJzJs3NmUQDewlnGXCmG2jwhuBGRrBxB2a1Xg4kxY2CCdKd0K 2MsiRNiyHk/LxCJfWs58b0dkutpkINj1cWH/xQ0LczOE15faTfel56+nb fgdzYZbxcyQUz108fNnH6ab3Dl8VtGqOV4OdzSOnq8U+OO2ENNujFZj3W Q==; X-IronPort-AV: E=McAfee;i="6400,9594,10441"; a="289972495" X-IronPort-AV: E=Sophos;i="5.93,242,1654585200"; d="scan'208";a="289972495" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Aug 2022 22:12:00 -0700 X-IronPort-AV: E=Sophos;i="5.93,242,1654585200"; d="scan'208";a="557976684" Received: from araj-dh-work.jf.intel.com ([10.165.157.158]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Aug 2022 22:11:59 -0700 From: Ashok Raj To: Borislav Petkov , Thomas Gleixner Cc: Tony Luck , Dave Hansen , "LKML Mailing List" , X86-kernel , Andy Lutomirski , Tom Lendacky , "Jacon Jun Pan" , Ashok Raj Subject: [PATCH v3 1/5] x86/microcode/intel: Check against CPU signature before saving microcode Date: Wed, 17 Aug 2022 05:11:23 +0000 Message-Id: <20220817051127.3323755-2-ashok.raj@intel.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220817051127.3323755-1-ashok.raj@intel.com> References: <20220817051127.3323755-1-ashok.raj@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" When save_microcode_patch() is looking to replace an existing microcode in the cache, current code is *only* checks the CPU sig/pf in the main header. Microcode can carry additional sig/pf combinations in the extended signature table, which is completely missed today. For e.g. Current patch is a multi-stepping patch and new incoming patch is a specific patch just for this CPUs stepping. patch1: fms3 <--- header FMS ... ext_sig: fms1 fms2 patch2: new fms2 <--- header FMS Current code takes only fms3 and checks with patch2 fms2. saved_patch.header.fms3 !=3D new_patch.header.fms2, so save_microcode_patch saves it to the end of list instead of replacing patch1 with patch2. There is no functional user observable issue since find_patch() skips patch versions that are <=3D current_patch and will land on patch2 properly. Nevertheless this will just end up storing every patch that isn't required. Kernel just needs to store the latest patch. Otherwise its a memory leak that sits in kernel and never used. Cc: stable@vger.kernel.org Fixes: fe055896c040 ("x86/microcode: Merge the early microcode loader") Tested-by: William Xie Reported-by: William Xie Signed-off-by: Ashok Raj --- arch/x86/kernel/cpu/microcode/intel.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/mi= crocode/intel.c index 025c8f0cd948..c4b11e2fbe33 100644 --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -114,10 +114,18 @@ static void save_microcode_patch(struct ucode_cpu_inf= o *uci, void *data, unsigne =20 list_for_each_entry_safe(iter, tmp, µcode_cache, plist) { mc_saved_hdr =3D (struct microcode_header_intel *)iter->data; - sig =3D mc_saved_hdr->sig; - pf =3D mc_saved_hdr->pf; =20 - if (find_matching_signature(data, sig, pf)) { + sig =3D uci->cpu_sig.sig; + pf =3D uci->cpu_sig.pf; + + /* + * Compare the current CPUs signature with the ones in the + * cache to identify the right candidate to replace. At any + * given time, we should have no more than one valid patch + * file for a given CPU fms+pf in the cache list. + */ + + if (find_matching_signature(iter->data, sig, pf)) { prev_found =3D true; =20 if (mc_hdr->rev <=3D mc_saved_hdr->rev) --=20 2.32.0