From nobody Sat Apr 11 02:17:42 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 15A26C38142 for ; Tue, 16 Aug 2022 21:15:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237475AbiHPVPE (ORCPT ); Tue, 16 Aug 2022 17:15:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54244 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237471AbiHPVPA (ORCPT ); Tue, 16 Aug 2022 17:15:00 -0400 Received: from mail-wm1-x333.google.com (mail-wm1-x333.google.com [IPv6:2a00:1450:4864:20::333]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 585EC7D7BA for ; Tue, 16 Aug 2022 14:14:59 -0700 (PDT) Received: by mail-wm1-x333.google.com with SMTP id r83-20020a1c4456000000b003a5cb389944so5485wma.4 for ; Tue, 16 Aug 2022 14:14:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=LvSKUVtr5Gp4BgmH/TzQ81b8EX2DhTfAUAFDUiW03kI=; b=bRWLm4TI/Y2cCF3vuQE23DoT1UwUjndleUK28KJkWmBRPnO0LnyaE6mhqZxkLqJqaV E8IpyM62YSpJlid86sYrQUMi72m7iM4g821qxkCnx3aNmk0b6AX8SvFlyXI4TI6opng9 fEAIdhShwdMHA0818rzk7NpGSXqW2ru4e+I0Yq4F+w1DsWjH1XacMNVuGYdGuYKV3UlK 1LK8sYwd8aDHAD1cGExKH23bxORx4AAm9e21Ad9QC3niM413zTIvbz7N1oEP4T+fpPhP rG5bEwkTTbiK2XRIolrzxtBc/AGW4kGpPqfjo1DR8+wqWbgOdnNDclPU3Y6/hJ73atI9 ytpw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=LvSKUVtr5Gp4BgmH/TzQ81b8EX2DhTfAUAFDUiW03kI=; b=DMXSEbGktf6jxV8BU3injLwSoR3EButsXX/MGGd90IP/VCymRfk0B+yDZ2zfLv2JxU lsT17X+xnrzczj7/Fb0wZVSVIVF1Fcpe12CBOX02sl6d+H13Qoyw3y+bZww5sMwg/S1q 76+K4Nk0Ty1gPFP77yeGhJmX2nKgxqMUKAlXLI4gF47IEOGMquVYTpGXX1giAi3cVb4I k7YvkmcijjgZkBg7aJi0Y5mKGmNK8RZ89c49pxcQCZDZ9+fMQRF3tf6qJ+Bv2A9wICI8 BT+hlPMjCJxnLZdtQzB5fODJZN1Dc83EQFmqlj4JW7leoeR4dBhicE5iQxhlcyPlSVZC v+2g== X-Gm-Message-State: ACgBeo0om8LaSXb6K7mKOuED4YkqM6NHtGZ6Dj9sYf2fH2PLPrSeghQn E5Jwml+lNplY2QlmvtOKnsVAXA== X-Google-Smtp-Source: AA6agR7WU2umVyZku64Rq1qUALdsgHptgVygp32cUgOiAnp2l1mktYWFst85Ti0DAjmfA66iEX6z0w== X-Received: by 2002:a05:600c:206:b0:3a5:41f1:aa23 with SMTP id 6-20020a05600c020600b003a541f1aa23mr215637wmi.31.1660684497606; Tue, 16 Aug 2022 14:14:57 -0700 (PDT) Received: from rainbowdash.office.codethink.co.uk ([167.98.27.226]) by smtp.gmail.com with ESMTPSA id r4-20020a1c4404000000b003a3170a7af9sm23913wma.4.2022.08.16.14.14.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Aug 2022 14:14:57 -0700 (PDT) From: Ben Dooks To: linux-pwm@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Lee Jones , u.kleine-koenig@pengutronix.de, Thierry Reding , Krzysztof Kozlowski , Greentime Hu , jarkko.nikula@linux.intel.com, William Salmon , Jude Onyenegecha , Ben Dooks Subject: [RFC v4 01/10] dt-bindings: pwm: Document Synopsys DesignWare snps,pwm-dw-apb-timers-pwm2 Date: Tue, 16 Aug 2022 22:14:45 +0100 Message-Id: <20220816211454.237751-2-ben.dooks@sifive.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220816211454.237751-1-ben.dooks@sifive.com> References: <20220816211454.237751-1-ben.dooks@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add documentation for the bindings for Synopsys' DesignWare PWM block as we will be adding DT/platform support to the Linux driver soon. Signed-off-by: Ben Dooks --- v4: - fixed typos, added reg v3: - add description and example - merge the snps,pwm-number into this patch - rename snps,pwm to snps,dw-apb-timers-pwm2 v2: - fix #pwm-cells to be 3 - fix indentation and ordering issues --- .../bindings/pwm/snps,dw-apb-timers-pwm2.yaml | 69 +++++++++++++++++++ 1 file changed, 69 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/snps,dw-apb-timer= s-pwm2.yaml diff --git a/Documentation/devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.= yaml b/Documentation/devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.yaml new file mode 100644 index 000000000000..e7feae6d4404 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.yaml @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2022 SiFive, Inc. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/snps,dw-apb-timers-pwm2.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Synopsys DW-APB timers PWM controller + +maintainers: + - Ben Dooks + +description: + This describes the DesignWare APB timers module when used in the PWM + mode. The IP core can be generated with various options which can + control the functionality, the number of PWMs available and other + internal controls the designer requires. + + The IP block has a version register so this can be used for detection + instead of having to encode the IP version number in the device tree + comaptible. + +allOf: + - $ref: pwm.yaml# + +properties: + compatible: + const: snps,dw-apb-timers-pwm2 + + "#pwm-cells": + const: 3 + + clocks: + items: + - description: Interface bus clock + - description: PWM reference clock + + clock-names: + items: + - const: bus + - const: timer + + snps,pwm-number: + $ref: /schemas/types.yaml#/definitions/uint32 + description: The number of PWM channels configured for this instance + enum: [1, 2, 3, 4, 5, 6, 7, 8] + + reg: + maxItems: 1 + +required: + - "#pwm-cells" + - compatible + - reg + - clocks + - clock-names + +additionalProperties: false + + +examples: + - | + pwm: pwm@180000 { + #pwm-cells =3D <3>; + compatible =3D "snps,dw-apb-timers-pwm2"; + reg =3D <0x180000 0x200>; + clocks =3D <&bus &timer>; + clock-names =3D "bus", "timer"; + }; --=20 2.35.1 From nobody Sat Apr 11 02:17:42 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B5699C25B0E for ; Tue, 16 Aug 2022 21:15:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237513AbiHPVPK (ORCPT ); Tue, 16 Aug 2022 17:15:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54252 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237468AbiHPVPB (ORCPT ); Tue, 16 Aug 2022 17:15:01 -0400 Received: from mail-wr1-x436.google.com (mail-wr1-x436.google.com [IPv6:2a00:1450:4864:20::436]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 348D466A5C for ; Tue, 16 Aug 2022 14:15:00 -0700 (PDT) Received: by mail-wr1-x436.google.com with SMTP id e27so9337972wra.11 for ; Tue, 16 Aug 2022 14:14:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=pOKidRu+yxajr1o110Z9rt8XpJh4zLytmd2a75/kdaY=; b=eycbJA9QimgNmj6FqsedtUpws9mFwuQMTmqmi7bWPB+Slec+QuQeQnPnlbNjGETRb1 iFK24JTcpfKfIOLgLStWto0lUa6i9zdJX2y5OpLxjITVHkpf3YAV5aiu5QUJe423RM6E VqG/wmJ5ao2urhXB2WF/MYw6B4qZTCeco1FEn7VPcV9cusG5BSPeEWECdL6OW1l23s3o awJH3tZDVx+NYYD9dgpREKunb8LFursJ2bvKsH6EQWMWydKNys4vfr61VepPWBIwQvKK So2lKq0dgmIIDZ21IG5o3aZJQP6uzPn5+dTTnTnMXeJ84+bcw/7Z2fntv6PR42PjAkf0 zb2w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=pOKidRu+yxajr1o110Z9rt8XpJh4zLytmd2a75/kdaY=; b=SIwKxSrZDN+1c8u8P58hBMOGzEzgSof1V1B2BNFFWJRcO/pleU6vhLUgwzOz9FeMEo LlKcfkhG7em5YVuB/TJ2Pxv+X6qx7x/u8mWo93ehHKgEnXkrao3eA5yR35NLX/wsbLik mwrc3KVS/n2YqLHtsZGR9MJ9QMI+MtOObHWxuhqdzD4vs38s/KkUisJsQMIyqFZGv6ma BaURu010fnevuQn+5ixrNXUUIX9eg+vLb0skleS8q8Y79hcZ+WaBBDSzbKU3kXQY6aMu hem1qPx1/23Tp9L6B7NqbcWoUtnNBPe6oGG82NlNUk3ytxJFCNDzH2Q1WbJSxZ/mzN/5 hrnA== X-Gm-Message-State: ACgBeo2/Q1OGLeu3ujqbP2VeN07GhocBKPAasFiWdr+2ncNOdJ3i5aCQ QSiIiH97gclnaHUkzOAO2ix5ZQ== X-Google-Smtp-Source: AA6agR4jnXSmm1WE3xmPat9hSfuxaHd1ndKNlueu8VFQO7Wz7awB0kB/CNbeG6zrxQ95PDBr1wAvew== X-Received: by 2002:a5d:4201:0:b0:21d:7b63:1b43 with SMTP id n1-20020a5d4201000000b0021d7b631b43mr12129030wrq.225.1660684498400; Tue, 16 Aug 2022 14:14:58 -0700 (PDT) Received: from rainbowdash.office.codethink.co.uk ([167.98.27.226]) by smtp.gmail.com with ESMTPSA id r4-20020a1c4404000000b003a3170a7af9sm23913wma.4.2022.08.16.14.14.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Aug 2022 14:14:58 -0700 (PDT) From: Ben Dooks To: linux-pwm@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Lee Jones , u.kleine-koenig@pengutronix.de, Thierry Reding , Krzysztof Kozlowski , Greentime Hu , jarkko.nikula@linux.intel.com, William Salmon , Jude Onyenegecha , Ben Dooks Subject: [RFC v4 02/10] pwm: dwc: allow driver to be built with COMPILE_TEST Date: Tue, 16 Aug 2022 22:14:46 +0100 Message-Id: <20220816211454.237751-3-ben.dooks@sifive.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220816211454.237751-1-ben.dooks@sifive.com> References: <20220816211454.237751-1-ben.dooks@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Allow dwc driver to be built with COMPILE_TEST should allow better coverage when build testing. Signed-off-by: Ben Dooks Acked-by: Uwe Kleine-K=C3=B6nig --- v4: - moved to earlier in the series v3: - add HAS_IOMEM depdency for compile testing --- drivers/pwm/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 60d13a949bc5..3f3c53af4a56 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -176,7 +176,8 @@ config PWM_CROS_EC =20 config PWM_DWC tristate "DesignWare PWM Controller" - depends on PCI + depends on PCI || COMPILE_TEST + depends on HAS_IOMEM help PWM driver for Synopsys DWC PWM Controller attached to a PCI bus. =20 --=20 2.35.1 From nobody Sat Apr 11 02:17:42 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 92954C32772 for ; Tue, 16 Aug 2022 21:15:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237523AbiHPVPO (ORCPT ); Tue, 16 Aug 2022 17:15:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54244 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237484AbiHPVPC (ORCPT ); Tue, 16 Aug 2022 17:15:02 -0400 Received: from mail-wm1-x329.google.com (mail-wm1-x329.google.com [IPv6:2a00:1450:4864:20::329]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C327165813 for ; Tue, 16 Aug 2022 14:15:00 -0700 (PDT) Received: by mail-wm1-x329.google.com with SMTP id h204-20020a1c21d5000000b003a5b467c3abso3300wmh.5 for ; Tue, 16 Aug 2022 14:15:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=BEOpRioXienSDDf6vjruAkPlsDKDhUNbn1dmZioZ4X4=; b=eYefCuC/rgQ6p0YNaYBu3lEQX3Uj5IL6sNCWvehy/NqfbV2p8Tg917eIc4dD2xBV0i K6XA3rjwJrLptS3Vz6FWghqV/m/+uSJZOHd3f1V/5Iuu7cyDt+EnKxHLceb//0HzG+0U VMAw6kcNGsOyYE+zE8yRUZcMNM1FWfVR2vaEptiW2uiAGrPMtoyMmaT+/xiiBPXVNkmx JBx3FNmZxxDxmOSq5XtmfuSRL8YncLD/nkyfu/ji3WjuS3IQ/ekjJFSIRpBSF52V2WyO I/IocNCe/7jr1MYPJB/9stcdR3DucirXsphktPY+U+g3ZM3M2LUbFC5e29KVDZIggqNs bB1g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=BEOpRioXienSDDf6vjruAkPlsDKDhUNbn1dmZioZ4X4=; b=VcqHEX7ze8aDn8OvbPyi91UzJSKREqOuFIWhPm0fXIYJNLUGsMFduQx3qbLMENWuoV xrJQmH5KhSyGwCsSwHSRc84opwaVGcEoH6X93zLMzbrwsuTVxQuOzG9tXp6znyzGDdaQ NH4e39Qm5cuLvG2x3ImiRYG6t2vm8b6oAEaelqE6VV2mUNTKq3gbWQg+jWeqEthhPAK4 vi9QatWupOOfvNA5oEe7RFtdt/5FPziQf5YbDStYSGfocgqtLZrLjDKpTOAeZixadcNY x9Bp5zLSrSU4+hEAjiaFyjOIW6cdBg+9qGtJFujSQgtcjVv/DN0vyZ8cJ4TszpUkI75m FC4g== X-Gm-Message-State: ACgBeo04Y1v3OttD9WHXApiNxGSd6h03QtFMk16fjV+R8fZCXEqP52im rYKCFQzmRtWnLHqqTHoi7Te3Bg== X-Google-Smtp-Source: AA6agR4x5105693B/mvfnk5ocFtht52wNSb/pOgM+837u+GyY9Nw0+ugNz4CTpZcN8mxWyQV6UPlmg== X-Received: by 2002:a1c:3b04:0:b0:3a5:487c:6240 with SMTP id i4-20020a1c3b04000000b003a5487c6240mr212714wma.152.1660684499117; Tue, 16 Aug 2022 14:14:59 -0700 (PDT) Received: from rainbowdash.office.codethink.co.uk ([167.98.27.226]) by smtp.gmail.com with ESMTPSA id r4-20020a1c4404000000b003a3170a7af9sm23913wma.4.2022.08.16.14.14.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Aug 2022 14:14:58 -0700 (PDT) From: Ben Dooks To: linux-pwm@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Lee Jones , u.kleine-koenig@pengutronix.de, Thierry Reding , Krzysztof Kozlowski , Greentime Hu , jarkko.nikula@linux.intel.com, William Salmon , Jude Onyenegecha , Ben Dooks Subject: [RFC v4 03/10] pwm: dwc: change &pci->dev to dev in probe Date: Tue, 16 Aug 2022 22:14:47 +0100 Message-Id: <20220816211454.237751-4-ben.dooks@sifive.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220816211454.237751-1-ben.dooks@sifive.com> References: <20220816211454.237751-1-ben.dooks@sifive.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The dwc_pwm_probe() assignes dev to be &pci->dev but then uses &pci->dev throughout the function. Change these all to the be 'dev' variable to make lines shorter. Signed-off-by: Ben Dooks Acked-by: Uwe Kleine-K=C3=B6nig --- drivers/pwm/pwm-dwc.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/drivers/pwm/pwm-dwc.c b/drivers/pwm/pwm-dwc.c index 7568300bb11e..c706ef9a7ba1 100644 --- a/drivers/pwm/pwm-dwc.c +++ b/drivers/pwm/pwm-dwc.c @@ -202,14 +202,13 @@ static int dwc_pwm_probe(struct pci_dev *pci, const s= truct pci_device_id *id) struct dwc_pwm *dwc; int ret; =20 - dwc =3D devm_kzalloc(&pci->dev, sizeof(*dwc), GFP_KERNEL); + dwc =3D devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL); if (!dwc) return -ENOMEM; =20 ret =3D pcim_enable_device(pci); if (ret) { - dev_err(&pci->dev, - "Failed to enable device (%pe)\n", ERR_PTR(ret)); + dev_err(dev, "Failed to enable device (%pe)\n", ERR_PTR(ret)); return ret; } =20 @@ -217,14 +216,13 @@ static int dwc_pwm_probe(struct pci_dev *pci, const s= truct pci_device_id *id) =20 ret =3D pcim_iomap_regions(pci, BIT(0), pci_name(pci)); if (ret) { - dev_err(&pci->dev, - "Failed to iomap PCI BAR (%pe)\n", ERR_PTR(ret)); + dev_err(dev, "Failed to iomap PCI BAR (%pe)\n", ERR_PTR(ret)); return ret; } =20 dwc->base =3D pcim_iomap_table(pci)[0]; if (!dwc->base) { - dev_err(&pci->dev, "Base address missing\n"); + dev_err(dev, "Base address missing\n"); return -ENOMEM; } =20 --=20 2.35.1 From nobody Sat Apr 11 02:17:42 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 50327C25B0E for ; Tue, 16 Aug 2022 21:15:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237529AbiHPVPS (ORCPT ); Tue, 16 Aug 2022 17:15:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54346 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237495AbiHPVPD (ORCPT ); Tue, 16 Aug 2022 17:15:03 -0400 Received: from mail-wr1-x434.google.com (mail-wr1-x434.google.com [IPv6:2a00:1450:4864:20::434]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 76CF77D7BA for ; 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charset="utf-8" In preparation for adding other bus support, move the allocation of the pwm struct out of the main driver code. Signed-off-by: Ben Dooks --- drivers/pwm/pwm-dwc.c | 24 +++++++++++++++++------- 1 file changed, 17 insertions(+), 7 deletions(-) diff --git a/drivers/pwm/pwm-dwc.c b/drivers/pwm/pwm-dwc.c index c706ef9a7ba1..61f11e0a9319 100644 --- a/drivers/pwm/pwm-dwc.c +++ b/drivers/pwm/pwm-dwc.c @@ -196,13 +196,29 @@ static const struct pwm_ops dwc_pwm_ops =3D { .owner =3D THIS_MODULE, }; =20 +static struct dwc_pwm *dwc_pwm_alloc(struct device *dev) +{ + struct dwc_pwm *dwc; + + dwc =3D devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL); + if (!dwc) + return NULL; + + dwc->chip.dev =3D dev; + dwc->chip.ops =3D &dwc_pwm_ops; + dwc->chip.npwm =3D DWC_TIMERS_TOTAL; + + dev_set_drvdata(dev, dwc); + return dwc; +} + static int dwc_pwm_probe(struct pci_dev *pci, const struct pci_device_id *= id) { struct device *dev =3D &pci->dev; struct dwc_pwm *dwc; int ret; =20 - dwc =3D devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL); + dwc =3D dwc_pwm_alloc(dev); if (!dwc) return -ENOMEM; =20 @@ -226,12 +242,6 @@ static int dwc_pwm_probe(struct pci_dev *pci, const st= ruct pci_device_id *id) return -ENOMEM; } =20 - pci_set_drvdata(pci, dwc); - - dwc->chip.dev =3D dev; - dwc->chip.ops =3D &dwc_pwm_ops; - dwc->chip.npwm =3D DWC_TIMERS_TOTAL; - ret =3D pwmchip_add(&dwc->chip); if (ret) return ret; --=20 2.35.1 From nobody Sat Apr 11 02:17:42 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 35CE1C25B0E for ; Tue, 16 Aug 2022 21:15:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237578AbiHPVPg (ORCPT ); Tue, 16 Aug 2022 17:15:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54550 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237510AbiHPVPJ (ORCPT ); Tue, 16 Aug 2022 17:15:09 -0400 Received: from mail-wr1-x436.google.com (mail-wr1-x436.google.com [IPv6:2a00:1450:4864:20::436]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 536657E32E for ; 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charset="utf-8" Use devm_pwmchip_add() to add the pwm chip to avoid having to manually remove it (useful for the next patch which adds the platform-device support). Signed-off-by: Ben Dooks Reviewed-by: Uwe Kleine-K=C3=B6nig --- drivers/pwm/pwm-dwc.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/drivers/pwm/pwm-dwc.c b/drivers/pwm/pwm-dwc.c index 61f11e0a9319..56cde9da2c0e 100644 --- a/drivers/pwm/pwm-dwc.c +++ b/drivers/pwm/pwm-dwc.c @@ -242,7 +242,7 @@ static int dwc_pwm_probe(struct pci_dev *pci, const str= uct pci_device_id *id) return -ENOMEM; } =20 - ret =3D pwmchip_add(&dwc->chip); + ret =3D devm_pwmchip_add(dev, &dwc->chip); if (ret) return ret; =20 @@ -254,12 +254,8 @@ static int dwc_pwm_probe(struct pci_dev *pci, const st= ruct pci_device_id *id) =20 static void dwc_pwm_remove(struct pci_dev *pci) { - struct dwc_pwm *dwc =3D pci_get_drvdata(pci); - pm_runtime_forbid(&pci->dev); pm_runtime_get_noresume(&pci->dev); - - pwmchip_remove(&dwc->chip); } =20 #ifdef CONFIG_PM_SLEEP --=20 2.35.1 From nobody Sat Apr 11 02:17:42 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E9844C25B0E for ; Tue, 16 Aug 2022 21:15:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237590AbiHPVPi (ORCPT ); Tue, 16 Aug 2022 17:15:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54816 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237536AbiHPVPU (ORCPT ); Tue, 16 Aug 2022 17:15:20 -0400 Received: from mail-wr1-x42d.google.com (mail-wr1-x42d.google.com [IPv6:2a00:1450:4864:20::42d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 691197A516 for ; Tue, 16 Aug 2022 14:15:03 -0700 (PDT) Received: by mail-wr1-x42d.google.com with SMTP id v3so14091053wrp.0 for ; Tue, 16 Aug 2022 14:15:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=KhMhCXNUPulyEqbvrgq3B8jPysRuP6fKiM4Dgs7yiW0=; b=HZsN1CX0Bc02mQo0Nfq87Qc0PfrEXZBxl7w/Da2GFOWKgOjeQeG6tKD4h+Hs6eIhvV JVOdD0L2ygzPThCwdaNS5NT16fdbrHQQtytkBBhwc8pQp7Lzd+aoeF5+5oaw1P7/Q1Tl JGiLqu8Xs7TZyBc4+8PcVwGgXe4Vs+V6ZqpqCtWr6nNaXF8aPEeL6qPJwOZdgQ9H6BLb coj9jCxkSgV4LtSETI8gYMi1iOhBdZo0hhRffy/61izSoZ5eCaE2TP9JNSMbjwtuqzI1 I2IGJWAgFOLMP0dY/N1P4ab74L4aP45w7D1qMFdp8hSjZ6II3aQLXFO3kXoHX/Ak8pYY fHYw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=KhMhCXNUPulyEqbvrgq3B8jPysRuP6fKiM4Dgs7yiW0=; b=hmQ6zOiAVUPxMemN2Zvb44LCIIsTEkJmeir+iQdbNpIXjnB11LhWAXc6qOhASxUuqz McffqipWCuI+gpTkJx0GuPx86hFbHz69Bw0ewrtWs/Juhp3ksyZBrX1ngtHK6Ltb7pFm faw+7EkLO5OmyLxis8gW6vQxomsUPMM+K5Yap38nkfTA8xXWOC7tbCLIbAhMXE0q1G0v 6n3i6Ris/IYI68fEBh92EkXr9kv+NLtpF4sKumEZ+nFNZyL4Nel4ixmbB1Dmslm4+bRF fLni+3khX92fYwxZsLvit0xdVPZ+mHIePmip/C2ly8XM9qLNsmNh4cORnBGgsz5PZ1C4 +gjg== X-Gm-Message-State: ACgBeo3KzW7XhkuAcoeYEFy4HpXZPGNTxneHYH+//vRxebhEuNY9XFhp YZPyviMewMa6zA00pY/weEfDuw== X-Google-Smtp-Source: AA6agR7lVU/aqe0NWxi8r1nhfuQLGSXQNuJn88FM950tnhSF+WitfhmKyJrWGi/c5DMyRyqh8jX2Hw== X-Received: by 2002:a5d:6da1:0:b0:220:b328:e4d4 with SMTP id u1-20020a5d6da1000000b00220b328e4d4mr12293232wrs.14.1660684501319; Tue, 16 Aug 2022 14:15:01 -0700 (PDT) Received: from rainbowdash.office.codethink.co.uk ([167.98.27.226]) by smtp.gmail.com with ESMTPSA id r4-20020a1c4404000000b003a3170a7af9sm23913wma.4.2022.08.16.14.15.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Aug 2022 14:15:01 -0700 (PDT) From: Ben Dooks To: linux-pwm@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Lee Jones , u.kleine-koenig@pengutronix.de, Thierry Reding , Krzysztof Kozlowski , Greentime Hu , jarkko.nikula@linux.intel.com, William Salmon , Jude Onyenegecha , Ben Dooks Subject: [RFC v4 06/10] pwm: dwc: split pci out of core driver Date: Tue, 16 Aug 2022 22:14:50 +0100 Message-Id: <20220816211454.237751-7-ben.dooks@sifive.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220816211454.237751-1-ben.dooks@sifive.com> References: <20220816211454.237751-1-ben.dooks@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Moving towards adding non-pci support for the driver, move the pci parts out of the core into their own module. This is partly due to the module_driver() code only being allowed once in a module and also to avoid a number of #ifdef if we build a single file in a system without pci support. Signed-off-by: Ben Dooks --- drivers/pwm/Kconfig | 14 +++- drivers/pwm/Makefile | 1 + drivers/pwm/pwm-dwc-pci.c | 133 ++++++++++++++++++++++++++++++++ drivers/pwm/pwm-dwc.c | 158 +------------------------------------- drivers/pwm/pwm-dwc.h | 58 ++++++++++++++ 5 files changed, 207 insertions(+), 157 deletions(-) create mode 100644 drivers/pwm/pwm-dwc-pci.c create mode 100644 drivers/pwm/pwm-dwc.h diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 3f3c53af4a56..a9f1c554db2b 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -175,15 +175,23 @@ config PWM_CROS_EC Controller. =20 config PWM_DWC - tristate "DesignWare PWM Controller" - depends on PCI || COMPILE_TEST + tristate "DesignWare PWM Controller core" depends on HAS_IOMEM help - PWM driver for Synopsys DWC PWM Controller attached to a PCI bus. + PWM driver for Synopsys DWC PWM Controller. =20 To compile this driver as a module, choose M here: the module will be called pwm-dwc. =20 +config PWM_DWC_PCI + tristate "DesignWare PWM Controller core" + depends on PWM_DWC && HAS_IOMEM && PCI + help + PWM driver for Synopsys DWC PWM Controller attached to a PCI bus. + + To compile this driver as a module, choose M here: the module + will be called pwm-dwc-pci. + config PWM_EP93XX tristate "Cirrus Logic EP93xx PWM support" depends on ARCH_EP93XX || COMPILE_TEST diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index 7bf1a29f02b8..a70d36623129 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -15,6 +15,7 @@ obj-$(CONFIG_PWM_CLPS711X) +=3D pwm-clps711x.o obj-$(CONFIG_PWM_CRC) +=3D pwm-crc.o obj-$(CONFIG_PWM_CROS_EC) +=3D pwm-cros-ec.o obj-$(CONFIG_PWM_DWC) +=3D pwm-dwc.o +obj-$(CONFIG_PWM_DWC_PCI) +=3D pwm-dwc-pci.o obj-$(CONFIG_PWM_EP93XX) +=3D pwm-ep93xx.o obj-$(CONFIG_PWM_FSL_FTM) +=3D pwm-fsl-ftm.o obj-$(CONFIG_PWM_HIBVT) +=3D pwm-hibvt.o diff --git a/drivers/pwm/pwm-dwc-pci.c b/drivers/pwm/pwm-dwc-pci.c new file mode 100644 index 000000000000..2213d0e7f3c8 --- /dev/null +++ b/drivers/pwm/pwm-dwc-pci.c @@ -0,0 +1,133 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * DesignWare PWM Controller driver (PCI part) + * + * Copyright (C) 2018-2020 Intel Corporation + * + * Author: Felipe Balbi (Intel) + * Author: Jarkko Nikula + * Author: Raymond Tan + * + * Limitations: + * - The hardware cannot generate a 0 % or 100 % duty cycle. Both high and= low + * periods are one or more input clock periods long. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "pwm-dwc.h" + +static int dwc_pwm_probe(struct pci_dev *pci, const struct pci_device_id *= id) +{ + struct device *dev =3D &pci->dev; + struct dwc_pwm *dwc; + int ret; + + dwc =3D dwc_pwm_alloc(dev); + if (!dwc) + return -ENOMEM; + + ret =3D pcim_enable_device(pci); + if (ret) { + dev_err(dev, "Failed to enable device (%pe)\n", ERR_PTR(ret)); + return ret; + } + + pci_set_master(pci); + + ret =3D pcim_iomap_regions(pci, BIT(0), pci_name(pci)); + if (ret) { + dev_err(dev, "Failed to iomap PCI BAR (%pe)\n", ERR_PTR(ret)); + return ret; + } + + dwc->base =3D pcim_iomap_table(pci)[0]; + if (!dwc->base) { + dev_err(dev, "Base address missing\n"); + return -ENOMEM; + } + + ret =3D devm_pwmchip_add(dev, &dwc->chip); + if (ret) + return ret; + + pm_runtime_put(dev); + pm_runtime_allow(dev); + + return 0; +} + +static void dwc_pwm_remove(struct pci_dev *pci) +{ + pm_runtime_forbid(&pci->dev); + pm_runtime_get_noresume(&pci->dev); +} + +#ifdef CONFIG_PM_SLEEP +static int dwc_pwm_suspend(struct device *dev) +{ + struct pci_dev *pdev =3D container_of(dev, struct pci_dev, dev); + struct dwc_pwm *dwc =3D pci_get_drvdata(pdev); + int i; + + for (i =3D 0; i < DWC_TIMERS_TOTAL; i++) { + if (dwc->chip.pwms[i].state.enabled) { + dev_err(dev, "PWM %u in use by consumer (%s)\n", + i, dwc->chip.pwms[i].label); + return -EBUSY; + } + dwc->ctx[i].cnt =3D dwc_pwm_readl(dwc, DWC_TIM_LD_CNT(i)); + dwc->ctx[i].cnt2 =3D dwc_pwm_readl(dwc, DWC_TIM_LD_CNT2(i)); + dwc->ctx[i].ctrl =3D dwc_pwm_readl(dwc, DWC_TIM_CTRL(i)); + } + + return 0; +} + +static int dwc_pwm_resume(struct device *dev) +{ + struct pci_dev *pdev =3D container_of(dev, struct pci_dev, dev); + struct dwc_pwm *dwc =3D pci_get_drvdata(pdev); + int i; + + for (i =3D 0; i < DWC_TIMERS_TOTAL; i++) { + dwc_pwm_writel(dwc, dwc->ctx[i].cnt, DWC_TIM_LD_CNT(i)); + dwc_pwm_writel(dwc, dwc->ctx[i].cnt2, DWC_TIM_LD_CNT2(i)); + dwc_pwm_writel(dwc, dwc->ctx[i].ctrl, DWC_TIM_CTRL(i)); + } + + return 0; +} +#endif + +static SIMPLE_DEV_PM_OPS(dwc_pwm_pm_ops, dwc_pwm_suspend, dwc_pwm_resume); + +static const struct pci_device_id dwc_pwm_id_table[] =3D { + { PCI_VDEVICE(INTEL, 0x4bb7) }, /* Elkhart Lake */ + { } /* Terminating Entry */ +}; +MODULE_DEVICE_TABLE(pci, dwc_pwm_id_table); + +static struct pci_driver dwc_pwm_driver =3D { + .name =3D "pwm-dwc", + .probe =3D dwc_pwm_probe, + .remove =3D dwc_pwm_remove, + .id_table =3D dwc_pwm_id_table, + .driver =3D { + .pm =3D &dwc_pwm_pm_ops, + }, +}; + +module_pci_driver(dwc_pwm_driver); + +MODULE_AUTHOR("Felipe Balbi (Intel)"); +MODULE_AUTHOR("Jarkko Nikula "); +MODULE_AUTHOR("Raymond Tan "); +MODULE_DESCRIPTION("DesignWare PWM Controller"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pwm/pwm-dwc.c b/drivers/pwm/pwm-dwc.c index 56cde9da2c0e..90a8ae1252a1 100644 --- a/drivers/pwm/pwm-dwc.c +++ b/drivers/pwm/pwm-dwc.c @@ -1,16 +1,12 @@ // SPDX-License-Identifier: GPL-2.0 /* - * DesignWare PWM Controller driver + * DesignWare PWM Controller driver core * * Copyright (C) 2018-2020 Intel Corporation * * Author: Felipe Balbi (Intel) * Author: Jarkko Nikula * Author: Raymond Tan - * - * Limitations: - * - The hardware cannot generate a 0 % or 100 % duty cycle. Both high and= low - * periods are one or more input clock periods long. */ =20 #include @@ -21,51 +17,7 @@ #include #include =20 -#define DWC_TIM_LD_CNT(n) ((n) * 0x14) -#define DWC_TIM_LD_CNT2(n) (((n) * 4) + 0xb0) -#define DWC_TIM_CUR_VAL(n) (((n) * 0x14) + 0x04) -#define DWC_TIM_CTRL(n) (((n) * 0x14) + 0x08) -#define DWC_TIM_EOI(n) (((n) * 0x14) + 0x0c) -#define DWC_TIM_INT_STS(n) (((n) * 0x14) + 0x10) - -#define DWC_TIMERS_INT_STS 0xa0 -#define DWC_TIMERS_EOI 0xa4 -#define DWC_TIMERS_RAW_INT_STS 0xa8 -#define DWC_TIMERS_COMP_VERSION 0xac - -#define DWC_TIMERS_TOTAL 8 -#define DWC_CLK_PERIOD_NS 10 - -/* Timer Control Register */ -#define DWC_TIM_CTRL_EN BIT(0) -#define DWC_TIM_CTRL_MODE BIT(1) -#define DWC_TIM_CTRL_MODE_FREE (0 << 1) -#define DWC_TIM_CTRL_MODE_USER (1 << 1) -#define DWC_TIM_CTRL_INT_MASK BIT(2) -#define DWC_TIM_CTRL_PWM BIT(3) - -struct dwc_pwm_ctx { - u32 cnt; - u32 cnt2; - u32 ctrl; -}; - -struct dwc_pwm { - struct pwm_chip chip; - void __iomem *base; - struct dwc_pwm_ctx ctx[DWC_TIMERS_TOTAL]; -}; -#define to_dwc_pwm(p) (container_of((p), struct dwc_pwm, chip)) - -static inline u32 dwc_pwm_readl(struct dwc_pwm *dwc, u32 offset) -{ - return readl(dwc->base + offset); -} - -static inline void dwc_pwm_writel(struct dwc_pwm *dwc, u32 value, u32 offs= et) -{ - writel(value, dwc->base + offset); -} +#include "pwm-dwc.h" =20 static void __dwc_pwm_set_enable(struct dwc_pwm *dwc, int pwm, int enabled) { @@ -196,7 +148,7 @@ static const struct pwm_ops dwc_pwm_ops =3D { .owner =3D THIS_MODULE, }; =20 -static struct dwc_pwm *dwc_pwm_alloc(struct device *dev) +struct dwc_pwm *dwc_pwm_alloc(struct device *dev) { struct dwc_pwm *dwc; =20 @@ -211,109 +163,7 @@ static struct dwc_pwm *dwc_pwm_alloc(struct device *d= ev) dev_set_drvdata(dev, dwc); return dwc; } - -static int dwc_pwm_probe(struct pci_dev *pci, const struct pci_device_id *= id) -{ - struct device *dev =3D &pci->dev; - struct dwc_pwm *dwc; - int ret; - - dwc =3D dwc_pwm_alloc(dev); - if (!dwc) - return -ENOMEM; - - ret =3D pcim_enable_device(pci); - if (ret) { - dev_err(dev, "Failed to enable device (%pe)\n", ERR_PTR(ret)); - return ret; - } - - pci_set_master(pci); - - ret =3D pcim_iomap_regions(pci, BIT(0), pci_name(pci)); - if (ret) { - dev_err(dev, "Failed to iomap PCI BAR (%pe)\n", ERR_PTR(ret)); - return ret; - } - - dwc->base =3D pcim_iomap_table(pci)[0]; - if (!dwc->base) { - dev_err(dev, "Base address missing\n"); - return -ENOMEM; - } - - ret =3D devm_pwmchip_add(dev, &dwc->chip); - if (ret) - return ret; - - pm_runtime_put(dev); - pm_runtime_allow(dev); - - return 0; -} - -static void dwc_pwm_remove(struct pci_dev *pci) -{ - pm_runtime_forbid(&pci->dev); - pm_runtime_get_noresume(&pci->dev); -} - -#ifdef CONFIG_PM_SLEEP -static int dwc_pwm_suspend(struct device *dev) -{ - struct pci_dev *pdev =3D container_of(dev, struct pci_dev, dev); - struct dwc_pwm *dwc =3D pci_get_drvdata(pdev); - int i; - - for (i =3D 0; i < DWC_TIMERS_TOTAL; i++) { - if (dwc->chip.pwms[i].state.enabled) { - dev_err(dev, "PWM %u in use by consumer (%s)\n", - i, dwc->chip.pwms[i].label); - return -EBUSY; - } - dwc->ctx[i].cnt =3D dwc_pwm_readl(dwc, DWC_TIM_LD_CNT(i)); - dwc->ctx[i].cnt2 =3D dwc_pwm_readl(dwc, DWC_TIM_LD_CNT2(i)); - dwc->ctx[i].ctrl =3D dwc_pwm_readl(dwc, DWC_TIM_CTRL(i)); - } - - return 0; -} - -static int dwc_pwm_resume(struct device *dev) -{ - struct pci_dev *pdev =3D container_of(dev, struct pci_dev, dev); - struct dwc_pwm *dwc =3D pci_get_drvdata(pdev); - int i; - - for (i =3D 0; i < DWC_TIMERS_TOTAL; i++) { - dwc_pwm_writel(dwc, dwc->ctx[i].cnt, DWC_TIM_LD_CNT(i)); - dwc_pwm_writel(dwc, dwc->ctx[i].cnt2, DWC_TIM_LD_CNT2(i)); - dwc_pwm_writel(dwc, dwc->ctx[i].ctrl, DWC_TIM_CTRL(i)); - } - - return 0; -} -#endif - -static SIMPLE_DEV_PM_OPS(dwc_pwm_pm_ops, dwc_pwm_suspend, dwc_pwm_resume); - -static const struct pci_device_id dwc_pwm_id_table[] =3D { - { PCI_VDEVICE(INTEL, 0x4bb7) }, /* Elkhart Lake */ - { } /* Terminating Entry */ -}; -MODULE_DEVICE_TABLE(pci, dwc_pwm_id_table); - -static struct pci_driver dwc_pwm_driver =3D { - .name =3D "pwm-dwc", - .probe =3D dwc_pwm_probe, - .remove =3D dwc_pwm_remove, - .id_table =3D dwc_pwm_id_table, - .driver =3D { - .pm =3D &dwc_pwm_pm_ops, - }, -}; - -module_pci_driver(dwc_pwm_driver); +EXPORT_SYMBOL_GPL(dwc_pwm_alloc); =20 MODULE_AUTHOR("Felipe Balbi (Intel)"); MODULE_AUTHOR("Jarkko Nikula "); diff --git a/drivers/pwm/pwm-dwc.h b/drivers/pwm/pwm-dwc.h new file mode 100644 index 000000000000..68f98eb76152 --- /dev/null +++ b/drivers/pwm/pwm-dwc.h @@ -0,0 +1,58 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * DesignWare PWM Controller driver + * + * Copyright (C) 2018-2020 Intel Corporation + * + * Author: Felipe Balbi (Intel) + * Author: Jarkko Nikula + * Author: Raymond Tan + */ + +#define DWC_TIM_LD_CNT(n) ((n) * 0x14) +#define DWC_TIM_LD_CNT2(n) (((n) * 4) + 0xb0) +#define DWC_TIM_CUR_VAL(n) (((n) * 0x14) + 0x04) +#define DWC_TIM_CTRL(n) (((n) * 0x14) + 0x08) +#define DWC_TIM_EOI(n) (((n) * 0x14) + 0x0c) +#define DWC_TIM_INT_STS(n) (((n) * 0x14) + 0x10) + +#define DWC_TIMERS_INT_STS 0xa0 +#define DWC_TIMERS_EOI 0xa4 +#define DWC_TIMERS_RAW_INT_STS 0xa8 +#define DWC_TIMERS_COMP_VERSION 0xac + +#define DWC_TIMERS_TOTAL 8 +#define DWC_CLK_PERIOD_NS 10 + +/* Timer Control Register */ +#define DWC_TIM_CTRL_EN BIT(0) +#define DWC_TIM_CTRL_MODE BIT(1) +#define DWC_TIM_CTRL_MODE_FREE (0 << 1) +#define DWC_TIM_CTRL_MODE_USER (1 << 1) +#define DWC_TIM_CTRL_INT_MASK BIT(2) +#define DWC_TIM_CTRL_PWM BIT(3) + +struct dwc_pwm_ctx { + u32 cnt; + u32 cnt2; + u32 ctrl; +}; + +struct dwc_pwm { + struct pwm_chip chip; + void __iomem *base; + struct dwc_pwm_ctx ctx[DWC_TIMERS_TOTAL]; +}; +#define to_dwc_pwm(p) (container_of((p), struct dwc_pwm, chip)) + +static inline u32 dwc_pwm_readl(struct dwc_pwm *dwc, u32 offset) +{ + return readl(dwc->base + offset); +} + +static inline void dwc_pwm_writel(struct dwc_pwm *dwc, u32 value, u32 offs= et) +{ + writel(value, dwc->base + offset); +} + +extern struct dwc_pwm *dwc_pwm_alloc(struct device *dev); --=20 2.35.1 From nobody Sat Apr 11 02:17:42 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B3FC2C32789 for ; Tue, 16 Aug 2022 21:15:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237561AbiHPVPb (ORCPT ); Tue, 16 Aug 2022 17:15:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54664 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237517AbiHPVPN (ORCPT ); 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Tue, 16 Aug 2022 14:15:01 -0700 (PDT) From: Ben Dooks To: linux-pwm@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Lee Jones , u.kleine-koenig@pengutronix.de, Thierry Reding , Krzysztof Kozlowski , Greentime Hu , jarkko.nikula@linux.intel.com, William Salmon , Jude Onyenegecha , Ben Dooks Subject: [RFC v4 07/10] pwm: dwc: make timer clock configurable Date: Tue, 16 Aug 2022 22:14:51 +0100 Message-Id: <20220816211454.237751-8-ben.dooks@sifive.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220816211454.237751-1-ben.dooks@sifive.com> References: <20220816211454.237751-1-ben.dooks@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add a configurable clock base rate for the pwm as when being built for non-PCI the block may be sourced from an internal clock. Signed-off-by: Ben Dooks --- v4: - moved earlier before the of changes to make the of changes one patch v2: - removed the ifdef and merged the other clock patch in here --- drivers/pwm/pwm-dwc-pci.c | 1 + drivers/pwm/pwm-dwc.c | 10 ++++++---- drivers/pwm/pwm-dwc.h | 2 ++ 3 files changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/pwm/pwm-dwc-pci.c b/drivers/pwm/pwm-dwc-pci.c index 2213d0e7f3c8..949423e368f9 100644 --- a/drivers/pwm/pwm-dwc-pci.c +++ b/drivers/pwm/pwm-dwc-pci.c @@ -20,6 +20,7 @@ #include #include #include +#include =20 #include "pwm-dwc.h" =20 diff --git a/drivers/pwm/pwm-dwc.c b/drivers/pwm/pwm-dwc.c index 90a8ae1252a1..1251620ab771 100644 --- a/drivers/pwm/pwm-dwc.c +++ b/drivers/pwm/pwm-dwc.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include =20 @@ -47,13 +48,13 @@ static int __dwc_pwm_configure_timer(struct dwc_pwm *dw= c, * periods and check are the result within HW limits between 1 and * 2^32 periods. */ - tmp =3D DIV_ROUND_CLOSEST_ULL(state->duty_cycle, DWC_CLK_PERIOD_NS); + tmp =3D DIV_ROUND_CLOSEST_ULL(state->duty_cycle, dwc->clk_ns); if (tmp < 1 || tmp > (1ULL << 32)) return -ERANGE; low =3D tmp - 1; =20 tmp =3D DIV_ROUND_CLOSEST_ULL(state->period - state->duty_cycle, - DWC_CLK_PERIOD_NS); + dwc->clk_ns); if (tmp < 1 || tmp > (1ULL << 32)) return -ERANGE; high =3D tmp - 1; @@ -128,12 +129,12 @@ static void dwc_pwm_get_state(struct pwm_chip *chip, = struct pwm_device *pwm, =20 duty =3D dwc_pwm_readl(dwc, DWC_TIM_LD_CNT(pwm->hwpwm)); duty +=3D 1; - duty *=3D DWC_CLK_PERIOD_NS; + duty *=3D dwc->clk_ns; state->duty_cycle =3D duty; =20 period =3D dwc_pwm_readl(dwc, DWC_TIM_LD_CNT2(pwm->hwpwm)); period +=3D 1; - period *=3D DWC_CLK_PERIOD_NS; + period *=3D dwc->clk_ns; period +=3D duty; state->period =3D period; =20 @@ -156,6 +157,7 @@ struct dwc_pwm *dwc_pwm_alloc(struct device *dev) if (!dwc) return NULL; =20 + dwc->clk_ns =3D 10; dwc->chip.dev =3D dev; dwc->chip.ops =3D &dwc_pwm_ops; dwc->chip.npwm =3D DWC_TIMERS_TOTAL; diff --git a/drivers/pwm/pwm-dwc.h b/drivers/pwm/pwm-dwc.h index 68f98eb76152..e5a1f7be7bc8 100644 --- a/drivers/pwm/pwm-dwc.h +++ b/drivers/pwm/pwm-dwc.h @@ -41,6 +41,8 @@ struct dwc_pwm_ctx { struct dwc_pwm { struct pwm_chip chip; void __iomem *base; + struct clk *clk; + unsigned int clk_ns; struct dwc_pwm_ctx ctx[DWC_TIMERS_TOTAL]; }; #define to_dwc_pwm(p) (container_of((p), struct dwc_pwm, chip)) --=20 2.35.1 From nobody Sat Apr 11 02:17:42 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 09425C25B0E for ; Tue, 16 Aug 2022 21:15:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237623AbiHPVPm (ORCPT ); Tue, 16 Aug 2022 17:15:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54684 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237552AbiHPVPV (ORCPT ); Tue, 16 Aug 2022 17:15:21 -0400 Received: from mail-wr1-x42e.google.com (mail-wr1-x42e.google.com [IPv6:2a00:1450:4864:20::42e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C723D83BFA for ; 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charset="utf-8" The dwc pwm controller can be used in non-PCI systems, so allow either platform or OF based probing. Signed-off-by: Ben Dooks --- v4: - split the of code out of the core - moved the compile test code earlier - fixed review comments - used NS_PER_SEC - use devm_clk_get_enabled v3: - changed compatible name --- drivers/pwm/Kconfig | 9 +++++ drivers/pwm/Makefile | 1 + drivers/pwm/pwm-dwc-of.c | 78 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 88 insertions(+) create mode 100644 drivers/pwm/pwm-dwc-of.c diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index a9f1c554db2b..f1735653365f 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -192,6 +192,15 @@ config PWM_DWC_PCI To compile this driver as a module, choose M here: the module will be called pwm-dwc-pci. =20 +config PWM_DWC_OF + tristate "DesignWare PWM Controller (OF bus) + depends on PWM_DWC && OF + help + PWM driver for Synopsys DWC PWM Controller on an OF bus. + + To compile this driver as a module, choose M here: the module + will be called pwm-dwc-of. + config PWM_EP93XX tristate "Cirrus Logic EP93xx PWM support" depends on ARCH_EP93XX || COMPILE_TEST diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index a70d36623129..d1fd1641f077 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -15,6 +15,7 @@ obj-$(CONFIG_PWM_CLPS711X) +=3D pwm-clps711x.o obj-$(CONFIG_PWM_CRC) +=3D pwm-crc.o obj-$(CONFIG_PWM_CROS_EC) +=3D pwm-cros-ec.o obj-$(CONFIG_PWM_DWC) +=3D pwm-dwc.o +obj-$(CONFIG_PWM_DWC_OF) +=3D pwm-dwc-of.o obj-$(CONFIG_PWM_DWC_PCI) +=3D pwm-dwc-pci.o obj-$(CONFIG_PWM_EP93XX) +=3D pwm-ep93xx.o obj-$(CONFIG_PWM_FSL_FTM) +=3D pwm-fsl-ftm.o diff --git a/drivers/pwm/pwm-dwc-of.c b/drivers/pwm/pwm-dwc-of.c new file mode 100644 index 000000000000..d18fac287325 --- /dev/null +++ b/drivers/pwm/pwm-dwc-of.c @@ -0,0 +1,78 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * DesignWare PWM Controller driver OF + * + * Copyright (C) 2022 SiFive, Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "pwm-dwc.h" + +static int dwc_pwm_plat_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct dwc_pwm *dwc; + int ret; + + dwc =3D dwc_pwm_alloc(dev); + if (!dwc) + return -ENOMEM; + + dwc->base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(dwc->base)) + return dev_err_probe(dev, PTR_ERR(dwc->base), + "failed to map IO\n"); + + dwc->clk =3D devm_clk_get_enabled(dev, "timer"); + if (IS_ERR(dwc->clk)) + return dev_err_probe(dev, PTR_ERR(dwc->clk), + "failed to get timer clock\n"); + + clk_prepare_enable(dwc->clk); + dwc->clk_ns =3D NSEC_PER_SEC / clk_get_rate(dwc->clk); + + ret =3D devm_pwmchip_add(dev, &dwc->chip); + if (ret) + return ret; + + return 0; +} + +static int dwc_pwm_plat_remove(struct platform_device *pdev) +{ + struct dwc_pwm *dwc =3D platform_get_drvdata(pdev); + + clk_disable_unprepare(dwc->clk); + return 0; +} + +static const struct of_device_id dwc_pwm_dt_ids[] =3D { + { .compatible =3D "snps,dw-apb-timers-pwm2" }, + { }, +}; +MODULE_DEVICE_TABLE(of, dwc_pwm_dt_ids); + +static struct platform_driver dwc_pwm_plat_driver =3D { + .driver =3D { + .name =3D "dwc-pwm", + .of_match_table =3D dwc_pwm_dt_ids, + }, + .probe =3D dwc_pwm_plat_probe, + .remove =3D dwc_pwm_plat_remove, +}; + +module_platform_driver(dwc_pwm_plat_driver); + +MODULE_ALIAS("platform:dwc-pwm-of"); +MODULE_AUTHOR("Ben Dooks "); +MODULE_DESCRIPTION("DesignWare PWM Controller"); +MODULE_LICENSE("GPL"); --=20 2.35.1 From nobody Sat Apr 11 02:17:42 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E8190C25B0E for ; Tue, 16 Aug 2022 21:15:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237634AbiHPVPq (ORCPT ); Tue, 16 Aug 2022 17:15:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54818 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237567AbiHPVPW (ORCPT ); Tue, 16 Aug 2022 17:15:22 -0400 Received: from mail-wr1-x42b.google.com (mail-wr1-x42b.google.com [IPv6:2a00:1450:4864:20::42b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C1CCF88DF6 for ; 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charset="utf-8" Add snps,pwm-number property to indicate if the block does not have all 8 of the PWM blocks. Not sure if this should be a general PWM property consider optional for all PWM types, so have added a specific one here (there is only one other controller with a property for PWM count at the moment) Signed-off-by: Ben Dooks --- drivers/pwm/pwm-dwc-of.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/pwm/pwm-dwc-of.c b/drivers/pwm/pwm-dwc-of.c index d18fac287325..65c7e6621bba 100644 --- a/drivers/pwm/pwm-dwc-of.c +++ b/drivers/pwm/pwm-dwc-of.c @@ -21,12 +21,20 @@ static int dwc_pwm_plat_probe(struct platform_device *p= dev) { struct device *dev =3D &pdev->dev; struct dwc_pwm *dwc; + u32 nr_pwm; int ret; =20 dwc =3D dwc_pwm_alloc(dev); if (!dwc) return -ENOMEM; =20 + if (!device_property_read_u32(dev, "snps,pwm-number", &nr_pwm)) { + if (nr_pwm > DWC_TIMERS_TOTAL) + dev_err(dev, "too many PWMs specified (%d)\n", nr_pwm); + else + dwc->chip.npwm =3D nr_pwm; + } + dwc->base =3D devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(dwc->base)) return dev_err_probe(dev, PTR_ERR(dwc->base), --=20 2.35.1 From nobody Sat Apr 11 02:17:42 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E9C57C25B0E for ; Tue, 16 Aug 2022 21:15:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237640AbiHPVPu (ORCPT ); Tue, 16 Aug 2022 17:15:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54550 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237566AbiHPVPW (ORCPT ); Tue, 16 Aug 2022 17:15:22 -0400 Received: from mail-wr1-x430.google.com (mail-wr1-x430.google.com [IPv6:2a00:1450:4864:20::430]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 52523895C3 for ; Tue, 16 Aug 2022 14:15:05 -0700 (PDT) Received: by mail-wr1-x430.google.com with SMTP id n7so2849310wrv.4 for ; Tue, 16 Aug 2022 14:15:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=phcPBaGxOFAemR9YFsCDrE8yrlHvz+AvjsJ/jn+/KmI=; b=D2LBTNDmEF2+Dr1NzlXFxUrarWUqPPataJ7eBvvm12Ez5MuwP9UXnt3hAVGjut9uaW 10d7KRwvsmRnkblDnIGWGr9woJ/rSO57iN7N5bCNHYrBAjuOcatAK7hi/r7iiB72izxY gMkFSK3VpssRb6tFteFowVmh6kBf31UNSAwgB1Upw/iNMmHfIbtzmtvkFRiiry/5CKFL JK/gdsnf6uNRrgEMoZnOzMRaAtyONnn1gbXy3s6RP+bPuE6EuuyZ4zgaW5Aj/063xIJE iTwG2P79SecEn4QjY+LjHcn/8Hxsv7H5NiNOOMNWaYxGk5kF4CnT/S9F8CfZzq3EjblN ErxA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=phcPBaGxOFAemR9YFsCDrE8yrlHvz+AvjsJ/jn+/KmI=; b=kbvkjIIFJw37HqRK7Vio4LvpF6Pi3FlaKK4kFzvySxfHKo5BUAxZ17tM8wJY7AqVj3 2VZzUFreDTtXTOzqm2c8tzTMoWayL/tlfU9EVAhuQkzONY272zxibDwHWKD/4LgnfiQ2 yU2jd40TKOYYU8phgCnRF+7J2r7J5RyoZKU9USgK+0HuR2a44vJRgOO7mApkC6uKmiDY PiavmvsrDyrdiA7cteiMkref3rCHeZY/fwZ7yXgTb+/9WC3ExAgOIm3eS/FfigniGRLA Z7a/ZNICTXjJGS0PlJCcUDlzB2dYAYpS6Y3gbh+ROc4zGyaKO+3Ff7YtdBlFUQpk7jaH HFnA== X-Gm-Message-State: ACgBeo3BfikGxDGI+vFdeJHalNVrUoTUwqKjLP/az/h3WOVxz5NF+GyB 5dTLWZxtUwFAjqjW0G8NnUolrw== X-Google-Smtp-Source: AA6agR7I7O5srqcLe0uvZsPtmDixINs6HcsyX4Rz7ZRgeDlHqmucBoGATsBy2Nq2Jzcldqq8Kaujkw== X-Received: by 2002:a5d:4b87:0:b0:21e:ffa6:a3a6 with SMTP id b7-20020a5d4b87000000b0021effa6a3a6mr12289683wrt.418.1660684504334; Tue, 16 Aug 2022 14:15:04 -0700 (PDT) Received: from rainbowdash.office.codethink.co.uk ([167.98.27.226]) by smtp.gmail.com with ESMTPSA id r4-20020a1c4404000000b003a3170a7af9sm23913wma.4.2022.08.16.14.15.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Aug 2022 14:15:04 -0700 (PDT) From: Ben Dooks To: linux-pwm@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Lee Jones , u.kleine-koenig@pengutronix.de, Thierry Reding , Krzysztof Kozlowski , Greentime Hu , jarkko.nikula@linux.intel.com, William Salmon , Jude Onyenegecha , Ben Dooks Subject: [RFC v4 10/10] pwm: dwc: add PWM bit unset in get_state call Date: Tue, 16 Aug 2022 22:14:54 +0100 Message-Id: <20220816211454.237751-11-ben.dooks@sifive.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220816211454.237751-1-ben.dooks@sifive.com> References: <20220816211454.237751-1-ben.dooks@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" If we are not in PWM mode, then the output is technically a 50% output based on a single timer instead of the high-low based on the two counters. Add a check for the PWM mode in dwc_pwm_get_state() and if DWC_TIM_CTRL_PWM is not set, then return a 50% cycle. This may only be an issue on initialisation, as the rest of the code currently assumes we're always going to have the extended PWM mode using two counters. Signed-off-by: Ben Dooks --- v4: - fixed review comment on mulit-line calculations --- drivers/pwm/pwm-dwc.c | 29 ++++++++++++++++++----------- 1 file changed, 18 insertions(+), 11 deletions(-) diff --git a/drivers/pwm/pwm-dwc.c b/drivers/pwm/pwm-dwc.c index 1251620ab771..5ef0fe7ea3e9 100644 --- a/drivers/pwm/pwm-dwc.c +++ b/drivers/pwm/pwm-dwc.c @@ -121,23 +121,30 @@ static void dwc_pwm_get_state(struct pwm_chip *chip, = struct pwm_device *pwm, { struct dwc_pwm *dwc =3D to_dwc_pwm(chip); u64 duty, period; + u32 ctrl, ld, ld2; =20 pm_runtime_get_sync(chip->dev); =20 - state->enabled =3D !!(dwc_pwm_readl(dwc, - DWC_TIM_CTRL(pwm->hwpwm)) & DWC_TIM_CTRL_EN); + ctrl =3D dwc_pwm_readl(dwc, DWC_TIM_CTRL(pwm->hwpwm)); + ld =3D dwc_pwm_readl(dwc, DWC_TIM_LD_CNT(pwm->hwpwm)); + ld2 =3D dwc_pwm_readl(dwc, DWC_TIM_LD_CNT2(pwm->hwpwm)); =20 - duty =3D dwc_pwm_readl(dwc, DWC_TIM_LD_CNT(pwm->hwpwm)); - duty +=3D 1; - duty *=3D dwc->clk_ns; - state->duty_cycle =3D duty; + state->enabled =3D !!(ctrl & DWC_TIM_CTRL_EN); =20 - period =3D dwc_pwm_readl(dwc, DWC_TIM_LD_CNT2(pwm->hwpwm)); - period +=3D 1; - period *=3D dwc->clk_ns; - period +=3D duty; - state->period =3D period; + /* If we're not in PWM, technically the output is a 50-50 + * based on the timer load-count only. + */ + if (ctrl & DWC_TIM_CTRL_PWM) { + duty =3D (ld + 1) * dwc->clk_ns; + period =3D (ld2 + 1) * dwc->clk_ns; + period +=3D duty; + } else { + duty =3D (ld + 1) * dwc->clk_ns; + period =3D duty * 2; + } =20 + state->period =3D period; + state->duty_cycle =3D duty; state->polarity =3D PWM_POLARITY_INVERSED; =20 pm_runtime_put_sync(chip->dev); --=20 2.35.1