From nobody Mon Sep 29 21:17:43 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A886AC282E7 for ; Tue, 16 Aug 2022 04:52:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231710AbiHPEwP (ORCPT ); Tue, 16 Aug 2022 00:52:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56790 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232662AbiHPErl (ORCPT ); Tue, 16 Aug 2022 00:47:41 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B3419B07C2; Mon, 15 Aug 2022 13:43:19 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id BF88860F60; Mon, 15 Aug 2022 20:43:18 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id C1D9DC433C1; Mon, 15 Aug 2022 20:43:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1660596198; bh=8h8eRryY+Nlcy5QakMX7qwQudFKSukdR+46jHwLhkvk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=MQHMQWAMLFVhqExyA1393Fe1KH/uIrirAmcYGKhRsCVVYNT1tIzBk1vcfb4CFcWVj QMlYylzR5zgKgjrsm1FIgx6YzmGJOCEHnSo7h4qcnF/S7SectZ0+u2HwEZ3TclQWPi gqujlRYKtKO2HRzFZqv7nWzwaXOm9dU5XawrPLnQ= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Douglas Anderson , Vijaya Krishna Nivarthi , Sasha Levin Subject: [PATCH 5.19 1002/1157] tty: serial: qcom-geni-serial: Fix get_clk_div_rate() which otherwise could return a sub-optimal clock rate. Date: Mon, 15 Aug 2022 20:05:58 +0200 Message-Id: <20220815180519.873396149@linuxfoundation.org> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220815180439.416659447@linuxfoundation.org> References: <20220815180439.416659447@linuxfoundation.org> User-Agent: quilt/0.67 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Vijaya Krishna Nivarthi [ Upstream commit c474c775716edd46a51bf8161142bbd1545f8733 ] In the logic around call to clk_round_rate(), for some corner conditions, get_clk_div_rate() could return an sub-optimal clock rate. Also, if an exact clock rate was not found lowest clock was being returned. Search for suitable clock rate in 2 steps a) exact match or within 2% tolerance b) within 5% tolerance This also takes care of corner conditions. Fixes: c2194bc999d4 ("tty: serial: qcom-geni-serial: Remove uart frequency = table. Instead, find suitable frequency with call to clk_round_rate") Reviewed-by: Douglas Anderson Signed-off-by: Vijaya Krishna Nivarthi Link: https://lore.kernel.org/r/1657911343-1909-1-git-send-email-quic_vniva= rth@quicinc.com Signed-off-by: Greg Kroah-Hartman Signed-off-by: Sasha Levin --- drivers/tty/serial/qcom_geni_serial.c | 88 ++++++++++++++++----------- 1 file changed, 53 insertions(+), 35 deletions(-) diff --git a/drivers/tty/serial/qcom_geni_serial.c b/drivers/tty/serial/qco= m_geni_serial.c index f8f950641ad9..f754619451dc 100644 --- a/drivers/tty/serial/qcom_geni_serial.c +++ b/drivers/tty/serial/qcom_geni_serial.c @@ -940,52 +940,63 @@ static int qcom_geni_serial_startup(struct uart_port = *uport) return 0; } =20 -static unsigned long get_clk_div_rate(struct clk *clk, unsigned int baud, - unsigned int sampling_rate, unsigned int *clk_div) +static unsigned long find_clk_rate_in_tol(struct clk *clk, unsigned int de= sired_clk, + unsigned int *clk_div, unsigned int percent_tol) { - unsigned long ser_clk; - unsigned long desired_clk; - unsigned long freq, prev; + unsigned long freq; unsigned long div, maxdiv; - int64_t mult; - - desired_clk =3D baud * sampling_rate; - if (!desired_clk) { - pr_err("%s: Invalid frequency\n", __func__); - return 0; - } + u64 mult; + unsigned long offset, abs_tol, achieved; =20 + abs_tol =3D div_u64((u64)desired_clk * percent_tol, 100); maxdiv =3D CLK_DIV_MSK >> CLK_DIV_SHFT; - prev =3D 0; - - for (div =3D 1; div <=3D maxdiv; div++) { - mult =3D div * desired_clk; - if (mult > ULONG_MAX) + div =3D 1; + while (div <=3D maxdiv) { + mult =3D (u64)div * desired_clk; + if (mult !=3D (unsigned long)mult) break; =20 - freq =3D clk_round_rate(clk, (unsigned long)mult); - if (!(freq % desired_clk)) { - ser_clk =3D freq; - break; - } + offset =3D div * abs_tol; + freq =3D clk_round_rate(clk, mult - offset); =20 - if (!prev) - ser_clk =3D freq; - else if (prev =3D=3D freq) + /* Can only get lower if we're done */ + if (freq < mult - offset) break; =20 - prev =3D freq; - } + /* + * Re-calculate div in case rounding skipped rates but we + * ended up at a good one, then check for a match. + */ + div =3D DIV_ROUND_CLOSEST(freq, desired_clk); + achieved =3D DIV_ROUND_CLOSEST(freq, div); + if (achieved <=3D desired_clk + abs_tol && + achieved >=3D desired_clk - abs_tol) { + *clk_div =3D div; + return freq; + } =20 - if (!ser_clk) { - pr_err("%s: Can't find matching DFS entry for baud %d\n", - __func__, baud); - return ser_clk; + div =3D DIV_ROUND_UP(freq, desired_clk); } =20 - *clk_div =3D ser_clk / desired_clk; - if (!(*clk_div)) - *clk_div =3D 1; + return 0; +} + +static unsigned long get_clk_div_rate(struct clk *clk, unsigned int baud, + unsigned int sampling_rate, unsigned int *clk_div) +{ + unsigned long ser_clk; + unsigned long desired_clk; + + desired_clk =3D baud * sampling_rate; + if (!desired_clk) + return 0; + + /* + * try to find a clock rate within 2% tolerance, then within 5% + */ + ser_clk =3D find_clk_rate_in_tol(clk, desired_clk, clk_div, 2); + if (!ser_clk) + ser_clk =3D find_clk_rate_in_tol(clk, desired_clk, clk_div, 5); =20 return ser_clk; } @@ -1020,8 +1031,15 @@ static void qcom_geni_serial_set_termios(struct uart= _port *uport, =20 clk_rate =3D get_clk_div_rate(port->se.clk, baud, sampling_rate, &clk_div); - if (!clk_rate) + if (!clk_rate) { + dev_err(port->se.dev, + "Couldn't find suitable clock rate for %lu\n", + baud * sampling_rate); goto out_restart_rx; + } + + dev_dbg(port->se.dev, "desired_rate-%lu, clk_rate-%lu, clk_div-%u\n", + baud * sampling_rate, clk_rate, clk_div); =20 uport->uartclk =3D clk_rate; dev_pm_opp_set_rate(uport->dev, clk_rate); --=20 2.35.1