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Wysocki" , Sasha Levin Subject: [PATCH 5.18 1033/1095] intel_idle: make SPR C1 and C1E be independent Date: Mon, 15 Aug 2022 20:07:12 +0200 Message-Id: <20220815180511.794102365@linuxfoundation.org> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220815180429.240518113@linuxfoundation.org> References: <20220815180429.240518113@linuxfoundation.org> User-Agent: quilt/0.67 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Artem Bityutskiy [ Upstream commit 1548fac47a114b42063def551eb152a536ed9697 ] This patch partially reverts the changes made by the following commit: da0e58c038e6 intel_idle: add 'preferred_cstates' module argument As that commit describes, on early Sapphire Rapids Xeon platforms the C1 and C1E states were mutually exclusive, so that users could only have either C1= and C6, or C1E and C6. However, Intel firmware engineers managed to remove this limitation and mak= e C1 and C1E to be completely independent, just like on previous Xeon platforms. Therefore, this patch: * Removes commentary describing the old, and now non-existing SPR C1E limitation. * Marks SPR C1E as available by default. * Removes the 'preferred_cstates' parameter handling for SPR. Both C1 and C1E will be available regardless of 'preferred_cstates' value. We expect that all SPR systems are shipping with new firmware, which includ= es the C1/C1E improvement. Cc: v5.18+ # v5.18+ Signed-off-by: Artem Bityutskiy Signed-off-by: Rafael J. Wysocki Signed-off-by: Sasha Levin --- drivers/idle/intel_idle.c | 24 +----------------------- 1 file changed, 1 insertion(+), 23 deletions(-) diff --git a/drivers/idle/intel_idle.c b/drivers/idle/intel_idle.c index 907700d1e78e..9515a3146dc9 100644 --- a/drivers/idle/intel_idle.c +++ b/drivers/idle/intel_idle.c @@ -911,16 +911,6 @@ static struct cpuidle_state adl_l_cstates[] __initdata= =3D { .enter =3D NULL } }; =20 -/* - * On Sapphire Rapids Xeon C1 has to be disabled if C1E is enabled, and vi= ce - * versa. On SPR C1E is enabled only if "C1E promotion" bit is set in - * MSR_IA32_POWER_CTL. But in this case there effectively no C1, because C1 - * requests are promoted to C1E. If the "C1E promotion" bit is cleared, th= en - * both C1 and C1E requests end up with C1, so there is effectively no C1E. - * - * By default we enable C1 and disable C1E by marking it with - * 'CPUIDLE_FLAG_UNUSABLE'. - */ static struct cpuidle_state spr_cstates[] __initdata =3D { { .name =3D "C1", @@ -933,8 +923,7 @@ static struct cpuidle_state spr_cstates[] __initdata = =3D { { .name =3D "C1E", .desc =3D "MWAIT 0x01", - .flags =3D MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE | - CPUIDLE_FLAG_UNUSABLE, + .flags =3D MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE, .exit_latency =3D 2, .target_residency =3D 4, .enter =3D &intel_idle, @@ -1756,17 +1745,6 @@ static void __init spr_idle_state_table_update(void) { unsigned long long msr; =20 - /* Check if user prefers C1E over C1. */ - if ((preferred_states_mask & BIT(2)) && - !(preferred_states_mask & BIT(1))) { - /* Disable C1 and enable C1E. */ - spr_cstates[0].flags |=3D CPUIDLE_FLAG_UNUSABLE; - spr_cstates[1].flags &=3D ~CPUIDLE_FLAG_UNUSABLE; - - /* Enable C1E using the "C1E promotion" bit. */ - c1e_promotion =3D C1E_PROMOTION_ENABLE; - } - /* * By default, the C6 state assumes the worst-case scenario of package * C6. However, if PC6 is disabled, we update the numbers to match --=20 2.35.1