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Wysocki" , Sasha Levin Subject: [PATCH 5.18 1032/1095] intel_idle: Add AlderLake support Date: Mon, 15 Aug 2022 20:07:11 +0200 Message-Id: <20220815180511.754732096@linuxfoundation.org> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220815180429.240518113@linuxfoundation.org> References: <20220815180429.240518113@linuxfoundation.org> User-Agent: quilt/0.67 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Zhang Rui [ Upstream commit d1cf8bbfed1edc5108220342ab39e4544d55fbc3 ] Similar to SPR, the C1 and C1E states on ADL are mutually exclusive. Only one of them can be enabled at a time. But contrast to SPR, which usually has a strong latency requirement as a Xeon processor, C1E is preferred on ADL for better energy efficiency. Add custom C-state tables for ADL with both C1 and C1E, and 1. Enable the "C1E promotion" bit in MSR_IA32_POWER_CTL and mark C1 with the CPUIDLE_FLAG_UNUSABLE flag, so C1 is not available by default. 2. Add support for the "preferred_cstates" module parameter, so that users can choose to use C1 instead of C1E by booting with "intel_idle.preferred_cstates=3D2". Separate custom C-state tables are introduced for the ADL mobile and desktop processors, because of the exit latency differences between these two variants, especially with respect to PC10. Signed-off-by: Zhang Rui [ rjw: Changelog edits, code rearrangement ] Signed-off-by: Rafael J. Wysocki Signed-off-by: Sasha Levin --- drivers/idle/intel_idle.c | 133 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 133 insertions(+) diff --git a/drivers/idle/intel_idle.c b/drivers/idle/intel_idle.c index 47b68c6071be..907700d1e78e 100644 --- a/drivers/idle/intel_idle.c +++ b/drivers/idle/intel_idle.c @@ -811,6 +811,106 @@ static struct cpuidle_state icx_cstates[] __initdata = =3D { .enter =3D NULL } }; =20 +/* + * On AlderLake C1 has to be disabled if C1E is enabled, and vice versa. + * C1E is enabled only if "C1E promotion" bit is set in MSR_IA32_POWER_CTL. + * But in this case there is effectively no C1, because C1 requests are + * promoted to C1E. If the "C1E promotion" bit is cleared, then both C1 + * and C1E requests end up with C1, so there is effectively no C1E. + * + * By default we enable C1E and disable C1 by marking it with + * 'CPUIDLE_FLAG_UNUSABLE'. + */ +static struct cpuidle_state adl_cstates[] __initdata =3D { + { + .name =3D "C1", + .desc =3D "MWAIT 0x00", + .flags =3D MWAIT2flg(0x00) | CPUIDLE_FLAG_UNUSABLE, + .exit_latency =3D 1, + .target_residency =3D 1, + .enter =3D &intel_idle, + .enter_s2idle =3D intel_idle_s2idle, }, + { + .name =3D "C1E", + .desc =3D "MWAIT 0x01", + .flags =3D MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE, + .exit_latency =3D 2, + .target_residency =3D 4, + .enter =3D &intel_idle, + .enter_s2idle =3D intel_idle_s2idle, }, + { + .name =3D "C6", + .desc =3D "MWAIT 0x20", + .flags =3D MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, + .exit_latency =3D 220, + .target_residency =3D 600, + .enter =3D &intel_idle, + .enter_s2idle =3D intel_idle_s2idle, }, + { + .name =3D "C8", + .desc =3D "MWAIT 0x40", + .flags =3D MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED, + .exit_latency =3D 280, + .target_residency =3D 800, + .enter =3D &intel_idle, + .enter_s2idle =3D intel_idle_s2idle, }, + { + .name =3D "C10", + .desc =3D "MWAIT 0x60", + .flags =3D MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED, + .exit_latency =3D 680, + .target_residency =3D 2000, + .enter =3D &intel_idle, + .enter_s2idle =3D intel_idle_s2idle, }, + { + .enter =3D NULL } +}; + +static struct cpuidle_state adl_l_cstates[] __initdata =3D { + { + .name =3D "C1", + .desc =3D "MWAIT 0x00", + .flags =3D MWAIT2flg(0x00) | CPUIDLE_FLAG_UNUSABLE, + .exit_latency =3D 1, + .target_residency =3D 1, + .enter =3D &intel_idle, + .enter_s2idle =3D intel_idle_s2idle, }, + { + .name =3D "C1E", + .desc =3D "MWAIT 0x01", + .flags =3D MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE, + .exit_latency =3D 2, + .target_residency =3D 4, + .enter =3D &intel_idle, + .enter_s2idle =3D intel_idle_s2idle, }, + { + .name =3D "C6", + .desc =3D "MWAIT 0x20", + .flags =3D MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, + .exit_latency =3D 170, + .target_residency =3D 500, + .enter =3D &intel_idle, + .enter_s2idle =3D intel_idle_s2idle, }, + { + .name =3D "C8", + .desc =3D "MWAIT 0x40", + .flags =3D MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED, + .exit_latency =3D 200, + .target_residency =3D 600, + .enter =3D &intel_idle, + .enter_s2idle =3D intel_idle_s2idle, }, + { + .name =3D "C10", + .desc =3D "MWAIT 0x60", + .flags =3D MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED, + .exit_latency =3D 230, + .target_residency =3D 700, + .enter =3D &intel_idle, + .enter_s2idle =3D intel_idle_s2idle, }, + { + .enter =3D NULL } +}; + /* * On Sapphire Rapids Xeon C1 has to be disabled if C1E is enabled, and vi= ce * versa. On SPR C1E is enabled only if "C1E promotion" bit is set in @@ -1194,6 +1294,14 @@ static const struct idle_cpu idle_cpu_icx __initcons= t =3D { .use_acpi =3D true, }; =20 +static const struct idle_cpu idle_cpu_adl __initconst =3D { + .state_table =3D adl_cstates, +}; + +static const struct idle_cpu idle_cpu_adl_l __initconst =3D { + .state_table =3D adl_l_cstates, +}; + static const struct idle_cpu idle_cpu_spr __initconst =3D { .state_table =3D spr_cstates, .disable_promotion_to_c1e =3D true, @@ -1262,6 +1370,8 @@ static const struct x86_cpu_id intel_idle_ids[] __ini= tconst =3D { X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_X, &idle_cpu_skx), X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_X, &idle_cpu_icx), X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_D, &idle_cpu_icx), + X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE, &idle_cpu_adl), + X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L, &idle_cpu_adl_l), X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X, &idle_cpu_spr), X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNL, &idle_cpu_knl), X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNM, &idle_cpu_knl), @@ -1620,6 +1730,25 @@ static void __init skx_idle_state_table_update(void) } } =20 +/** + * adl_idle_state_table_update - Adjust AlderLake idle states table. + */ +static void __init adl_idle_state_table_update(void) +{ + /* Check if user prefers C1 over C1E. */ + if (preferred_states_mask & BIT(1) && !(preferred_states_mask & BIT(2))) { + cpuidle_state_table[0].flags &=3D ~CPUIDLE_FLAG_UNUSABLE; + cpuidle_state_table[1].flags |=3D CPUIDLE_FLAG_UNUSABLE; + + /* Disable C1E by clearing the "C1E promotion" bit. */ + c1e_promotion =3D C1E_PROMOTION_DISABLE; + return; + } + + /* Make sure C1E is enabled by default */ + c1e_promotion =3D C1E_PROMOTION_ENABLE; +} + /** * spr_idle_state_table_update - Adjust Sapphire Rapids idle states table. */ @@ -1689,6 +1818,10 @@ static void __init intel_idle_init_cstates_icpu(stru= ct cpuidle_driver *drv) case INTEL_FAM6_SAPPHIRERAPIDS_X: spr_idle_state_table_update(); break; + case INTEL_FAM6_ALDERLAKE: + case INTEL_FAM6_ALDERLAKE_L: + adl_idle_state_table_update(); + break; } =20 for (cstate =3D 0; cstate < CPUIDLE_STATE_MAX; ++cstate) { --=20 2.35.1