From nobody Sat Apr 11 06:39:31 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B8C30C00140 for ; Mon, 15 Aug 2022 15:16:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242328AbiHOPQi (ORCPT ); Mon, 15 Aug 2022 11:16:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59268 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243063AbiHOPQV (ORCPT ); Mon, 15 Aug 2022 11:16:21 -0400 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 79FEF255B8; Mon, 15 Aug 2022 08:16:19 -0700 (PDT) X-IronPort-AV: E=Sophos;i="5.93,238,1654527600"; d="scan'208";a="129579724" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 16 Aug 2022 00:16:19 +0900 Received: from localhost.localdomain (unknown [10.226.36.204]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 0AF96400197E; Tue, 16 Aug 2022 00:16:14 +0900 (JST) From: Lad Prabhakar To: Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Geert Uytterhoeven Cc: Conor Dooley , Anup Patel , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Lad Prabhakar Subject: [PATCH v2 5/8] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC Date: Mon, 15 Aug 2022 16:14:48 +0100 Message-Id: <20220815151451.23293-6-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220815151451.23293-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20220815151451.23293-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add initial device tree for Renesas RZ/Five RISC-V CPU Core (AX45MP Single). Below is the list of IP blocks added in the initial SoC DTSI which can be used to boot via initramfs on RZ/Five SMARC EVK: - AX45MP CPU - CPG - PINCTRL - PLIC - SCIF0 - SYSC Signed-off-by: Lad Prabhakar Reviewed-by: Conor Dooley Reviewed-by: Geert Uytterhoeven --- v1->v2 * Dropped including makefile change * Updated ndev count --- arch/riscv/boot/dts/renesas/r9a07g043.dtsi | 121 +++++++++++++++++++++ 1 file changed, 121 insertions(+) create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043.dtsi diff --git a/arch/riscv/boot/dts/renesas/r9a07g043.dtsi b/arch/riscv/boot/d= ts/renesas/r9a07g043.dtsi new file mode 100644 index 000000000000..b288d2607796 --- /dev/null +++ b/arch/riscv/boot/dts/renesas/r9a07g043.dtsi @@ -0,0 +1,121 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/Five SoC + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +#include +#include + +/ { + compatible =3D "renesas,r9a07g043"; + #address-cells =3D <2>; + #size-cells =3D <2>; + + /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */ + extal_clk: extal-clk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + /* This value must be overridden by the board */ + clock-frequency =3D <0>; + }; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + timebase-frequency =3D <24000000>; + + ax45mp: cpu@0 { + compatible =3D "andestech,ax45mp", "riscv"; + device_type =3D "cpu"; + reg =3D <0x0>; + status =3D "okay"; + riscv,isa =3D "rv64imafdc"; + mmu-type =3D "riscv,sv39"; + i-cache-size =3D <0x8000>; + i-cache-line-size =3D <0x40>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <0x40>; + clocks =3D <&cpg CPG_CORE R9A07G043_AX45MP_CORE0_CLK>, + <&cpg CPG_CORE R9A07G043_AX45MP_ACLK>; + + cpu0_intc: interrupt-controller { + #interrupt-cells =3D <1>; + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + }; + }; + }; + + soc: soc { + compatible =3D "simple-bus"; + interrupt-parent =3D <&plic>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + scif0: serial@1004b800 { + compatible =3D "renesas,scif-r9a07g043", + "renesas,scif-r9a07g044"; + reg =3D <0 0x1004b800 0 0x400>; + interrupts =3D <412 IRQ_TYPE_LEVEL_HIGH>, + <414 IRQ_TYPE_LEVEL_HIGH>, + <415 IRQ_TYPE_LEVEL_HIGH>, + <413 IRQ_TYPE_LEVEL_HIGH>, + <416 IRQ_TYPE_LEVEL_HIGH>, + <416 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names =3D "eri", "rxi", "txi", + "bri", "dri", "tei"; + clocks =3D <&cpg CPG_MOD R9A07G043_SCIF0_CLK_PCK>; + clock-names =3D "fck"; + power-domains =3D <&cpg>; + resets =3D <&cpg R9A07G043_SCIF0_RST_SYSTEM_N>; + status =3D "disabled"; + }; + + cpg: clock-controller@11010000 { + compatible =3D "renesas,r9a07g043-cpg"; + reg =3D <0 0x11010000 0 0x10000>; + clocks =3D <&extal_clk>; + clock-names =3D "extal"; + #clock-cells =3D <2>; + #reset-cells =3D <1>; + #power-domain-cells =3D <0>; + }; + + sysc: system-controller@11020000 { + compatible =3D "renesas,r9a07g043-sysc"; + reg =3D <0 0x11020000 0 0x10000>; + status =3D "disabled"; + }; + + pinctrl: pinctrl@11030000 { + compatible =3D "renesas,r9a07g043-pinctrl"; + reg =3D <0 0x11030000 0 0x10000>; + gpio-controller; + #gpio-cells =3D <2>; + #interrupt-cells =3D <2>; + interrupt-controller; + gpio-ranges =3D <&pinctrl 0 0 152>; + clocks =3D <&cpg CPG_MOD R9A07G043_GPIO_HCLK>; + power-domains =3D <&cpg>; + resets =3D <&cpg R9A07G043_GPIO_RSTN>, + <&cpg R9A07G043_GPIO_PORT_RESETN>, + <&cpg R9A07G043_GPIO_SPARE_RESETN>; + }; + + plic: interrupt-controller@12c00000 { + compatible =3D "renesas,r9a07g043-plic", "andestech,nceplic100"; + #interrupt-cells =3D <2>; + #address-cells =3D <0>; + riscv,ndev =3D <512>; + interrupt-controller; + reg =3D <0x0 0x12c00000 0 0x400000>; + clocks =3D <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>; + power-domains =3D <&cpg>; + resets =3D <&cpg R9A07G043_NCEPLIC_ARESETN>; + interrupts-extended =3D <&cpu0_intc 11 &cpu0_intc 9>; + }; + }; +}; --=20 2.25.1