From nobody Sat Apr 11 06:29:29 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 582A6C25B06 for ; Mon, 15 Aug 2022 13:13:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242731AbiHONN0 (ORCPT ); Mon, 15 Aug 2022 09:13:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52548 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242703AbiHONNX (ORCPT ); Mon, 15 Aug 2022 09:13:23 -0400 Received: from muru.com (muru.com [72.249.23.125]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id A707D12D3E; Mon, 15 Aug 2022 06:13:22 -0700 (PDT) Received: from hillo.muru.com (localhost [127.0.0.1]) by muru.com (Postfix) with ESMTP id 2CEB381D0; Mon, 15 Aug 2022 13:06:29 +0000 (UTC) From: Tony Lindgren To: Daniel Lezcano , Thomas Gleixner Cc: Aaro Koskinen , Grygorii Strashko , Janusz Krzysztofik , Keerthy , Ladislav Michl , Nishanth Menon , Suman Anna , Vignesh Raghavendra , linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 1/9] clocksource/drivers/timer-ti-dm: Drop unused functions Date: Mon, 15 Aug 2022 16:12:42 +0300 Message-Id: <20220815131250.34603-2-tony@atomide.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220815131250.34603-1-tony@atomide.com> References: <20220815131250.34603-1-tony@atomide.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" We still have some unused functions left, let's drop them. Signed-off-by: Tony Lindgren Reviewed-by: Janusz Krzysztofik --- drivers/clocksource/timer-ti-dm.c | 51 ------------------------------- include/clocksource/timer-ti-dm.h | 7 ----- 2 files changed, 58 deletions(-) diff --git a/drivers/clocksource/timer-ti-dm.c b/drivers/clocksource/timer-= ti-dm.c --- a/drivers/clocksource/timer-ti-dm.c +++ b/drivers/clocksource/timer-ti-dm.c @@ -388,16 +388,6 @@ static inline u32 omap_dm_timer_reserved_systimer(int = id) return (omap_reserved_systimers & (1 << (id - 1))) ? 1 : 0; } =20 -int omap_dm_timer_reserve_systimer(int id) -{ - if (omap_dm_timer_reserved_systimer(id)) - return -ENODEV; - - omap_reserved_systimers |=3D (1 << (id - 1)); - - return 0; -} - static struct omap_dm_timer *_omap_dm_timer_request(int req_type, void *da= ta) { struct omap_dm_timer *timer =3D NULL, *t; @@ -499,20 +489,6 @@ static struct omap_dm_timer *omap_dm_timer_request_spe= cific(int id) return _omap_dm_timer_request(REQUEST_BY_ID, &id); } =20 -/** - * omap_dm_timer_request_by_cap - Request a timer by capability - * @cap: Bit mask of capabilities to match - * - * Find a timer based upon capabilities bit mask. Callers of this function - * should use the definitions found in the plat/dmtimer.h file under the - * comment "timer capabilities used in hwmod database". Returns pointer to - * timer handle on success and a NULL pointer on failure. - */ -struct omap_dm_timer *omap_dm_timer_request_by_cap(u32 cap) -{ - return _omap_dm_timer_request(REQUEST_BY_CAP, &cap); -} - /** * omap_dm_timer_request_by_node - Request a timer by device-tree node * @np: Pointer to device-tree timer node @@ -606,17 +582,6 @@ __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask) =20 #endif =20 -int omap_dm_timer_trigger(struct omap_dm_timer *timer) -{ - if (unlikely(!timer || !atomic_read(&timer->enabled))) { - pr_err("%s: timer not available or enabled.\n", __func__); - return -EINVAL; - } - - omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0); - return 0; -} - static int omap_dm_timer_start(struct omap_dm_timer *timer) { u32 l; @@ -833,22 +798,6 @@ static int omap_dm_timer_write_counter(struct omap_dm_= timer *timer, unsigned int return 0; } =20 -int omap_dm_timers_active(void) -{ - struct omap_dm_timer *timer; - - list_for_each_entry(timer, &omap_timer_list, node) { - if (!timer->reserved) - continue; - - if (omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG) & - OMAP_TIMER_CTRL_ST) { - return 1; - } - } - return 0; -} - static int __maybe_unused omap_dm_timer_runtime_suspend(struct device *dev) { struct omap_dm_timer *timer =3D dev_get_drvdata(dev); diff --git a/include/clocksource/timer-ti-dm.h b/include/clocksource/timer-= ti-dm.h --- a/include/clocksource/timer-ti-dm.h +++ b/include/clocksource/timer-ti-dm.h @@ -119,17 +119,10 @@ struct omap_dm_timer { struct notifier_block nb; }; =20 -int omap_dm_timer_reserve_systimer(int id); -struct omap_dm_timer *omap_dm_timer_request_by_cap(u32 cap); - int omap_dm_timer_get_irq(struct omap_dm_timer *timer); =20 u32 omap_dm_timer_modify_idlect_mask(u32 inputmask); =20 -int omap_dm_timer_trigger(struct omap_dm_timer *timer); - -int omap_dm_timers_active(void); - /* * Do not use the defines below, they are not needed. They should be only * used by dmtimer.c and sys_timer related code. --=20 2.37.1 From nobody Sat Apr 11 06:29:29 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E85D7C00140 for ; Mon, 15 Aug 2022 13:13:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242752AbiHONNd (ORCPT ); Mon, 15 Aug 2022 09:13:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52596 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242733AbiHONN1 (ORCPT ); Mon, 15 Aug 2022 09:13:27 -0400 Received: from muru.com (muru.com [72.249.23.125]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 63EE712D3E; Mon, 15 Aug 2022 06:13:25 -0700 (PDT) Received: from hillo.muru.com (localhost [127.0.0.1]) by muru.com (Postfix) with ESMTP id E19D48218; Mon, 15 Aug 2022 13:06:31 +0000 (UTC) From: Tony Lindgren To: Daniel Lezcano , Thomas Gleixner Cc: Aaro Koskinen , Grygorii Strashko , Janusz Krzysztofik , Keerthy , Ladislav Michl , Nishanth Menon , Suman Anna , Vignesh Raghavendra , linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 2/9] clocksource/drivers/timer-ti-dm: Simplify register reads with dmtimer_read() Date: Mon, 15 Aug 2022 16:12:43 +0300 Message-Id: <20220815131250.34603-3-tony@atomide.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220815131250.34603-1-tony@atomide.com> References: <20220815131250.34603-1-tony@atomide.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" We can simplify register read access by checking for the register write posted mode in the read function. This way we can combine the functions for __omap_dm_timer_read() and omap_dm_timer_read_reg() into a single function dmtimer_read(). We update the shared register access first, the timer revision specific register access will be updated in a later patch. Signed-off-by: Tony Lindgren Reviewed-by: Janusz Krzysztofik --- drivers/clocksource/timer-ti-dm.c | 88 ++++++++++++++----------------- 1 file changed, 40 insertions(+), 48 deletions(-) diff --git a/drivers/clocksource/timer-ti-dm.c b/drivers/clocksource/timer-= ti-dm.c --- a/drivers/clocksource/timer-ti-dm.c +++ b/drivers/clocksource/timer-ti-dm.c @@ -44,14 +44,28 @@ enum { REQUEST_BY_NODE, }; =20 -static inline u32 __omap_dm_timer_read(struct omap_dm_timer *timer, u32 re= g, - int posted) +/** + * dmtimer_read - read timer registers in posted and non-posted mode + * @timer: timer pointer over which read operation to perform + * @reg: lowest byte holds the register offset + * + * The posted mode bit is encoded in reg. Note that in posted mode, write + * pending bit must be checked. Otherwise a read of a non completed write + * will produce an error. + */ +static inline u32 dmtimer_read(struct omap_dm_timer *timer, u32 reg) { - if (posted) - while (readl_relaxed(timer->pend) & (reg >> WPSHIFT)) + u16 wp, offset; + + wp =3D reg >> WPSHIFT; + offset =3D reg & 0xff; + + /* Wait for a possible write pending bit in posted mode */ + if (wp && timer->posted) + while (readl_relaxed(timer->pend) & wp) cpu_relax(); =20 - return readl_relaxed(timer->func_base + (reg & 0xff)); + return readl_relaxed(timer->func_base + offset); } =20 static inline void __omap_dm_timer_write(struct omap_dm_timer *timer, @@ -121,13 +135,13 @@ static inline void __omap_dm_timer_stop(struct omap_d= m_timer *timer, { u32 l; =20 - l =3D __omap_dm_timer_read(timer, OMAP_TIMER_CTRL_REG, posted); + l =3D dmtimer_read(timer, OMAP_TIMER_CTRL_REG); if (l & OMAP_TIMER_CTRL_ST) { l &=3D ~0x1; __omap_dm_timer_write(timer, OMAP_TIMER_CTRL_REG, l, posted); #ifdef CONFIG_ARCH_OMAP2PLUS /* Readback to make sure write has completed */ - __omap_dm_timer_read(timer, OMAP_TIMER_CTRL_REG, posted); + dmtimer_read(timer, OMAP_TIMER_CTRL_REG); /* * Wait for functional clock period x 3.5 to make sure that * timer is stopped @@ -148,9 +162,9 @@ static inline void __omap_dm_timer_int_enable(struct om= ap_dm_timer *timer, } =20 static inline unsigned int -__omap_dm_timer_read_counter(struct omap_dm_timer *timer, int posted) +__omap_dm_timer_read_counter(struct omap_dm_timer *timer) { - return __omap_dm_timer_read(timer, OMAP_TIMER_COUNTER_REG, posted); + return dmtimer_read(timer, OMAP_TIMER_COUNTER_REG); } =20 static inline void __omap_dm_timer_write_status(struct omap_dm_timer *time= r, @@ -159,21 +173,6 @@ static inline void __omap_dm_timer_write_status(struct= omap_dm_timer *timer, writel_relaxed(value, timer->irq_stat); } =20 -/** - * omap_dm_timer_read_reg - read timer registers in posted and non-posted = mode - * @timer: timer pointer over which read operation to perform - * @reg: lowest byte holds the register offset - * - * The posted mode bit is encoded in reg. Note that in posted mode write - * pending bit must be checked. Otherwise a read of a non completed write - * will produce an error. - */ -static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, u32 = reg) -{ - WARN_ON((reg & 0xff) < _OMAP_TIMER_WAKEUP_EN_OFFSET); - return __omap_dm_timer_read(timer, reg, timer->posted); -} - /** * omap_dm_timer_write_reg - write timer registers in posted and non-poste= d mode * @timer: timer pointer over which write operation is to perform @@ -213,20 +212,14 @@ static void omap_timer_restore_context(struct omap_dm= _timer *timer) =20 static void omap_timer_save_context(struct omap_dm_timer *timer) { - timer->context.ocp_cfg =3D - __omap_dm_timer_read(timer, OMAP_TIMER_OCP_CFG_OFFSET, 0); - - timer->context.tclr =3D - omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); - timer->context.twer =3D - omap_dm_timer_read_reg(timer, OMAP_TIMER_WAKEUP_EN_REG); - timer->context.tldr =3D - omap_dm_timer_read_reg(timer, OMAP_TIMER_LOAD_REG); - timer->context.tmar =3D - omap_dm_timer_read_reg(timer, OMAP_TIMER_MATCH_REG); + timer->context.ocp_cfg =3D dmtimer_read(timer, OMAP_TIMER_OCP_CFG_OFFSET); + + timer->context.tclr =3D dmtimer_read(timer, OMAP_TIMER_CTRL_REG); + timer->context.twer =3D dmtimer_read(timer, OMAP_TIMER_WAKEUP_EN_REG); + timer->context.tldr =3D dmtimer_read(timer, OMAP_TIMER_LOAD_REG); + timer->context.tmar =3D dmtimer_read(timer, OMAP_TIMER_MATCH_REG); timer->context.tier =3D readl_relaxed(timer->irq_ena); - timer->context.tsicr =3D - omap_dm_timer_read_reg(timer, OMAP_TIMER_IF_CTRL_REG); + timer->context.tsicr =3D dmtimer_read(timer, OMAP_TIMER_IF_CTRL_REG); } =20 static int omap_timer_context_notifier(struct notifier_block *nb, @@ -266,8 +259,7 @@ static int omap_dm_timer_reset(struct omap_dm_timer *ti= mer) omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06); =20 do { - l =3D __omap_dm_timer_read(timer, - OMAP_TIMER_V1_SYS_STAT_OFFSET, 0); + l =3D dmtimer_read(timer, OMAP_TIMER_V1_SYS_STAT_OFFSET); } while (!l && timeout--); =20 if (!timeout) { @@ -276,7 +268,7 @@ static int omap_dm_timer_reset(struct omap_dm_timer *ti= mer) } =20 /* Configure timer for smart-idle mode */ - l =3D __omap_dm_timer_read(timer, OMAP_TIMER_OCP_CFG_OFFSET, 0); + l =3D dmtimer_read(timer, OMAP_TIMER_OCP_CFG_OFFSET); l |=3D 0x2 << 0x3; __omap_dm_timer_write(timer, OMAP_TIMER_OCP_CFG_OFFSET, l, 0); =20 @@ -550,7 +542,7 @@ __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask) list_for_each_entry(timer, &omap_timer_list, node) { u32 l; =20 - l =3D omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); + l =3D dmtimer_read(timer, OMAP_TIMER_CTRL_REG); if (l & OMAP_TIMER_CTRL_ST) { if (((omap_readl(MOD_CONF_CTRL_1) >> (i * 2)) & 0x03) =3D=3D 0) inputmask &=3D ~(1 << 1); @@ -591,7 +583,7 @@ static int omap_dm_timer_start(struct omap_dm_timer *ti= mer) =20 omap_dm_timer_enable(timer); =20 - l =3D omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); + l =3D dmtimer_read(timer, OMAP_TIMER_CTRL_REG); if (!(l & OMAP_TIMER_CTRL_ST)) { l |=3D OMAP_TIMER_CTRL_ST; omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); @@ -638,7 +630,7 @@ static int omap_dm_timer_set_match(struct omap_dm_timer= *timer, int enable, return -EINVAL; =20 omap_dm_timer_enable(timer); - l =3D omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); + l =3D dmtimer_read(timer, OMAP_TIMER_CTRL_REG); if (enable) l |=3D OMAP_TIMER_CTRL_CE; else @@ -659,7 +651,7 @@ static int omap_dm_timer_set_pwm(struct omap_dm_timer *= timer, int def_on, return -EINVAL; =20 omap_dm_timer_enable(timer); - l =3D omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); + l =3D dmtimer_read(timer, OMAP_TIMER_CTRL_REG); l &=3D ~(OMAP_TIMER_CTRL_GPOCFG | OMAP_TIMER_CTRL_SCPWM | OMAP_TIMER_CTRL_PT | (0x03 << 10) | OMAP_TIMER_CTRL_AR); if (def_on) @@ -683,7 +675,7 @@ static int omap_dm_timer_get_pwm_status(struct omap_dm_= timer *timer) return -EINVAL; =20 omap_dm_timer_enable(timer); - l =3D omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); + l =3D dmtimer_read(timer, OMAP_TIMER_CTRL_REG); omap_dm_timer_disable(timer); =20 return l; @@ -698,7 +690,7 @@ static int omap_dm_timer_set_prescaler(struct omap_dm_t= imer *timer, return -EINVAL; =20 omap_dm_timer_enable(timer); - l =3D omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); + l =3D dmtimer_read(timer, OMAP_TIMER_CTRL_REG); l &=3D ~(OMAP_TIMER_CTRL_PRE | (0x07 << 2)); if (prescaler >=3D 0) { l |=3D OMAP_TIMER_CTRL_PRE; @@ -743,7 +735,7 @@ static int omap_dm_timer_set_int_disable(struct omap_dm= _timer *timer, u32 mask) l =3D readl_relaxed(timer->irq_ena) & ~mask; =20 writel_relaxed(l, timer->irq_dis); - l =3D omap_dm_timer_read_reg(timer, OMAP_TIMER_WAKEUP_EN_REG) & ~mask; + l =3D dmtimer_read(timer, OMAP_TIMER_WAKEUP_EN_REG) & ~mask; omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG, l); =20 omap_dm_timer_disable(timer); @@ -781,7 +773,7 @@ static unsigned int omap_dm_timer_read_counter(struct o= map_dm_timer *timer) return 0; } =20 - return __omap_dm_timer_read_counter(timer, timer->posted); + return __omap_dm_timer_read_counter(timer); } =20 static int omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsign= ed int value) --=20 2.37.1 From nobody Sat Apr 11 06:29:29 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 02757C282E7 for ; Mon, 15 Aug 2022 13:13:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242762AbiHONNk (ORCPT ); Mon, 15 Aug 2022 09:13:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52820 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242755AbiHONNg (ORCPT ); Mon, 15 Aug 2022 09:13:36 -0400 Received: from muru.com (muru.com [72.249.23.125]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 28E1217057; Mon, 15 Aug 2022 06:13:28 -0700 (PDT) Received: from hillo.muru.com (localhost [127.0.0.1]) by muru.com (Postfix) with ESMTP id A4DC88225; Mon, 15 Aug 2022 13:06:34 +0000 (UTC) From: Tony Lindgren To: Daniel Lezcano , Thomas Gleixner Cc: Aaro Koskinen , Grygorii Strashko , Janusz Krzysztofik , Keerthy , Ladislav Michl , Nishanth Menon , Suman Anna , Vignesh Raghavendra , linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 3/9] clocksource/drivers/timer-ti-dm: Simplify register writes with dmtimer_write() Date: Mon, 15 Aug 2022 16:12:44 +0300 Message-Id: <20220815131250.34603-4-tony@atomide.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220815131250.34603-1-tony@atomide.com> References: <20220815131250.34603-1-tony@atomide.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" We can simplify register write access by checking for the register write posted mode in the write function. This way we can combine the functions for __omap_dm_timer_write() and omap_dm_timer_write_reg() into a single function dmtimer_write(). We update the shared register access first, the timer revision specific register access will be updated in a later patch. Signed-off-by: Tony Lindgren Reviewed-by: Janusz Krzysztofik --- drivers/clocksource/timer-ti-dm.c | 98 ++++++++++++++----------------- 1 file changed, 44 insertions(+), 54 deletions(-) diff --git a/drivers/clocksource/timer-ti-dm.c b/drivers/clocksource/timer-= ti-dm.c --- a/drivers/clocksource/timer-ti-dm.c +++ b/drivers/clocksource/timer-ti-dm.c @@ -68,14 +68,29 @@ static inline u32 dmtimer_read(struct omap_dm_timer *ti= mer, u32 reg) return readl_relaxed(timer->func_base + offset); } =20 -static inline void __omap_dm_timer_write(struct omap_dm_timer *timer, - u32 reg, u32 val, int posted) +/** + * dmtimer_write - write timer registers in posted and non-posted mode + * @timer: timer pointer over which write operation is to perform + * @reg: lowest byte holds the register offset + * @value: data to write into the register + * + * The posted mode bit is encoded in reg. Note that in posted mode, the wr= ite + * pending bit must be checked. Otherwise a write on a register which has a + * pending write will be lost. + */ +static inline void dmtimer_write(struct omap_dm_timer *timer, u32 reg, u32= val) { - if (posted) - while (readl_relaxed(timer->pend) & (reg >> WPSHIFT)) + u16 wp, offset; + + wp =3D reg >> WPSHIFT; + offset =3D reg & 0xff; + + /* Wait for a possible write pending bit in posted mode */ + if (wp && timer->posted) + while (readl_relaxed(timer->pend) & wp) cpu_relax(); =20 - writel_relaxed(val, timer->func_base + (reg & 0xff)); + writel_relaxed(val, timer->func_base + offset); } =20 static inline void __omap_dm_timer_init_regs(struct omap_dm_timer *timer) @@ -120,25 +135,24 @@ static inline void __omap_dm_timer_enable_posted(stru= ct omap_dm_timer *timer) =20 if (timer->errata & OMAP_TIMER_ERRATA_I103_I767) { timer->posted =3D OMAP_TIMER_NONPOSTED; - __omap_dm_timer_write(timer, OMAP_TIMER_IF_CTRL_REG, 0, 0); + dmtimer_write(timer, OMAP_TIMER_IF_CTRL_REG, 0); return; } =20 - __omap_dm_timer_write(timer, OMAP_TIMER_IF_CTRL_REG, - OMAP_TIMER_CTRL_POSTED, 0); + dmtimer_write(timer, OMAP_TIMER_IF_CTRL_REG, OMAP_TIMER_CTRL_POSTED); timer->context.tsicr =3D OMAP_TIMER_CTRL_POSTED; timer->posted =3D OMAP_TIMER_POSTED; } =20 static inline void __omap_dm_timer_stop(struct omap_dm_timer *timer, - int posted, unsigned long rate) + unsigned long rate) { u32 l; =20 l =3D dmtimer_read(timer, OMAP_TIMER_CTRL_REG); if (l & OMAP_TIMER_CTRL_ST) { l &=3D ~0x1; - __omap_dm_timer_write(timer, OMAP_TIMER_CTRL_REG, l, posted); + dmtimer_write(timer, OMAP_TIMER_CTRL_REG, l); #ifdef CONFIG_ARCH_OMAP2PLUS /* Readback to make sure write has completed */ dmtimer_read(timer, OMAP_TIMER_CTRL_REG); @@ -158,7 +172,7 @@ static inline void __omap_dm_timer_int_enable(struct om= ap_dm_timer *timer, unsigned int value) { writel_relaxed(value, timer->irq_ena); - __omap_dm_timer_write(timer, OMAP_TIMER_WAKEUP_EN_REG, value, 0); + dmtimer_write(timer, OMAP_TIMER_WAKEUP_EN_REG, value); } =20 static inline unsigned int @@ -173,41 +187,17 @@ static inline void __omap_dm_timer_write_status(struc= t omap_dm_timer *timer, writel_relaxed(value, timer->irq_stat); } =20 -/** - * omap_dm_timer_write_reg - write timer registers in posted and non-poste= d mode - * @timer: timer pointer over which write operation is to perform - * @reg: lowest byte holds the register offset - * @value: data to write into the register - * - * The posted mode bit is encoded in reg. Note that in posted mode the wri= te - * pending bit must be checked. Otherwise a write on a register which has a - * pending write will be lost. - */ -static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, u32 reg, - u32 value) -{ - WARN_ON((reg & 0xff) < _OMAP_TIMER_WAKEUP_EN_OFFSET); - __omap_dm_timer_write(timer, reg, value, timer->posted); -} - static void omap_timer_restore_context(struct omap_dm_timer *timer) { - __omap_dm_timer_write(timer, OMAP_TIMER_OCP_CFG_OFFSET, - timer->context.ocp_cfg, 0); - - omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG, - timer->context.twer); - omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, - timer->context.tcrr); - omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, - timer->context.tldr); - omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG, - timer->context.tmar); - omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, - timer->context.tsicr); + dmtimer_write(timer, OMAP_TIMER_OCP_CFG_OFFSET, timer->context.ocp_cfg); + + dmtimer_write(timer, OMAP_TIMER_WAKEUP_EN_REG, timer->context.twer); + dmtimer_write(timer, OMAP_TIMER_COUNTER_REG, timer->context.tcrr); + dmtimer_write(timer, OMAP_TIMER_LOAD_REG, timer->context.tldr); + dmtimer_write(timer, OMAP_TIMER_MATCH_REG, timer->context.tmar); + dmtimer_write(timer, OMAP_TIMER_IF_CTRL_REG, timer->context.tsicr); writel_relaxed(timer->context.tier, timer->irq_ena); - omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, - timer->context.tclr); + dmtimer_write(timer, OMAP_TIMER_CTRL_REG, timer->context.tclr); } =20 static void omap_timer_save_context(struct omap_dm_timer *timer) @@ -256,7 +246,7 @@ static int omap_dm_timer_reset(struct omap_dm_timer *ti= mer) if (timer->revision !=3D 1) return -EINVAL; =20 - omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06); + dmtimer_write(timer, OMAP_TIMER_IF_CTRL_REG, 0x06); =20 do { l =3D dmtimer_read(timer, OMAP_TIMER_V1_SYS_STAT_OFFSET); @@ -270,7 +260,7 @@ static int omap_dm_timer_reset(struct omap_dm_timer *ti= mer) /* Configure timer for smart-idle mode */ l =3D dmtimer_read(timer, OMAP_TIMER_OCP_CFG_OFFSET); l |=3D 0x2 << 0x3; - __omap_dm_timer_write(timer, OMAP_TIMER_OCP_CFG_OFFSET, l, 0); + dmtimer_write(timer, OMAP_TIMER_OCP_CFG_OFFSET, l); =20 timer->posted =3D 0; =20 @@ -586,7 +576,7 @@ static int omap_dm_timer_start(struct omap_dm_timer *ti= mer) l =3D dmtimer_read(timer, OMAP_TIMER_CTRL_REG); if (!(l & OMAP_TIMER_CTRL_ST)) { l |=3D OMAP_TIMER_CTRL_ST; - omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); + dmtimer_write(timer, OMAP_TIMER_CTRL_REG, l); } =20 return 0; @@ -602,7 +592,7 @@ static int omap_dm_timer_stop(struct omap_dm_timer *tim= er) if (!(timer->capability & OMAP_TIMER_NEEDS_RESET)) rate =3D clk_get_rate(timer->fclk); =20 - __omap_dm_timer_stop(timer, timer->posted, rate); + __omap_dm_timer_stop(timer, rate); =20 omap_dm_timer_disable(timer); return 0; @@ -615,7 +605,7 @@ static int omap_dm_timer_set_load(struct omap_dm_timer = *timer, return -EINVAL; =20 omap_dm_timer_enable(timer); - omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load); + dmtimer_write(timer, OMAP_TIMER_LOAD_REG, load); =20 omap_dm_timer_disable(timer); return 0; @@ -635,8 +625,8 @@ static int omap_dm_timer_set_match(struct omap_dm_timer= *timer, int enable, l |=3D OMAP_TIMER_CTRL_CE; else l &=3D ~OMAP_TIMER_CTRL_CE; - omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG, match); - omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); + dmtimer_write(timer, OMAP_TIMER_MATCH_REG, match); + dmtimer_write(timer, OMAP_TIMER_CTRL_REG, l); =20 omap_dm_timer_disable(timer); return 0; @@ -661,7 +651,7 @@ static int omap_dm_timer_set_pwm(struct omap_dm_timer *= timer, int def_on, l |=3D trigger << 10; if (autoreload) l |=3D OMAP_TIMER_CTRL_AR; - omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); + dmtimer_write(timer, OMAP_TIMER_CTRL_REG, l); =20 omap_dm_timer_disable(timer); return 0; @@ -696,7 +686,7 @@ static int omap_dm_timer_set_prescaler(struct omap_dm_t= imer *timer, l |=3D OMAP_TIMER_CTRL_PRE; l |=3D prescaler << 2; } - omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); + dmtimer_write(timer, OMAP_TIMER_CTRL_REG, l); =20 omap_dm_timer_disable(timer); return 0; @@ -736,7 +726,7 @@ static int omap_dm_timer_set_int_disable(struct omap_dm= _timer *timer, u32 mask) =20 writel_relaxed(l, timer->irq_dis); l =3D dmtimer_read(timer, OMAP_TIMER_WAKEUP_EN_REG) & ~mask; - omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG, l); + dmtimer_write(timer, OMAP_TIMER_WAKEUP_EN_REG, l); =20 omap_dm_timer_disable(timer); return 0; @@ -783,7 +773,7 @@ static int omap_dm_timer_write_counter(struct omap_dm_t= imer *timer, unsigned int return -EINVAL; } =20 - omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, value); + dmtimer_write(timer, OMAP_TIMER_COUNTER_REG, value); =20 /* Save the context */ timer->context.tcrr =3D value; --=20 2.37.1 From nobody Sat Apr 11 06:29:29 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6354FC00140 for ; Mon, 15 Aug 2022 13:13:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242772AbiHONNn (ORCPT ); Mon, 15 Aug 2022 09:13:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52856 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242760AbiHONNh (ORCPT ); Mon, 15 Aug 2022 09:13:37 -0400 Received: from muru.com (muru.com [72.249.23.125]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id DA8B91901E; Mon, 15 Aug 2022 06:13:30 -0700 (PDT) Received: from hillo.muru.com (localhost [127.0.0.1]) by muru.com (Postfix) with ESMTP id 672F180FB; Mon, 15 Aug 2022 13:06:37 +0000 (UTC) From: Tony Lindgren To: Daniel Lezcano , Thomas Gleixner Cc: Aaro Koskinen , Grygorii Strashko , Janusz Krzysztofik , Keerthy , Ladislav Michl , Nishanth Menon , Suman Anna , Vignesh Raghavendra , linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 4/9] clocksource/drivers/timer-ti-dm: Simplify register access further Date: Mon, 15 Aug 2022 16:12:45 +0300 Message-Id: <20220815131250.34603-5-tony@atomide.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220815131250.34603-1-tony@atomide.com> References: <20220815131250.34603-1-tony@atomide.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Let's unify register access and use dmtimer_read() and dmtimer_write() also for the timer revision specific registers like we now do for the shread registers. Signed-off-by: Tony Lindgren Reviewed-by: Janusz Krzysztofik --- drivers/clocksource/timer-ti-dm.c | 28 ++++++++++++++-------------- include/clocksource/timer-ti-dm.h | 6 +++--- 2 files changed, 17 insertions(+), 17 deletions(-) diff --git a/drivers/clocksource/timer-ti-dm.c b/drivers/clocksource/timer-= ti-dm.c --- a/drivers/clocksource/timer-ti-dm.c +++ b/drivers/clocksource/timer-ti-dm.c @@ -101,16 +101,16 @@ static inline void __omap_dm_timer_init_regs(struct o= map_dm_timer *timer) tidr =3D readl_relaxed(timer->io_base); if (!(tidr >> 16)) { timer->revision =3D 1; - timer->irq_stat =3D timer->io_base + OMAP_TIMER_V1_STAT_OFFSET; - timer->irq_ena =3D timer->io_base + OMAP_TIMER_V1_INT_EN_OFFSET; - timer->irq_dis =3D timer->io_base + OMAP_TIMER_V1_INT_EN_OFFSET; + timer->irq_stat =3D OMAP_TIMER_V1_STAT_OFFSET; + timer->irq_ena =3D OMAP_TIMER_V1_INT_EN_OFFSET; + timer->irq_dis =3D OMAP_TIMER_V1_INT_EN_OFFSET; timer->pend =3D timer->io_base + _OMAP_TIMER_WRITE_PEND_OFFSET; timer->func_base =3D timer->io_base; } else { timer->revision =3D 2; - timer->irq_stat =3D timer->io_base + OMAP_TIMER_V2_IRQSTATUS; - timer->irq_ena =3D timer->io_base + OMAP_TIMER_V2_IRQENABLE_SET; - timer->irq_dis =3D timer->io_base + OMAP_TIMER_V2_IRQENABLE_CLR; + timer->irq_stat =3D OMAP_TIMER_V2_IRQSTATUS - OMAP_TIMER_V2_FUNC_OFFSET; + timer->irq_ena =3D OMAP_TIMER_V2_IRQENABLE_SET - OMAP_TIMER_V2_FUNC_OFFS= ET; + timer->irq_dis =3D OMAP_TIMER_V2_IRQENABLE_CLR - OMAP_TIMER_V2_FUNC_OFFS= ET; timer->pend =3D timer->io_base + _OMAP_TIMER_WRITE_PEND_OFFSET + OMAP_TIMER_V2_FUNC_OFFSET; @@ -165,13 +165,13 @@ static inline void __omap_dm_timer_stop(struct omap_d= m_timer *timer, } =20 /* Ack possibly pending interrupt */ - writel_relaxed(OMAP_TIMER_INT_OVERFLOW, timer->irq_stat); + dmtimer_write(timer, timer->irq_stat, OMAP_TIMER_INT_OVERFLOW); } =20 static inline void __omap_dm_timer_int_enable(struct omap_dm_timer *timer, unsigned int value) { - writel_relaxed(value, timer->irq_ena); + dmtimer_write(timer, timer->irq_ena, value); dmtimer_write(timer, OMAP_TIMER_WAKEUP_EN_REG, value); } =20 @@ -184,7 +184,7 @@ __omap_dm_timer_read_counter(struct omap_dm_timer *time= r) static inline void __omap_dm_timer_write_status(struct omap_dm_timer *time= r, unsigned int value) { - writel_relaxed(value, timer->irq_stat); + dmtimer_write(timer, timer->irq_stat, value); } =20 static void omap_timer_restore_context(struct omap_dm_timer *timer) @@ -196,7 +196,7 @@ static void omap_timer_restore_context(struct omap_dm_t= imer *timer) dmtimer_write(timer, OMAP_TIMER_LOAD_REG, timer->context.tldr); dmtimer_write(timer, OMAP_TIMER_MATCH_REG, timer->context.tmar); dmtimer_write(timer, OMAP_TIMER_IF_CTRL_REG, timer->context.tsicr); - writel_relaxed(timer->context.tier, timer->irq_ena); + dmtimer_write(timer, timer->irq_ena, timer->context.tier); dmtimer_write(timer, OMAP_TIMER_CTRL_REG, timer->context.tclr); } =20 @@ -208,7 +208,7 @@ static void omap_timer_save_context(struct omap_dm_time= r *timer) timer->context.twer =3D dmtimer_read(timer, OMAP_TIMER_WAKEUP_EN_REG); timer->context.tldr =3D dmtimer_read(timer, OMAP_TIMER_LOAD_REG); timer->context.tmar =3D dmtimer_read(timer, OMAP_TIMER_MATCH_REG); - timer->context.tier =3D readl_relaxed(timer->irq_ena); + timer->context.tier =3D dmtimer_read(timer, timer->irq_ena); timer->context.tsicr =3D dmtimer_read(timer, OMAP_TIMER_IF_CTRL_REG); } =20 @@ -722,9 +722,9 @@ static int omap_dm_timer_set_int_disable(struct omap_dm= _timer *timer, u32 mask) omap_dm_timer_enable(timer); =20 if (timer->revision =3D=3D 1) - l =3D readl_relaxed(timer->irq_ena) & ~mask; + l =3D dmtimer_read(timer, timer->irq_ena) & ~mask; =20 - writel_relaxed(l, timer->irq_dis); + dmtimer_write(timer, timer->irq_dis, l); l =3D dmtimer_read(timer, OMAP_TIMER_WAKEUP_EN_REG) & ~mask; dmtimer_write(timer, OMAP_TIMER_WAKEUP_EN_REG, l); =20 @@ -741,7 +741,7 @@ static unsigned int omap_dm_timer_read_status(struct om= ap_dm_timer *timer) return 0; } =20 - l =3D readl_relaxed(timer->irq_stat); + l =3D dmtimer_read(timer, timer->irq_stat); =20 return l; } diff --git a/include/clocksource/timer-ti-dm.h b/include/clocksource/timer-= ti-dm.h --- a/include/clocksource/timer-ti-dm.h +++ b/include/clocksource/timer-ti-dm.h @@ -100,9 +100,9 @@ struct omap_dm_timer { struct clk *fclk; =20 void __iomem *io_base; - void __iomem *irq_stat; /* TISR/IRQSTATUS interrupt status */ - void __iomem *irq_ena; /* irq enable */ - void __iomem *irq_dis; /* irq disable, only on v2 ip */ + int irq_stat; /* TISR/IRQSTATUS interrupt status */ + int irq_ena; /* irq enable */ + int irq_dis; /* irq disable, only on v2 ip */ void __iomem *pend; /* write pending */ void __iomem *func_base; /* function register base */ =20 --=20 2.37.1 From nobody Sat Apr 11 06:29:29 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C053CC25B06 for ; Mon, 15 Aug 2022 13:13:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242787AbiHONNz (ORCPT ); Mon, 15 Aug 2022 09:13:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52986 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242769AbiHONNm (ORCPT ); Mon, 15 Aug 2022 09:13:42 -0400 Received: from muru.com (muru.com [72.249.23.125]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 60AB01AF1D; Mon, 15 Aug 2022 06:13:33 -0700 (PDT) Received: from hillo.muru.com (localhost [127.0.0.1]) by muru.com (Postfix) with ESMTP id 032098231; Mon, 15 Aug 2022 13:06:39 +0000 (UTC) From: Tony Lindgren To: Daniel Lezcano , Thomas Gleixner Cc: Aaro Koskinen , Grygorii Strashko , Janusz Krzysztofik , Keerthy , Ladislav Michl , Nishanth Menon , Suman Anna , Vignesh Raghavendra , linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 5/9] clocksource/drivers/timer-ti-dm: Move private defines to the driver Date: Mon, 15 Aug 2022 16:12:46 +0300 Message-Id: <20220815131250.34603-6-tony@atomide.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220815131250.34603-1-tony@atomide.com> References: <20220815131250.34603-1-tony@atomide.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" These defines are only used by timer-ti-dm driver. Signed-off-by: Tony Lindgren Reviewed-by: Janusz Krzysztofik --- drivers/clocksource/timer-ti-dm.c | 62 +++++++++++++++++++++++++++++++ include/clocksource/timer-ti-dm.h | 62 ------------------------------- 2 files changed, 62 insertions(+), 62 deletions(-) diff --git a/drivers/clocksource/timer-ti-dm.c b/drivers/clocksource/timer-= ti-dm.c --- a/drivers/clocksource/timer-ti-dm.c +++ b/drivers/clocksource/timer-ti-dm.c @@ -33,6 +33,68 @@ =20 #include =20 +/* + * timer errata flags + * + * Errata i103/i767 impacts all OMAP3/4/5 devices including AM33xx. This + * errata prevents us from using posted mode on these devices, unless the + * timer counter register is never read. For more details please refer to + * the OMAP3/4/5 errata documents. + */ +#define OMAP_TIMER_ERRATA_I103_I767 0x80000000 + +/* posted mode types */ +#define OMAP_TIMER_NONPOSTED 0x00 +#define OMAP_TIMER_POSTED 0x01 + +/* register offsets with the write pending bit encoded */ +#define WPSHIFT 16 + +#define OMAP_TIMER_WAKEUP_EN_REG (_OMAP_TIMER_WAKEUP_EN_OFFSET \ + | (WP_NONE << WPSHIFT)) + +#define OMAP_TIMER_CTRL_REG (_OMAP_TIMER_CTRL_OFFSET \ + | (WP_TCLR << WPSHIFT)) + +#define OMAP_TIMER_COUNTER_REG (_OMAP_TIMER_COUNTER_OFFSET \ + | (WP_TCRR << WPSHIFT)) + +#define OMAP_TIMER_LOAD_REG (_OMAP_TIMER_LOAD_OFFSET \ + | (WP_TLDR << WPSHIFT)) + +#define OMAP_TIMER_TRIGGER_REG (_OMAP_TIMER_TRIGGER_OFFSET \ + | (WP_TTGR << WPSHIFT)) + +#define OMAP_TIMER_WRITE_PEND_REG (_OMAP_TIMER_WRITE_PEND_OFFSET \ + | (WP_NONE << WPSHIFT)) + +#define OMAP_TIMER_MATCH_REG (_OMAP_TIMER_MATCH_OFFSET \ + | (WP_TMAR << WPSHIFT)) + +#define OMAP_TIMER_CAPTURE_REG (_OMAP_TIMER_CAPTURE_OFFSET \ + | (WP_NONE << WPSHIFT)) + +#define OMAP_TIMER_IF_CTRL_REG (_OMAP_TIMER_IF_CTRL_OFFSET \ + | (WP_NONE << WPSHIFT)) + +#define OMAP_TIMER_CAPTURE2_REG (_OMAP_TIMER_CAPTURE2_OFFSET \ + | (WP_NONE << WPSHIFT)) + +#define OMAP_TIMER_TICK_POS_REG (_OMAP_TIMER_TICK_POS_OFFSET \ + | (WP_TPIR << WPSHIFT)) + +#define OMAP_TIMER_TICK_NEG_REG (_OMAP_TIMER_TICK_NEG_OFFSET \ + | (WP_TNIR << WPSHIFT)) + +#define OMAP_TIMER_TICK_COUNT_REG (_OMAP_TIMER_TICK_COUNT_OFFSET \ + | (WP_TCVR << WPSHIFT)) + +#define OMAP_TIMER_TICK_INT_MASK_SET_REG \ + (_OMAP_TIMER_TICK_INT_MASK_SET_OFFSET | (WP_TOCR << WPSHIFT)) + +#define OMAP_TIMER_TICK_INT_MASK_COUNT_REG \ + (_OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET | (WP_TOWR << WPSHIFT)) + static u32 omap_reserved_systimers; static LIST_HEAD(omap_timer_list); static DEFINE_SPINLOCK(dm_timer_lock); diff --git a/include/clocksource/timer-ti-dm.h b/include/clocksource/timer-= ti-dm.h --- a/include/clocksource/timer-ti-dm.h +++ b/include/clocksource/timer-ti-dm.h @@ -52,10 +52,6 @@ #define OMAP_TIMER_TRIGGER_OVERFLOW 0x01 #define OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE 0x02 =20 -/* posted mode types */ -#define OMAP_TIMER_NONPOSTED 0x00 -#define OMAP_TIMER_POSTED 0x01 - /* timer capabilities used in hwmod database */ #define OMAP_TIMER_SECURE 0x80000000 #define OMAP_TIMER_ALWON 0x40000000 @@ -63,16 +59,6 @@ #define OMAP_TIMER_NEEDS_RESET 0x10000000 #define OMAP_TIMER_HAS_DSP_IRQ 0x08000000 =20 -/* - * timer errata flags - * - * Errata i103/i767 impacts all OMAP3/4/5 devices including AM33xx. This - * errata prevents us from using posted mode on these devices, unless the - * timer counter register is never read. For more details please refer to - * the OMAP3/4/5 errata documents. - */ -#define OMAP_TIMER_ERRATA_I103_I767 0x80000000 - struct timer_regs { u32 ocp_cfg; u32 tidr; @@ -192,52 +178,4 @@ u32 omap_dm_timer_modify_idlect_mask(u32 inputmask); #define _OMAP_TIMER_TICK_INT_MASK_SET_OFFSET 0x54 /* TOCR, 34xx only */ #define _OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET 0x58 /* TOWR, 34xx only */ =20 -/* register offsets with the write pending bit encoded */ -#define WPSHIFT 16 - -#define OMAP_TIMER_WAKEUP_EN_REG (_OMAP_TIMER_WAKEUP_EN_OFFSET \ - | (WP_NONE << WPSHIFT)) - -#define OMAP_TIMER_CTRL_REG (_OMAP_TIMER_CTRL_OFFSET \ - | (WP_TCLR << WPSHIFT)) - -#define OMAP_TIMER_COUNTER_REG (_OMAP_TIMER_COUNTER_OFFSET \ - | (WP_TCRR << WPSHIFT)) - -#define OMAP_TIMER_LOAD_REG (_OMAP_TIMER_LOAD_OFFSET \ - | (WP_TLDR << WPSHIFT)) - -#define OMAP_TIMER_TRIGGER_REG (_OMAP_TIMER_TRIGGER_OFFSET \ - | (WP_TTGR << WPSHIFT)) - -#define OMAP_TIMER_WRITE_PEND_REG (_OMAP_TIMER_WRITE_PEND_OFFSET \ - | (WP_NONE << WPSHIFT)) - -#define OMAP_TIMER_MATCH_REG (_OMAP_TIMER_MATCH_OFFSET \ - | (WP_TMAR << WPSHIFT)) - -#define OMAP_TIMER_CAPTURE_REG (_OMAP_TIMER_CAPTURE_OFFSET \ - | (WP_NONE << WPSHIFT)) - -#define OMAP_TIMER_IF_CTRL_REG (_OMAP_TIMER_IF_CTRL_OFFSET \ - | (WP_NONE << WPSHIFT)) - -#define OMAP_TIMER_CAPTURE2_REG (_OMAP_TIMER_CAPTURE2_OFFSET \ - | (WP_NONE << WPSHIFT)) - -#define OMAP_TIMER_TICK_POS_REG (_OMAP_TIMER_TICK_POS_OFFSET \ - | (WP_TPIR << WPSHIFT)) - -#define OMAP_TIMER_TICK_NEG_REG (_OMAP_TIMER_TICK_NEG_OFFSET \ - | (WP_TNIR << WPSHIFT)) - -#define OMAP_TIMER_TICK_COUNT_REG (_OMAP_TIMER_TICK_COUNT_OFFSET \ - | (WP_TCVR << WPSHIFT)) - -#define OMAP_TIMER_TICK_INT_MASK_SET_REG \ - (_OMAP_TIMER_TICK_INT_MASK_SET_OFFSET | (WP_TOCR << WPSHIFT)) - -#define OMAP_TIMER_TICK_INT_MASK_COUNT_REG \ - (_OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET | (WP_TOWR << WPSHIFT)) - #endif /* __CLOCKSOURCE_DMTIMER_H */ --=20 2.37.1 From nobody Sat Apr 11 06:29:29 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2DA07C00140 for ; Mon, 15 Aug 2022 13:14:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242814AbiHONOA (ORCPT ); Mon, 15 Aug 2022 09:14:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53202 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242802AbiHONNw (ORCPT ); Mon, 15 Aug 2022 09:13:52 -0400 Received: from muru.com (muru.com [72.249.23.125]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 21CD91C10D; Mon, 15 Aug 2022 06:13:36 -0700 (PDT) Received: from hillo.muru.com (localhost [127.0.0.1]) by muru.com (Postfix) with ESMTP id 9580181D0; Mon, 15 Aug 2022 13:06:42 +0000 (UTC) From: Tony Lindgren To: Daniel Lezcano , Thomas Gleixner Cc: Aaro Koskinen , Grygorii Strashko , Janusz Krzysztofik , Keerthy , Ladislav Michl , Nishanth Menon , Suman Anna , Vignesh Raghavendra , linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 6/9] clocksource/drivers/timer-ti-dm: Use runtime PM directly and check errors Date: Mon, 15 Aug 2022 16:12:47 +0300 Message-Id: <20220815131250.34603-7-tony@atomide.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220815131250.34603-1-tony@atomide.com> References: <20220815131250.34603-1-tony@atomide.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Use pm_runtime_resume_and_get() and check for a possible error returned. We want to do this as omap_dm_timer_enable() and omap_dm_timer_disable() are exposed to the pwm and remoteproc drivers, and in the following patch we turn struct omap_dm_timer into a cookie used by the exposed functions only. Signed-off-by: Tony Lindgren Reviewed-by: Janusz Krzysztofik --- drivers/clocksource/timer-ti-dm.c | 117 +++++++++++++++++++++++------- 1 file changed, 91 insertions(+), 26 deletions(-) diff --git a/drivers/clocksource/timer-ti-dm.c b/drivers/clocksource/timer-= ti-dm.c --- a/drivers/clocksource/timer-ti-dm.c +++ b/drivers/clocksource/timer-ti-dm.c @@ -387,16 +387,24 @@ static int omap_dm_timer_set_source(struct omap_dm_ti= mer *timer, int source) =20 static void omap_dm_timer_enable(struct omap_dm_timer *timer) { - pm_runtime_get_sync(&timer->pdev->dev); + struct device *dev =3D &timer->pdev->dev; + int rc; + + rc =3D pm_runtime_resume_and_get(dev); + if (rc) + dev_err(dev, "could not enable timer\n"); } =20 static void omap_dm_timer_disable(struct omap_dm_timer *timer) { - pm_runtime_put_sync(&timer->pdev->dev); + struct device *dev =3D &timer->pdev->dev; + + pm_runtime_put_sync(dev); } =20 static int omap_dm_timer_prepare(struct omap_dm_timer *timer) { + struct device *dev =3D &timer->pdev->dev; int rc; =20 /* @@ -411,18 +419,20 @@ static int omap_dm_timer_prepare(struct omap_dm_timer= *timer) } } =20 - omap_dm_timer_enable(timer); + rc =3D pm_runtime_resume_and_get(dev); + if (rc) + return rc; =20 if (timer->capability & OMAP_TIMER_NEEDS_RESET) { rc =3D omap_dm_timer_reset(timer); if (rc) { - omap_dm_timer_disable(timer); + pm_runtime_put_sync(dev); return rc; } } =20 __omap_dm_timer_enable_posted(timer); - omap_dm_timer_disable(timer); + pm_runtime_put_sync(dev); =20 return 0; } @@ -628,12 +638,16 @@ __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmas= k) =20 static int omap_dm_timer_start(struct omap_dm_timer *timer) { + struct device *dev =3D &timer->pdev->dev; + int rc; u32 l; =20 if (unlikely(!timer)) return -EINVAL; =20 - omap_dm_timer_enable(timer); + rc =3D pm_runtime_resume_and_get(dev); + if (rc) + return rc; =20 l =3D dmtimer_read(timer, OMAP_TIMER_CTRL_REG); if (!(l & OMAP_TIMER_CTRL_ST)) { @@ -646,6 +660,7 @@ static int omap_dm_timer_start(struct omap_dm_timer *ti= mer) =20 static int omap_dm_timer_stop(struct omap_dm_timer *timer) { + struct device *dev =3D &timer->pdev->dev; unsigned long rate =3D 0; =20 if (unlikely(!timer)) @@ -656,32 +671,47 @@ static int omap_dm_timer_stop(struct omap_dm_timer *t= imer) =20 __omap_dm_timer_stop(timer, rate); =20 - omap_dm_timer_disable(timer); + pm_runtime_put_sync(dev); + return 0; } =20 static int omap_dm_timer_set_load(struct omap_dm_timer *timer, unsigned int load) { + struct device *dev; + int rc; + if (unlikely(!timer)) return -EINVAL; =20 - omap_dm_timer_enable(timer); + dev =3D &timer->pdev->dev; + rc =3D pm_runtime_resume_and_get(dev); + if (rc) + return rc; + dmtimer_write(timer, OMAP_TIMER_LOAD_REG, load); =20 - omap_dm_timer_disable(timer); + pm_runtime_put_sync(dev); + return 0; } =20 static int omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable, unsigned int match) { + struct device *dev; + int rc; u32 l; =20 if (unlikely(!timer)) return -EINVAL; =20 - omap_dm_timer_enable(timer); + dev =3D &timer->pdev->dev; + rc =3D pm_runtime_resume_and_get(dev); + if (rc) + return rc; + l =3D dmtimer_read(timer, OMAP_TIMER_CTRL_REG); if (enable) l |=3D OMAP_TIMER_CTRL_CE; @@ -690,19 +720,26 @@ static int omap_dm_timer_set_match(struct omap_dm_tim= er *timer, int enable, dmtimer_write(timer, OMAP_TIMER_MATCH_REG, match); dmtimer_write(timer, OMAP_TIMER_CTRL_REG, l); =20 - omap_dm_timer_disable(timer); + pm_runtime_put_sync(dev); + return 0; } =20 static int omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on, int toggle, int trigger, int autoreload) { + struct device *dev; + int rc; u32 l; =20 if (unlikely(!timer)) return -EINVAL; =20 - omap_dm_timer_enable(timer); + dev =3D &timer->pdev->dev; + rc =3D pm_runtime_resume_and_get(dev); + if (rc) + return rc; + l =3D dmtimer_read(timer, OMAP_TIMER_CTRL_REG); l &=3D ~(OMAP_TIMER_CTRL_GPOCFG | OMAP_TIMER_CTRL_SCPWM | OMAP_TIMER_CTRL_PT | (0x03 << 10) | OMAP_TIMER_CTRL_AR); @@ -715,20 +752,28 @@ static int omap_dm_timer_set_pwm(struct omap_dm_timer= *timer, int def_on, l |=3D OMAP_TIMER_CTRL_AR; dmtimer_write(timer, OMAP_TIMER_CTRL_REG, l); =20 - omap_dm_timer_disable(timer); + pm_runtime_put_sync(dev); + return 0; } =20 static int omap_dm_timer_get_pwm_status(struct omap_dm_timer *timer) { + struct device *dev; + int rc; u32 l; =20 if (unlikely(!timer)) return -EINVAL; =20 - omap_dm_timer_enable(timer); + dev =3D &timer->pdev->dev; + rc =3D pm_runtime_resume_and_get(dev); + if (rc) + return rc; + l =3D dmtimer_read(timer, OMAP_TIMER_CTRL_REG); - omap_dm_timer_disable(timer); + + pm_runtime_put_sync(dev); =20 return l; } @@ -736,12 +781,18 @@ static int omap_dm_timer_get_pwm_status(struct omap_d= m_timer *timer) static int omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler) { + struct device *dev; + int rc; u32 l; =20 if (unlikely(!timer) || prescaler < -1 || prescaler > 7) return -EINVAL; =20 - omap_dm_timer_enable(timer); + dev =3D &timer->pdev->dev; + rc =3D pm_runtime_resume_and_get(dev); + if (rc) + return rc; + l =3D dmtimer_read(timer, OMAP_TIMER_CTRL_REG); l &=3D ~(OMAP_TIMER_CTRL_PRE | (0x07 << 2)); if (prescaler >=3D 0) { @@ -750,20 +801,29 @@ static int omap_dm_timer_set_prescaler(struct omap_dm= _timer *timer, } dmtimer_write(timer, OMAP_TIMER_CTRL_REG, l); =20 - omap_dm_timer_disable(timer); + pm_runtime_put_sync(dev); + return 0; } =20 static int omap_dm_timer_set_int_enable(struct omap_dm_timer *timer, unsigned int value) { + struct device *dev; + int rc; + if (unlikely(!timer)) return -EINVAL; =20 - omap_dm_timer_enable(timer); + dev =3D &timer->pdev->dev; + rc =3D pm_runtime_resume_and_get(dev); + if (rc) + return rc; + __omap_dm_timer_int_enable(timer, value); =20 - omap_dm_timer_disable(timer); + pm_runtime_put_sync(dev); + return 0; } =20 @@ -776,12 +836,17 @@ static int omap_dm_timer_set_int_enable(struct omap_d= m_timer *timer, */ static int omap_dm_timer_set_int_disable(struct omap_dm_timer *timer, u32 = mask) { + struct device *dev; u32 l =3D mask; + int rc; =20 if (unlikely(!timer)) return -EINVAL; =20 - omap_dm_timer_enable(timer); + dev =3D &timer->pdev->dev; + rc =3D pm_runtime_resume_and_get(dev); + if (rc) + return rc; =20 if (timer->revision =3D=3D 1) l =3D dmtimer_read(timer, timer->irq_ena) & ~mask; @@ -790,7 +855,8 @@ static int omap_dm_timer_set_int_disable(struct omap_dm= _timer *timer, u32 mask) l =3D dmtimer_read(timer, OMAP_TIMER_WAKEUP_EN_REG) & ~mask; dmtimer_write(timer, OMAP_TIMER_WAKEUP_EN_REG, l); =20 - omap_dm_timer_disable(timer); + pm_runtime_put_sync(dev); + return 0; } =20 @@ -943,11 +1009,11 @@ static int omap_dm_timer_probe(struct platform_devic= e *pdev) pm_runtime_enable(dev); =20 if (!timer->reserved) { - ret =3D pm_runtime_get_sync(dev); - if (ret < 0) { + ret =3D pm_runtime_resume_and_get(dev); + if (ret) { dev_err(dev, "%s: pm_runtime_get_sync failed!\n", __func__); - goto err_get_sync; + goto err_disable; } __omap_dm_timer_init_regs(timer); pm_runtime_put(dev); @@ -962,8 +1028,7 @@ static int omap_dm_timer_probe(struct platform_device = *pdev) =20 return 0; =20 -err_get_sync: - pm_runtime_put_noidle(dev); +err_disable: pm_runtime_disable(dev); return ret; } --=20 2.37.1 From nobody Sat Apr 11 06:29:29 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 71D62C25B06 for ; Mon, 15 Aug 2022 13:14:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242821AbiHONOE (ORCPT ); Mon, 15 Aug 2022 09:14:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53322 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242792AbiHONOB (ORCPT ); Mon, 15 Aug 2022 09:14:01 -0400 Received: from muru.com (muru.com [72.249.23.125]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id AFBE51928E; Mon, 15 Aug 2022 06:13:38 -0700 (PDT) Received: from hillo.muru.com (localhost [127.0.0.1]) by muru.com (Postfix) with ESMTP id 3A5758218; Mon, 15 Aug 2022 13:06:45 +0000 (UTC) From: Tony Lindgren To: Daniel Lezcano , Thomas Gleixner Cc: Aaro Koskinen , Grygorii Strashko , Janusz Krzysztofik , Keerthy , Ladislav Michl , Nishanth Menon , Suman Anna , Vignesh Raghavendra , linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 7/9] clocksource/drivers/timer-ti-dm: Move struct omap_dm_timer fields to driver Date: Mon, 15 Aug 2022 16:12:48 +0300 Message-Id: <20220815131250.34603-8-tony@atomide.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220815131250.34603-1-tony@atomide.com> References: <20220815131250.34603-1-tony@atomide.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" There is no longer any need to expose the elements of struct omap_dm_timer outside the driver. The pwm and remoteproc drivers just use struct omap_dm_timer as a cookie. Let's move the elements of struct omap_dm_timer into struct dmtimer that is private to the driver. To do this, we mostly rename omap_dm_timer to dmtimer in the driver. We keep omap_dm_timer only for the exposed functions in the platform_data for the pwm and remoteproc drivers. Let's also add a note about not using the exposed functions internally as those will get deprecated eventually in favor of Linux generic frameworks. Signed-off-by: Tony Lindgren Reviewed-by: Janusz Krzysztofik --- drivers/clocksource/timer-ti-dm.c | 218 +++++++++++++++++++++++------- include/clocksource/timer-ti-dm.h | 43 ------ 2 files changed, 170 insertions(+), 91 deletions(-) diff --git a/drivers/clocksource/timer-ti-dm.c b/drivers/clocksource/timer-= ti-dm.c --- a/drivers/clocksource/timer-ti-dm.c +++ b/drivers/clocksource/timer-ti-dm.c @@ -95,6 +95,53 @@ #define OMAP_TIMER_TICK_INT_MASK_COUNT_REG \ (_OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET | (WP_TOWR << WPSHIFT)) =20 +struct timer_regs { + u32 ocp_cfg; + u32 tidr; + u32 tier; + u32 twer; + u32 tclr; + u32 tcrr; + u32 tldr; + u32 ttrg; + u32 twps; + u32 tmar; + u32 tcar1; + u32 tsicr; + u32 tcar2; + u32 tpir; + u32 tnir; + u32 tcvr; + u32 tocr; + u32 towr; +}; + +struct dmtimer { + struct omap_dm_timer cookie; + int id; + int irq; + struct clk *fclk; + + void __iomem *io_base; + int irq_stat; /* TISR/IRQSTATUS interrupt status */ + int irq_ena; /* irq enable */ + int irq_dis; /* irq disable, only on v2 ip */ + void __iomem *pend; /* write pending */ + void __iomem *func_base; /* function register base */ + + atomic_t enabled; + unsigned long rate; + unsigned reserved:1; + unsigned posted:1; + struct timer_regs context; + int revision; + u32 capability; + u32 errata; + struct platform_device *pdev; + struct list_head node; + struct notifier_block nb; +}; + static u32 omap_reserved_systimers; static LIST_HEAD(omap_timer_list); static DEFINE_SPINLOCK(dm_timer_lock); @@ -115,7 +162,7 @@ enum { * pending bit must be checked. Otherwise a read of a non completed write * will produce an error. */ -static inline u32 dmtimer_read(struct omap_dm_timer *timer, u32 reg) +static inline u32 dmtimer_read(struct dmtimer *timer, u32 reg) { u16 wp, offset; =20 @@ -140,7 +187,7 @@ static inline u32 dmtimer_read(struct omap_dm_timer *ti= mer, u32 reg) * pending bit must be checked. Otherwise a write on a register which has a * pending write will be lost. */ -static inline void dmtimer_write(struct omap_dm_timer *timer, u32 reg, u32= val) +static inline void dmtimer_write(struct dmtimer *timer, u32 reg, u32 val) { u16 wp, offset; =20 @@ -155,7 +202,7 @@ static inline void dmtimer_write(struct omap_dm_timer *= timer, u32 reg, u32 val) writel_relaxed(val, timer->func_base + offset); } =20 -static inline void __omap_dm_timer_init_regs(struct omap_dm_timer *timer) +static inline void __omap_dm_timer_init_regs(struct dmtimer *timer) { u32 tidr; =20 @@ -190,7 +237,7 @@ static inline void __omap_dm_timer_init_regs(struct oma= p_dm_timer *timer) * complete. Enabling this feature can improve performance for writing to = the * timer registers. */ -static inline void __omap_dm_timer_enable_posted(struct omap_dm_timer *tim= er) +static inline void __omap_dm_timer_enable_posted(struct dmtimer *timer) { if (timer->posted) return; @@ -206,7 +253,7 @@ static inline void __omap_dm_timer_enable_posted(struct= omap_dm_timer *timer) timer->posted =3D OMAP_TIMER_POSTED; } =20 -static inline void __omap_dm_timer_stop(struct omap_dm_timer *timer, +static inline void __omap_dm_timer_stop(struct dmtimer *timer, unsigned long rate) { u32 l; @@ -230,26 +277,26 @@ static inline void __omap_dm_timer_stop(struct omap_d= m_timer *timer, dmtimer_write(timer, timer->irq_stat, OMAP_TIMER_INT_OVERFLOW); } =20 -static inline void __omap_dm_timer_int_enable(struct omap_dm_timer *timer, - unsigned int value) +static inline void __omap_dm_timer_int_enable(struct dmtimer *timer, + unsigned int value) { dmtimer_write(timer, timer->irq_ena, value); dmtimer_write(timer, OMAP_TIMER_WAKEUP_EN_REG, value); } =20 static inline unsigned int -__omap_dm_timer_read_counter(struct omap_dm_timer *timer) +__omap_dm_timer_read_counter(struct dmtimer *timer) { return dmtimer_read(timer, OMAP_TIMER_COUNTER_REG); } =20 -static inline void __omap_dm_timer_write_status(struct omap_dm_timer *time= r, +static inline void __omap_dm_timer_write_status(struct dmtimer *timer, unsigned int value) { dmtimer_write(timer, timer->irq_stat, value); } =20 -static void omap_timer_restore_context(struct omap_dm_timer *timer) +static void omap_timer_restore_context(struct dmtimer *timer) { dmtimer_write(timer, OMAP_TIMER_OCP_CFG_OFFSET, timer->context.ocp_cfg); =20 @@ -262,7 +309,7 @@ static void omap_timer_restore_context(struct omap_dm_t= imer *timer) dmtimer_write(timer, OMAP_TIMER_CTRL_REG, timer->context.tclr); } =20 -static void omap_timer_save_context(struct omap_dm_timer *timer) +static void omap_timer_save_context(struct dmtimer *timer) { timer->context.ocp_cfg =3D dmtimer_read(timer, OMAP_TIMER_OCP_CFG_OFFSET); =20 @@ -277,9 +324,9 @@ static void omap_timer_save_context(struct omap_dm_time= r *timer) static int omap_timer_context_notifier(struct notifier_block *nb, unsigned long cmd, void *v) { - struct omap_dm_timer *timer; + struct dmtimer *timer; =20 - timer =3D container_of(nb, struct omap_dm_timer, nb); + timer =3D container_of(nb, struct dmtimer, nb); =20 switch (cmd) { case CPU_CLUSTER_PM_ENTER: @@ -301,7 +348,7 @@ static int omap_timer_context_notifier(struct notifier_= block *nb, return NOTIFY_OK; } =20 -static int omap_dm_timer_reset(struct omap_dm_timer *timer) +static int omap_dm_timer_reset(struct dmtimer *timer) { u32 l, timeout =3D 100000; =20 @@ -329,13 +376,29 @@ static int omap_dm_timer_reset(struct omap_dm_timer *= timer) return 0; } =20 -static int omap_dm_timer_set_source(struct omap_dm_timer *timer, int sourc= e) +/* + * Functions exposed to PWM and remoteproc drivers via platform_data. + * Do not use these in the driver, these will get deprecated and will + * will be replaced by Linux generic framework functions such as + * chained interrupts and clock framework. + */ +static struct dmtimer *to_dmtimer(struct omap_dm_timer *cookie) +{ + if (!cookie) + return NULL; + + return container_of(cookie, struct dmtimer, cookie); +} + +static int omap_dm_timer_set_source(struct omap_dm_timer *cookie, int sour= ce) { int ret; const char *parent_name; struct clk *parent; struct dmtimer_platform_data *pdata; + struct dmtimer *timer; =20 + timer =3D to_dmtimer(cookie); if (unlikely(!timer) || IS_ERR(timer->fclk)) return -EINVAL; =20 @@ -385,8 +448,9 @@ static int omap_dm_timer_set_source(struct omap_dm_time= r *timer, int source) return ret; } =20 -static void omap_dm_timer_enable(struct omap_dm_timer *timer) +static void omap_dm_timer_enable(struct omap_dm_timer *cookie) { + struct dmtimer *timer =3D to_dmtimer(cookie); struct device *dev =3D &timer->pdev->dev; int rc; =20 @@ -395,14 +459,15 @@ static void omap_dm_timer_enable(struct omap_dm_timer= *timer) dev_err(dev, "could not enable timer\n"); } =20 -static void omap_dm_timer_disable(struct omap_dm_timer *timer) +static void omap_dm_timer_disable(struct omap_dm_timer *cookie) { + struct dmtimer *timer =3D to_dmtimer(cookie); struct device *dev =3D &timer->pdev->dev; =20 pm_runtime_put_sync(dev); } =20 -static int omap_dm_timer_prepare(struct omap_dm_timer *timer) +static int omap_dm_timer_prepare(struct dmtimer *timer) { struct device *dev =3D &timer->pdev->dev; int rc; @@ -442,9 +507,9 @@ static inline u32 omap_dm_timer_reserved_systimer(int i= d) return (omap_reserved_systimers & (1 << (id - 1))) ? 1 : 0; } =20 -static struct omap_dm_timer *_omap_dm_timer_request(int req_type, void *da= ta) +static struct dmtimer *_omap_dm_timer_request(int req_type, void *data) { - struct omap_dm_timer *timer =3D NULL, *t; + struct dmtimer *timer =3D NULL, *t; struct device_node *np =3D NULL; unsigned long flags; u32 cap =3D 0; @@ -528,11 +593,19 @@ static struct omap_dm_timer *_omap_dm_timer_request(i= nt req_type, void *data) =20 static struct omap_dm_timer *omap_dm_timer_request(void) { - return _omap_dm_timer_request(REQUEST_ANY, NULL); + struct dmtimer *timer; + + timer =3D _omap_dm_timer_request(REQUEST_ANY, NULL); + if (!timer) + return NULL; + + return &timer->cookie; } =20 static struct omap_dm_timer *omap_dm_timer_request_specific(int id) { + struct dmtimer *timer; + /* Requesting timer by ID is not supported when device tree is used */ if (of_have_populated_dt()) { pr_warn("%s: Please use omap_dm_timer_request_by_node()\n", @@ -540,7 +613,11 @@ static struct omap_dm_timer *omap_dm_timer_request_spe= cific(int id) return NULL; } =20 - return _omap_dm_timer_request(REQUEST_BY_ID, &id); + timer =3D _omap_dm_timer_request(REQUEST_BY_ID, &id); + if (!timer) + return NULL; + + return &timer->cookie; } =20 /** @@ -552,14 +629,23 @@ static struct omap_dm_timer *omap_dm_timer_request_sp= ecific(int id) */ static struct omap_dm_timer *omap_dm_timer_request_by_node(struct device_n= ode *np) { + struct dmtimer *timer; + if (!np) return NULL; =20 - return _omap_dm_timer_request(REQUEST_BY_NODE, np); + timer =3D _omap_dm_timer_request(REQUEST_BY_NODE, np); + if (!timer) + return NULL; + + return &timer->cookie; } =20 -static int omap_dm_timer_free(struct omap_dm_timer *timer) +static int omap_dm_timer_free(struct omap_dm_timer *cookie) { + struct dmtimer *timer; + + timer =3D to_dmtimer(cookie); if (unlikely(!timer)) return -EINVAL; =20 @@ -570,8 +656,9 @@ static int omap_dm_timer_free(struct omap_dm_timer *tim= er) return 0; } =20 -int omap_dm_timer_get_irq(struct omap_dm_timer *timer) +int omap_dm_timer_get_irq(struct omap_dm_timer *cookie) { + struct dmtimer *timer =3D to_dmtimer(cookie); if (timer) return timer->irq; return -EINVAL; @@ -580,7 +667,7 @@ int omap_dm_timer_get_irq(struct omap_dm_timer *timer) #if defined(CONFIG_ARCH_OMAP1) #include =20 -static struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer) +static struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *cookie) { return NULL; } @@ -592,7 +679,7 @@ static struct clk *omap_dm_timer_get_fclk(struct omap_d= m_timer *timer) __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask) { int i =3D 0; - struct omap_dm_timer *timer =3D NULL; + struct dmtimer *timer =3D NULL; unsigned long flags; =20 /* If ARMXOR cannot be idled this function call is unnecessary */ @@ -620,8 +707,10 @@ __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask) =20 #else =20 -static struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer) +static struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *cookie) { + struct dmtimer *timer =3D to_dmtimer(cookie); + if (timer && !IS_ERR(timer->fclk)) return timer->fclk; return NULL; @@ -636,15 +725,19 @@ __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmas= k) =20 #endif =20 -static int omap_dm_timer_start(struct omap_dm_timer *timer) +static int omap_dm_timer_start(struct omap_dm_timer *cookie) { - struct device *dev =3D &timer->pdev->dev; + struct dmtimer *timer; + struct device *dev; int rc; u32 l; =20 + timer =3D to_dmtimer(cookie); if (unlikely(!timer)) return -EINVAL; =20 + dev =3D &timer->pdev->dev; + rc =3D pm_runtime_resume_and_get(dev); if (rc) return rc; @@ -658,14 +751,18 @@ static int omap_dm_timer_start(struct omap_dm_timer *= timer) return 0; } =20 -static int omap_dm_timer_stop(struct omap_dm_timer *timer) +static int omap_dm_timer_stop(struct omap_dm_timer *cookie) { - struct device *dev =3D &timer->pdev->dev; + struct dmtimer *timer; + struct device *dev; unsigned long rate =3D 0; =20 + timer =3D to_dmtimer(cookie); if (unlikely(!timer)) return -EINVAL; =20 + dev =3D &timer->pdev->dev; + if (!(timer->capability & OMAP_TIMER_NEEDS_RESET)) rate =3D clk_get_rate(timer->fclk); =20 @@ -676,12 +773,14 @@ static int omap_dm_timer_stop(struct omap_dm_timer *t= imer) return 0; } =20 -static int omap_dm_timer_set_load(struct omap_dm_timer *timer, +static int omap_dm_timer_set_load(struct omap_dm_timer *cookie, unsigned int load) { + struct dmtimer *timer; struct device *dev; int rc; =20 + timer =3D to_dmtimer(cookie); if (unlikely(!timer)) return -EINVAL; =20 @@ -697,13 +796,15 @@ static int omap_dm_timer_set_load(struct omap_dm_time= r *timer, return 0; } =20 -static int omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable, +static int omap_dm_timer_set_match(struct omap_dm_timer *cookie, int enabl= e, unsigned int match) { + struct dmtimer *timer; struct device *dev; int rc; u32 l; =20 + timer =3D to_dmtimer(cookie); if (unlikely(!timer)) return -EINVAL; =20 @@ -725,13 +826,15 @@ static int omap_dm_timer_set_match(struct omap_dm_tim= er *timer, int enable, return 0; } =20 -static int omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on, +static int omap_dm_timer_set_pwm(struct omap_dm_timer *cookie, int def_on, int toggle, int trigger, int autoreload) { + struct dmtimer *timer; struct device *dev; int rc; u32 l; =20 + timer =3D to_dmtimer(cookie); if (unlikely(!timer)) return -EINVAL; =20 @@ -757,12 +860,14 @@ static int omap_dm_timer_set_pwm(struct omap_dm_timer= *timer, int def_on, return 0; } =20 -static int omap_dm_timer_get_pwm_status(struct omap_dm_timer *timer) +static int omap_dm_timer_get_pwm_status(struct omap_dm_timer *cookie) { + struct dmtimer *timer; struct device *dev; int rc; u32 l; =20 + timer =3D to_dmtimer(cookie); if (unlikely(!timer)) return -EINVAL; =20 @@ -778,13 +883,15 @@ static int omap_dm_timer_get_pwm_status(struct omap_d= m_timer *timer) return l; } =20 -static int omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, - int prescaler) +static int omap_dm_timer_set_prescaler(struct omap_dm_timer *cookie, + int prescaler) { + struct dmtimer *timer; struct device *dev; int rc; u32 l; =20 + timer =3D to_dmtimer(cookie); if (unlikely(!timer) || prescaler < -1 || prescaler > 7) return -EINVAL; =20 @@ -806,12 +913,14 @@ static int omap_dm_timer_set_prescaler(struct omap_dm= _timer *timer, return 0; } =20 -static int omap_dm_timer_set_int_enable(struct omap_dm_timer *timer, +static int omap_dm_timer_set_int_enable(struct omap_dm_timer *cookie, unsigned int value) { + struct dmtimer *timer; struct device *dev; int rc; =20 + timer =3D to_dmtimer(cookie); if (unlikely(!timer)) return -EINVAL; =20 @@ -834,12 +943,14 @@ static int omap_dm_timer_set_int_enable(struct omap_d= m_timer *timer, * * Disables the specified timer interrupts for a timer. */ -static int omap_dm_timer_set_int_disable(struct omap_dm_timer *timer, u32 = mask) +static int omap_dm_timer_set_int_disable(struct omap_dm_timer *cookie, u32= mask) { + struct dmtimer *timer; struct device *dev; u32 l =3D mask; int rc; =20 + timer =3D to_dmtimer(cookie); if (unlikely(!timer)) return -EINVAL; =20 @@ -860,10 +971,12 @@ static int omap_dm_timer_set_int_disable(struct omap_= dm_timer *timer, u32 mask) return 0; } =20 -static unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer) +static unsigned int omap_dm_timer_read_status(struct omap_dm_timer *cookie) { + struct dmtimer *timer; unsigned int l; =20 + timer =3D to_dmtimer(cookie); if (unlikely(!timer || !atomic_read(&timer->enabled))) { pr_err("%s: timer not available or enabled.\n", __func__); return 0; @@ -874,8 +987,11 @@ static unsigned int omap_dm_timer_read_status(struct o= map_dm_timer *timer) return l; } =20 -static int omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigne= d int value) +static int omap_dm_timer_write_status(struct omap_dm_timer *cookie, unsign= ed int value) { + struct dmtimer *timer; + + timer =3D to_dmtimer(cookie); if (unlikely(!timer || !atomic_read(&timer->enabled))) return -EINVAL; =20 @@ -884,8 +1000,11 @@ static int omap_dm_timer_write_status(struct omap_dm_= timer *timer, unsigned int return 0; } =20 -static unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer) +static unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *cooki= e) { + struct dmtimer *timer; + + timer =3D to_dmtimer(cookie); if (unlikely(!timer || !atomic_read(&timer->enabled))) { pr_err("%s: timer not iavailable or enabled.\n", __func__); return 0; @@ -894,8 +1013,11 @@ static unsigned int omap_dm_timer_read_counter(struct= omap_dm_timer *timer) return __omap_dm_timer_read_counter(timer); } =20 -static int omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsign= ed int value) +static int omap_dm_timer_write_counter(struct omap_dm_timer *cookie, unsig= ned int value) { + struct dmtimer *timer; + + timer =3D to_dmtimer(cookie); if (unlikely(!timer || !atomic_read(&timer->enabled))) { pr_err("%s: timer not available or enabled.\n", __func__); return -EINVAL; @@ -910,7 +1032,7 @@ static int omap_dm_timer_write_counter(struct omap_dm_= timer *timer, unsigned int =20 static int __maybe_unused omap_dm_timer_runtime_suspend(struct device *dev) { - struct omap_dm_timer *timer =3D dev_get_drvdata(dev); + struct dmtimer *timer =3D dev_get_drvdata(dev); =20 atomic_set(&timer->enabled, 0); =20 @@ -924,7 +1046,7 @@ static int __maybe_unused omap_dm_timer_runtime_suspen= d(struct device *dev) =20 static int __maybe_unused omap_dm_timer_runtime_resume(struct device *dev) { - struct omap_dm_timer *timer =3D dev_get_drvdata(dev); + struct dmtimer *timer =3D dev_get_drvdata(dev); =20 if (!(timer->capability & OMAP_TIMER_ALWON) && timer->func_base) omap_timer_restore_context(timer); @@ -951,7 +1073,7 @@ static const struct of_device_id omap_timer_match[]; static int omap_dm_timer_probe(struct platform_device *pdev) { unsigned long flags; - struct omap_dm_timer *timer; + struct dmtimer *timer; struct device *dev =3D &pdev->dev; const struct dmtimer_platform_data *pdata; int ret; @@ -1043,7 +1165,7 @@ static int omap_dm_timer_probe(struct platform_device= *pdev) */ static int omap_dm_timer_remove(struct platform_device *pdev) { - struct omap_dm_timer *timer; + struct dmtimer *timer; unsigned long flags; int ret =3D -EINVAL; =20 diff --git a/include/clocksource/timer-ti-dm.h b/include/clocksource/timer-= ti-dm.h --- a/include/clocksource/timer-ti-dm.h +++ b/include/clocksource/timer-ti-dm.h @@ -59,50 +59,7 @@ #define OMAP_TIMER_NEEDS_RESET 0x10000000 #define OMAP_TIMER_HAS_DSP_IRQ 0x08000000 =20 -struct timer_regs { - u32 ocp_cfg; - u32 tidr; - u32 tier; - u32 twer; - u32 tclr; - u32 tcrr; - u32 tldr; - u32 ttrg; - u32 twps; - u32 tmar; - u32 tcar1; - u32 tsicr; - u32 tcar2; - u32 tpir; - u32 tnir; - u32 tcvr; - u32 tocr; - u32 towr; -}; - struct omap_dm_timer { - int id; - int irq; - struct clk *fclk; - - void __iomem *io_base; - int irq_stat; /* TISR/IRQSTATUS interrupt status */ - int irq_ena; /* irq enable */ - int irq_dis; /* irq disable, only on v2 ip */ - void __iomem *pend; /* write pending */ - void __iomem *func_base; /* function register base */ - - atomic_t enabled; - unsigned long rate; - unsigned reserved:1; - unsigned posted:1; - struct timer_regs context; - int revision; - u32 capability; - u32 errata; - struct platform_device *pdev; - struct list_head node; - struct notifier_block nb; }; =20 int omap_dm_timer_get_irq(struct omap_dm_timer *timer); --=20 2.37.1 From nobody Sat Apr 11 06:29:29 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 21278C00140 for ; Mon, 15 Aug 2022 13:14:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242863AbiHONOQ (ORCPT ); Mon, 15 Aug 2022 09:14:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53442 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242807AbiHONOI (ORCPT ); Mon, 15 Aug 2022 09:14:08 -0400 Received: from muru.com (muru.com [72.249.23.125]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 9B48A1AF06; Mon, 15 Aug 2022 06:13:41 -0700 (PDT) Received: from hillo.muru.com (localhost [127.0.0.1]) by muru.com (Postfix) with ESMTP id EB9C880FB; Mon, 15 Aug 2022 13:06:47 +0000 (UTC) From: Tony Lindgren To: Daniel Lezcano , Thomas Gleixner Cc: Aaro Koskinen , Grygorii Strashko , Janusz Krzysztofik , Keerthy , Ladislav Michl , Nishanth Menon , Suman Anna , Vignesh Raghavendra , linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 8/9] clocksource/drivers/timer-ti-dm: Add flag to detect omap1 Date: Mon, 15 Aug 2022 16:12:49 +0300 Message-Id: <20220815131250.34603-9-tony@atomide.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220815131250.34603-1-tony@atomide.com> References: <20220815131250.34603-1-tony@atomide.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Let's make it clear that some features need to be tested currently on omap1. Only omap1 still uses platform_data. Signed-off-by: Tony Lindgren Reviewed-by: Janusz Krzysztofik --- drivers/clocksource/timer-ti-dm.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/clocksource/timer-ti-dm.c b/drivers/clocksource/timer-= ti-dm.c --- a/drivers/clocksource/timer-ti-dm.c +++ b/drivers/clocksource/timer-ti-dm.c @@ -133,6 +133,7 @@ struct dmtimer { unsigned long rate; unsigned reserved:1; unsigned posted:1; + unsigned omap1:1; struct timer_regs context; int revision; u32 capability; @@ -423,7 +424,7 @@ static int omap_dm_timer_set_source(struct omap_dm_time= r *cookie, int source) * use the clock framework to set the parent clock. To be removed * once OMAP1 migrated to using clock framework for dmtimers */ - if (pdata && pdata->set_timer_src) + if (timer->omap1 && pdata && pdata->set_timer_src) return pdata->set_timer_src(timer->pdev, source); =20 #if defined(CONFIG_COMMON_CLK) @@ -476,7 +477,7 @@ static int omap_dm_timer_prepare(struct dmtimer *timer) * FIXME: OMAP1 devices do not use the clock framework for dmtimers so * do not call clk_get() for these devices. */ - if (!(timer->capability & OMAP_TIMER_NEEDS_RESET)) { + if (!timer->omap1) { timer->fclk =3D clk_get(&timer->pdev->dev, "fck"); if (WARN_ON_ONCE(IS_ERR(timer->fclk))) { dev_err(&timer->pdev->dev, ": No fclk handle.\n"); @@ -763,7 +764,7 @@ static int omap_dm_timer_stop(struct omap_dm_timer *coo= kie) =20 dev =3D &timer->pdev->dev; =20 - if (!(timer->capability & OMAP_TIMER_NEEDS_RESET)) + if (!timer->omap1) rate =3D clk_get_rate(timer->fclk); =20 __omap_dm_timer_stop(timer, rate); @@ -1119,6 +1120,8 @@ static int omap_dm_timer_probe(struct platform_device= *pdev) timer->reserved =3D omap_dm_timer_reserved_systimer(timer->id); } =20 + timer->omap1 =3D timer->capability & OMAP_TIMER_NEEDS_RESET; + if (!(timer->capability & OMAP_TIMER_ALWON)) { timer->nb.notifier_call =3D omap_timer_context_notifier; cpu_pm_register_notifier(&timer->nb); --=20 2.37.1 From nobody Sat Apr 11 06:29:29 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A030AC00140 for ; Mon, 15 Aug 2022 13:14:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242866AbiHONOU (ORCPT ); Mon, 15 Aug 2022 09:14:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53510 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242826AbiHONOM (ORCPT ); Mon, 15 Aug 2022 09:14:12 -0400 Received: from muru.com (muru.com [72.249.23.125]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id DFFF61CB16; Mon, 15 Aug 2022 06:13:43 -0700 (PDT) Received: from hillo.muru.com (localhost [127.0.0.1]) by muru.com (Postfix) with ESMTP id 84FA78225; Mon, 15 Aug 2022 13:06:50 +0000 (UTC) From: Tony Lindgren To: Daniel Lezcano , Thomas Gleixner Cc: Aaro Koskinen , Grygorii Strashko , Janusz Krzysztofik , Keerthy , Ladislav Michl , Nishanth Menon , Suman Anna , Vignesh Raghavendra , linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 9/9] clocksource/drivers/timer-ti-dm: Get clock in probe with devm_clk_get() Date: Mon, 15 Aug 2022 16:12:50 +0300 Message-Id: <20220815131250.34603-10-tony@atomide.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220815131250.34603-1-tony@atomide.com> References: <20220815131250.34603-1-tony@atomide.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" We can simplify the code a bit by getting the clock in probe, and using devm_clk_get(). This will also make further changes easier as the clock is available in probe instead of prepare. Signed-off-by: Tony Lindgren Reviewed-by: Janusz Krzysztofik --- drivers/clocksource/timer-ti-dm.c | 24 +++++++++--------------- 1 file changed, 9 insertions(+), 15 deletions(-) diff --git a/drivers/clocksource/timer-ti-dm.c b/drivers/clocksource/timer-= ti-dm.c --- a/drivers/clocksource/timer-ti-dm.c +++ b/drivers/clocksource/timer-ti-dm.c @@ -473,18 +473,6 @@ static int omap_dm_timer_prepare(struct dmtimer *timer) struct device *dev =3D &timer->pdev->dev; int rc; =20 - /* - * FIXME: OMAP1 devices do not use the clock framework for dmtimers so - * do not call clk_get() for these devices. - */ - if (!timer->omap1) { - timer->fclk =3D clk_get(&timer->pdev->dev, "fck"); - if (WARN_ON_ONCE(IS_ERR(timer->fclk))) { - dev_err(&timer->pdev->dev, ": No fclk handle.\n"); - return -EINVAL; - } - } - rc =3D pm_runtime_resume_and_get(dev); if (rc) return rc; @@ -650,8 +638,6 @@ static int omap_dm_timer_free(struct omap_dm_timer *coo= kie) if (unlikely(!timer)) return -EINVAL; =20 - clk_put(timer->fclk); - WARN_ON(!timer->reserved); timer->reserved =3D 0; return 0; @@ -1098,7 +1084,6 @@ static int omap_dm_timer_probe(struct platform_device= *pdev) if (timer->irq < 0) return timer->irq; =20 - timer->fclk =3D ERR_PTR(-ENODEV); timer->io_base =3D devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(timer->io_base)) return PTR_ERR(timer->io_base); @@ -1122,6 +1107,15 @@ static int omap_dm_timer_probe(struct platform_devic= e *pdev) =20 timer->omap1 =3D timer->capability & OMAP_TIMER_NEEDS_RESET; =20 + /* OMAP1 devices do not yet use the clock framework for dmtimers */ + if (!timer->omap1) { + timer->fclk =3D devm_clk_get(dev, "fck"); + if (IS_ERR(timer->fclk)) + return PTR_ERR(timer->fclk); + } else { + timer->fclk =3D ERR_PTR(-ENODEV); + } + if (!(timer->capability & OMAP_TIMER_ALWON)) { timer->nb.notifier_call =3D omap_timer_context_notifier; cpu_pm_register_notifier(&timer->nb); --=20 2.37.1