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[34.168.22.137]) by smtp.gmail.com with ESMTPSA id 200-20020a6214d1000000b0052db82ad8b2sm5988233pfu.123.2022.08.14.23.38.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Aug 2022 23:38:33 -0700 (PDT) From: Prashant Malani To: linux-kernel@vger.kernel.org, chrome-platform@lists.linux.dev Cc: bleung@chromium.org, Prashant Malani , Daisuke Nojiri , "Dustin L. Howett" , Greg Kroah-Hartman , Guenter Roeck , "Gustavo A. R. Silva" , Tinghan Shen , Tzung-Bi Shih , Xiang wangx Subject: [PATCH v5 1/7] platform/chrome: Add Type-C mux set command definitions Date: Mon, 15 Aug 2022 06:34:17 +0000 Message-Id: <20220815063555.1384505-2-pmalani@chromium.org> X-Mailer: git-send-email 2.37.1.595.g718a3a8f04-goog In-Reply-To: <20220815063555.1384505-1-pmalani@chromium.org> References: <20220815063555.1384505-1-pmalani@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Copy EC header definitions for the USB Type-C Mux control command from the EC code base. Also pull in "TBT_UFP_REPLY" definitions, since that is the prior entry in the enum. These headers are already present in the EC code base. [1] [1] https://chromium.googlesource.com/chromiumos/platform/ec/+/b80f85a94a42= 3273c1638ef7b662c56931a138dd/include/ec_commands.h Signed-off-by: Prashant Malani Reviewed-by: Tzung-Bi Shih --- Changes since v4: - No changes. Changes since v3: - No changes. Changes since v2: - No changes. Changes since v1: - No changes. include/linux/platform_data/cros_ec_commands.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/include/linux/platform_data/cros_ec_commands.h b/include/linux= /platform_data/cros_ec_commands.h index 8b1b795867a1..5744a2d746aa 100644 --- a/include/linux/platform_data/cros_ec_commands.h +++ b/include/linux/platform_data/cros_ec_commands.h @@ -5724,8 +5724,21 @@ enum typec_control_command { TYPEC_CONTROL_COMMAND_EXIT_MODES, TYPEC_CONTROL_COMMAND_CLEAR_EVENTS, TYPEC_CONTROL_COMMAND_ENTER_MODE, + TYPEC_CONTROL_COMMAND_TBT_UFP_REPLY, + TYPEC_CONTROL_COMMAND_USB_MUX_SET, }; =20 +/* Replies the AP may specify to the TBT EnterMode command as a UFP */ +enum typec_tbt_ufp_reply { + TYPEC_TBT_UFP_REPLY_NAK, + TYPEC_TBT_UFP_REPLY_ACK, +}; + +struct typec_usb_mux_set { + uint8_t mux_index; /* Index of the mux to set in the chain */ + uint8_t mux_flags; /* USB_PD_MUX_*-encoded USB mux state to set */ +} __ec_align1; + struct ec_params_typec_control { uint8_t port; uint8_t command; /* enum typec_control_command */ @@ -5739,6 +5752,8 @@ struct ec_params_typec_control { union { uint32_t clear_events_mask; uint8_t mode_to_enter; /* enum typec_mode */ + uint8_t tbt_ufp_reply; /* enum typec_tbt_ufp_reply */ + struct typec_usb_mux_set mux_params; uint8_t placeholder[128]; }; } __ec_align1; @@ -5817,6 +5832,9 @@ enum tcpc_cc_polarity { #define PD_STATUS_EVENT_SOP_DISC_DONE BIT(0) #define PD_STATUS_EVENT_SOP_PRIME_DISC_DONE BIT(1) #define PD_STATUS_EVENT_HARD_RESET BIT(2) +#define PD_STATUS_EVENT_DISCONNECTED BIT(3) +#define PD_STATUS_EVENT_MUX_0_SET_DONE BIT(4) +#define PD_STATUS_EVENT_MUX_1_SET_DONE BIT(5) =20 struct ec_params_typec_status { uint8_t port; --=20 2.37.1.595.g718a3a8f04-goog From nobody Sat Apr 11 06:32:07 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E357DC00140 for ; Mon, 15 Aug 2022 06:40:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232493AbiHOGkD (ORCPT ); Mon, 15 Aug 2022 02:40:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41044 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231335AbiHOGkB (ORCPT ); Mon, 15 Aug 2022 02:40:01 -0400 Received: from mail-pj1-x102d.google.com (mail-pj1-x102d.google.com [IPv6:2607:f8b0:4864:20::102d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 434C51ADA6 for ; Sun, 14 Aug 2022 23:40:00 -0700 (PDT) Received: by mail-pj1-x102d.google.com with SMTP id p14-20020a17090a74ce00b001f4d04492faso5988253pjl.4 for ; Sun, 14 Aug 2022 23:40:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=3xUHf3HqS3mIbAzLpagrtMfBUff89AJ2SzxASGdwC3U=; b=NyMFVyLH/XSwsw8kvV+j7VDk1gXRk3KDssB9npb6dIfiQSh1g8j1sUNVXvmR6Z+NZx 5ME+fz5LIFMfLrr0vMXJd+hMTuH1NTqQKk5/C41bEJdtZRV3da27DKnf6bRILG4V3UBP UGKOKf/KFPKdVvmUdmhlxfQjSU2ZS7vQo35Y0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=3xUHf3HqS3mIbAzLpagrtMfBUff89AJ2SzxASGdwC3U=; b=wvJm5YwW7z3f8D+ZpCI6uNiifCJtWYfZMdltJ8qkDax9ZkJFLdxNuozxKknwDdpcfP mMgbOWiHGexhgiuhhRUj4Uk1CLDxszWqsJX8ULfnMfVe2Fs8byBUYKgtzw/y9VOhs+1s Ztj3Yd9Du0Ll27xYpD3tKKa4GJl/PTm/CNUUFO4mpc733QIpQ3u4uga0U84QMYUQCKLh FOYFAJE1918V/FoWzP1vHLShxmw4YxmsXJ4X+siHc2NgYC+GKtw10TC/xBIWbkXNonhP P0S6iPQzkg6kz0SlWr8OpgbbtGkoF/6t2JzTQ65GkrOsFg5EWJ8uQ1sA4qhTba4ZLmNz AR4g== X-Gm-Message-State: ACgBeo3Xh299BhkIVQAsoToj2g1/97gDrmvxkdU41F4VU9bbrh9hdJUZ MN/gSBW/f6onbmReoXTC7ldD1V0F3KAIxw== X-Google-Smtp-Source: AA6agR7YLxLck7accSogjcD0azd/9aNq35LIa8JTqXEvJ/9TlpetoFWCVjY8v0YSb5Q9jLMYWU/YFg== X-Received: by 2002:a17:903:41c6:b0:16f:3d1:f63 with SMTP id u6-20020a17090341c600b0016f03d10f63mr15463762ple.50.1660545599581; Sun, 14 Aug 2022 23:39:59 -0700 (PDT) Received: from pmalani.c.googlers.com.com (137.22.168.34.bc.googleusercontent.com. [34.168.22.137]) by smtp.gmail.com with ESMTPSA id 200-20020a6214d1000000b0052db82ad8b2sm5988233pfu.123.2022.08.14.23.39.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Aug 2022 23:39:59 -0700 (PDT) From: Prashant Malani To: linux-kernel@vger.kernel.org, chrome-platform@lists.linux.dev Cc: bleung@chromium.org, Prashant Malani , Daisuke Nojiri , "Dustin L. Howett" , Greg Kroah-Hartman , Guenter Roeck , "Gustavo A. R. Silva" , Lee Jones , Sebastian Reichel , Tinghan Shen , Tzung-Bi Shih , Xiang wangx Subject: [PATCH v5 2/7] platform/chrome: cros_typec_switch: Add switch driver Date: Mon, 15 Aug 2022 06:34:19 +0000 Message-Id: <20220815063555.1384505-3-pmalani@chromium.org> X-Mailer: git-send-email 2.37.1.595.g718a3a8f04-goog In-Reply-To: <20220815063555.1384505-1-pmalani@chromium.org> References: <20220815063555.1384505-1-pmalani@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Introduce a driver to configure USB Type-C mode switches and retimers which are controlled by the Chrome OS EC (Embedded Controller). This allows Type-C port drivers, as well as alternate mode drivers to configure their relevant mode switches and retimers according to the Type-C state they want to achieve. ACPI devices with ID GOOG001A will bind to this driver. Currently, we only register a retimer switch with a stub set function. Subsequent patches will implement the host command set functionality, and introduce mode switches. Signed-off-by: Prashant Malani --- Changes since v4: - Add ACPI dependency to Kconfig. Changes since v3: - No changes. Changes since v2: - Fixed missing "static" identifier. - Removed unnecessary new line for function signature. Changes since v1: - No changes. MAINTAINERS | 1 + drivers/platform/chrome/Kconfig | 11 ++ drivers/platform/chrome/Makefile | 1 + drivers/platform/chrome/cros_typec_switch.c | 170 ++++++++++++++++++++ 4 files changed, 183 insertions(+) create mode 100644 drivers/platform/chrome/cros_typec_switch.c diff --git a/MAINTAINERS b/MAINTAINERS index b7221f4143cb..6fa4da411275 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -4884,6 +4884,7 @@ M: Prashant Malani L: chrome-platform@lists.linux.dev S: Maintained F: drivers/platform/chrome/cros_ec_typec.c +F: drivers/platform/chrome/cros_typec_switch.c =20 CHROMEOS EC USB PD NOTIFY DRIVER M: Prashant Malani diff --git a/drivers/platform/chrome/Kconfig b/drivers/platform/chrome/Kcon= fig index c45fb376d653..55b68f247f02 100644 --- a/drivers/platform/chrome/Kconfig +++ b/drivers/platform/chrome/Kconfig @@ -265,6 +265,17 @@ config CHROMEOS_PRIVACY_SCREEN this should probably always be built into the kernel to avoid or minimize drm probe deferral. =20 +config CROS_TYPEC_SWITCH + tristate "ChromeOS EC Type-C Switch Control" + depends on MFD_CROS_EC_DEV && TYPEC && ACPI + default MFD_CROS_EC_DEV + help + If you say Y here, you get support for configuring the Chrome OS EC Typ= e C + muxes and retimers. + + To compile this driver as a module, choose M here: the module will be + called cros_typec_switch. + source "drivers/platform/chrome/wilco_ec/Kconfig" =20 # Kunit test cases diff --git a/drivers/platform/chrome/Makefile b/drivers/platform/chrome/Mak= efile index f7e74a845afc..2950610101f1 100644 --- a/drivers/platform/chrome/Makefile +++ b/drivers/platform/chrome/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_CHROMEOS_TBMC) +=3D chromeos_tbmc.o obj-$(CONFIG_CROS_EC) +=3D cros_ec.o obj-$(CONFIG_CROS_EC_I2C) +=3D cros_ec_i2c.o obj-$(CONFIG_CROS_EC_ISHTP) +=3D cros_ec_ishtp.o +obj-$(CONFIG_CROS_TYPEC_SWITCH) +=3D cros_typec_switch.o obj-$(CONFIG_CROS_EC_RPMSG) +=3D cros_ec_rpmsg.o obj-$(CONFIG_CROS_EC_SPI) +=3D cros_ec_spi.o cros_ec_lpcs-objs :=3D cros_ec_lpc.o cros_ec_lpc_mec.o diff --git a/drivers/platform/chrome/cros_typec_switch.c b/drivers/platform= /chrome/cros_typec_switch.c new file mode 100644 index 000000000000..0d319e315d57 --- /dev/null +++ b/drivers/platform/chrome/cros_typec_switch.c @@ -0,0 +1,170 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2022 Google LLC + * + * This driver provides the ability to configure Type C muxes and retimers= which are controlled by + * the Chrome OS EC. + */ + +#include +#include +#include +#include +#include + +#define DRV_NAME "cros-typec-switch" + +/* Handles and other relevant data required for each port's switches. */ +struct cros_typec_port { + int port_num; + struct typec_retimer *retimer; + struct cros_typec_switch_data *sdata; +}; + +/* Driver-specific data. */ +struct cros_typec_switch_data { + struct device *dev; + struct cros_ec_device *ec; + struct cros_typec_port *ports[EC_USB_PD_MAX_PORTS]; +}; + +static int cros_typec_retimer_set(struct typec_retimer *retimer, struct ty= pec_retimer_state *state) +{ + return 0; +} + +static void cros_typec_unregister_switches(struct cros_typec_switch_data *= sdata) +{ + int i; + + for (i =3D 0; i < EC_USB_PD_MAX_PORTS; i++) { + if (!sdata->ports[i]) + continue; + typec_retimer_unregister(sdata->ports[i]->retimer); + } +} + +static int cros_typec_register_retimer(struct cros_typec_port *port, struc= t fwnode_handle *fwnode) +{ + struct typec_retimer_desc retimer_desc =3D { + .fwnode =3D fwnode, + .drvdata =3D port, + .name =3D fwnode_get_name(fwnode), + .set =3D cros_typec_retimer_set, + }; + + port->retimer =3D typec_retimer_register(port->sdata->dev, &retimer_desc); + if (IS_ERR(port->retimer)) + return PTR_ERR(port->retimer); + + return 0; +} + +static int cros_typec_register_switches(struct cros_typec_switch_data *sda= ta) +{ + struct cros_typec_port *port =3D NULL; + struct device *dev =3D sdata->dev; + struct fwnode_handle *fwnode; + struct acpi_device *adev; + unsigned long long index; + int ret =3D 0; + int nports; + + nports =3D device_get_child_node_count(dev); + if (nports =3D=3D 0) { + dev_err(dev, "No switch devices found.\n"); + return -ENODEV; + } + + device_for_each_child_node(dev, fwnode) { + port =3D devm_kzalloc(dev, sizeof(*port), GFP_KERNEL); + if (!port) { + ret =3D -ENOMEM; + goto err_switch; + } + + adev =3D to_acpi_device_node(fwnode); + if (!adev) { + dev_err(fwnode->dev, "Couldn't get ACPI device handle\n"); + ret =3D -ENODEV; + goto err_switch; + } + + ret =3D acpi_evaluate_integer(adev->handle, "_ADR", NULL, &index); + if (ACPI_FAILURE(ret)) { + dev_err(fwnode->dev, "_ADR wasn't evaluated\n"); + ret =3D -ENODATA; + goto err_switch; + } + + if (index < 0 || index >=3D EC_USB_PD_MAX_PORTS) { + dev_err(fwnode->dev, "Invalid port index number: %llu", index); + ret =3D -EINVAL; + goto err_switch; + } + port->sdata =3D sdata; + port->port_num =3D index; + sdata->ports[index] =3D port; + + ret =3D cros_typec_register_retimer(port, fwnode); + if (ret) { + dev_err(dev, "Retimer switch register failed\n"); + goto err_switch; + } + + dev_dbg(dev, "Retimer switch registered for index %llu\n", index); + } + + return 0; +err_switch: + cros_typec_unregister_switches(sdata); + return ret; +} + +static int cros_typec_switch_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct cros_typec_switch_data *sdata; + + sdata =3D devm_kzalloc(dev, sizeof(*sdata), GFP_KERNEL); + if (!sdata) + return -ENOMEM; + + sdata->dev =3D dev; + sdata->ec =3D dev_get_drvdata(pdev->dev.parent); + + platform_set_drvdata(pdev, sdata); + + return cros_typec_register_switches(sdata); +} + +static int cros_typec_switch_remove(struct platform_device *pdev) +{ + struct cros_typec_switch_data *sdata =3D platform_get_drvdata(pdev); + + cros_typec_unregister_switches(sdata); + return 0; +} + +#ifdef CONFIG_ACPI +static const struct acpi_device_id cros_typec_switch_acpi_id[] =3D { + { "GOOG001A", 0 }, + {} +}; +MODULE_DEVICE_TABLE(acpi, cros_typec_switch_acpi_id); +#endif + +static struct platform_driver cros_typec_switch_driver =3D { + .driver =3D { + .name =3D DRV_NAME, + .acpi_match_table =3D ACPI_PTR(cros_typec_switch_acpi_id), + }, + .probe =3D cros_typec_switch_probe, + .remove =3D cros_typec_switch_remove, +}; + +module_platform_driver(cros_typec_switch_driver); + +MODULE_AUTHOR("Prashant Malani "); +MODULE_DESCRIPTION("Chrome OS EC Type C Switch control"); +MODULE_LICENSE("GPL"); --=20 2.37.1.595.g718a3a8f04-goog From nobody Sat Apr 11 06:32:07 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1465CC00140 for ; Mon, 15 Aug 2022 06:41:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233143AbiHOGl4 (ORCPT ); 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[34.168.22.137]) by smtp.gmail.com with ESMTPSA id 200-20020a6214d1000000b0052db82ad8b2sm5988233pfu.123.2022.08.14.23.41.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Aug 2022 23:41:52 -0700 (PDT) From: Prashant Malani To: linux-kernel@vger.kernel.org, chrome-platform@lists.linux.dev Cc: bleung@chromium.org, Prashant Malani , Daisuke Nojiri , "Dustin L. Howett" , Greg Kroah-Hartman , Guenter Roeck , "Gustavo A. R. Silva" , Tinghan Shen , Tzung-Bi Shih , Xiang wangx Subject: [PATCH v5 3/7] platform/chrome: cros_typec_switch: Set EC retimer Date: Mon, 15 Aug 2022 06:34:21 +0000 Message-Id: <20220815063555.1384505-4-pmalani@chromium.org> X-Mailer: git-send-email 2.37.1.595.g718a3a8f04-goog In-Reply-To: <20220815063555.1384505-1-pmalani@chromium.org> References: <20220815063555.1384505-1-pmalani@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Invoke Chrome EC host commands to set EC-controlled retimer switches to the state the Type-C framework instructs. Signed-off-by: Prashant Malani --- Changes since v4: - Update cros_ec_command() to cros_ec_cmd(). Changes since v3: - No changes. Changes since v2: - No changes. Changes since v1: - No changes. drivers/platform/chrome/cros_typec_switch.c | 56 ++++++++++++++++++++- 1 file changed, 55 insertions(+), 1 deletion(-) diff --git a/drivers/platform/chrome/cros_typec_switch.c b/drivers/platform= /chrome/cros_typec_switch.c index 0d319e315d57..befe35655a9a 100644 --- a/drivers/platform/chrome/cros_typec_switch.c +++ b/drivers/platform/chrome/cros_typec_switch.c @@ -9,7 +9,10 @@ #include #include #include +#include #include +#include +#include #include =20 #define DRV_NAME "cros-typec-switch" @@ -28,9 +31,60 @@ struct cros_typec_switch_data { struct cros_typec_port *ports[EC_USB_PD_MAX_PORTS]; }; =20 +static int cros_typec_cmd_mux_set(struct cros_typec_switch_data *sdata, in= t port_num, u8 index, + u8 state) +{ + struct typec_usb_mux_set params =3D { + .mux_index =3D index, + .mux_flags =3D state, + }; + + struct ec_params_typec_control req =3D { + .port =3D port_num, + .command =3D TYPEC_CONTROL_COMMAND_USB_MUX_SET, + .mux_params =3D params, + }; + + return cros_ec_cmd(sdata->ec, 0, EC_CMD_TYPEC_CONTROL, &req, + sizeof(req), NULL, 0); +} + +static int cros_typec_get_mux_state(unsigned long mode, struct typec_altmo= de *alt) +{ + int ret =3D -EOPNOTSUPP; + + if (mode =3D=3D TYPEC_STATE_SAFE) + ret =3D USB_PD_MUX_SAFE_MODE; + else if (mode =3D=3D TYPEC_STATE_USB) + ret =3D USB_PD_MUX_USB_ENABLED; + else if (alt && alt->svid =3D=3D USB_TYPEC_DP_SID) + ret =3D USB_PD_MUX_DP_ENABLED; + + return ret; +} + +/* + * The Chrome EC treats both mode-switches and retimers as "muxes" for the= purposes of the + * host command API. This common function configures and verifies the reti= mer/mode-switch + * according to the provided setting. + */ +static int cros_typec_configure_mux(struct cros_typec_switch_data *sdata, = int port_num, int index, + unsigned long mode, struct typec_altmode *alt) +{ + int ret =3D cros_typec_get_mux_state(mode, alt); + + if (ret < 0) + return ret; + + return cros_typec_cmd_mux_set(sdata, port_num, index, (u8)ret); +} + static int cros_typec_retimer_set(struct typec_retimer *retimer, struct ty= pec_retimer_state *state) { - return 0; + struct cros_typec_port *port =3D typec_retimer_get_drvdata(retimer); + + /* Retimers have index 1. */ + return cros_typec_configure_mux(port->sdata, port->port_num, 1, state->mo= de, state->alt); } =20 static void cros_typec_unregister_switches(struct cros_typec_switch_data *= sdata) --=20 2.37.1.595.g718a3a8f04-goog From nobody Sat Apr 11 06:32:07 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 51418C00140 for ; Mon, 15 Aug 2022 06:44:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240883AbiHOGoi (ORCPT ); Mon, 15 Aug 2022 02:44:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46074 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235241AbiHOGog (ORCPT ); Mon, 15 Aug 2022 02:44:36 -0400 Received: from mail-pg1-x534.google.com (mail-pg1-x534.google.com [IPv6:2607:f8b0:4864:20::534]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7F16E1AF33 for ; Sun, 14 Aug 2022 23:44:35 -0700 (PDT) Received: by mail-pg1-x534.google.com with SMTP id f65so5803036pgc.12 for ; Sun, 14 Aug 2022 23:44:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=RJziAcdwqSHxXgUj0onY2n8IS5JD3vb95lzQbzWkWLI=; b=XsJEoodtcCGJbDsuP0RLg51aYou66Ds+346IKLbcNX1VzKwLOBFeMf/YEsKX6AVUoR fWlxxUFBeE/4hBHmemMrlt6x9+e8yTABXmMhPZHbWS6LEKKfuHvCnuCsTBl70thUdU6n t7K5vQvej6G9KDjCE28HFd/n7+bZIMDze6fhs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=RJziAcdwqSHxXgUj0onY2n8IS5JD3vb95lzQbzWkWLI=; b=qL+jpUBQnIsK34yizMWXMKPRTDiSF0J9A6J9trN9+J+Y06KQPqMKWuE0JkhvNHkBXb tREcVpd7pvx8rW+WHXCROeyWFdjTm/OH/Ne2Dy3sC4h6vzrbOKBfRBEpgaFfLPqQIWUD G0t+HHf56pSZ6WzKry3AXEjX4aJSufdPwVMKznPBN3EOPLbAOq071swckF0s4/pO/Sg7 3SEcHw4XEmhhYz/W2GtvlCx5SV4HoMDqQDeP+PNmp5Pkxfs6UpQ6tBocIELAPDjP1dLT gRc5BF11G3OHmeSp7CxkCtF8tNxueIY1sP3B0J5d8iD5tkMfSCeyCp8HxqizX9n9W39N RAgw== X-Gm-Message-State: ACgBeo2VFoI9K9htKoT9eVqmBrvhCTx5WpgfTObl10vm3ZIH/N1DBjQy +8qKwDJXEQElnAfbI7HlRHms7IjQ0F9wRA== X-Google-Smtp-Source: AA6agR446wHPCYbLAa9lBoYkAl5m6yhRbR4u1jAAQ8WRws1gaRsilRU1+B7KO66gatZg4a0FpR9Gkg== X-Received: by 2002:a63:8548:0:b0:428:a204:c9f7 with SMTP id u69-20020a638548000000b00428a204c9f7mr3906037pgd.331.1660545874813; Sun, 14 Aug 2022 23:44:34 -0700 (PDT) Received: from pmalani.c.googlers.com.com (137.22.168.34.bc.googleusercontent.com. [34.168.22.137]) by smtp.gmail.com with ESMTPSA id 200-20020a6214d1000000b0052db82ad8b2sm5988233pfu.123.2022.08.14.23.44.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Aug 2022 23:44:34 -0700 (PDT) From: Prashant Malani To: linux-kernel@vger.kernel.org, chrome-platform@lists.linux.dev Cc: bleung@chromium.org, Prashant Malani , Daisuke Nojiri , "Dustin L. Howett" , Greg Kroah-Hartman , Guenter Roeck , "Gustavo A. R. Silva" , Lee Jones , Tzung-Bi Shih , Xiang wangx Subject: [PATCH v5 4/7] platform/chrome: cros_typec_switch: Add event check Date: Mon, 15 Aug 2022 06:34:24 +0000 Message-Id: <20220815063555.1384505-5-pmalani@chromium.org> X-Mailer: git-send-email 2.37.1.595.g718a3a8f04-goog In-Reply-To: <20220815063555.1384505-1-pmalani@chromium.org> References: <20220815063555.1384505-1-pmalani@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The Chrome EC updates Type-C status events when mux set requests from the Application Processor (AP) are completed. Add a check to the flow of configuring muxes to look for this status done bit, so that the driver is aware that the mux set completed successfully or not. Signed-off-by: Prashant Malani --- Changes since v4: - Update cros_ec_command() to cros_ec_cmd(). - Dropped unnecessary Reported-by tag (since this patch is not a bug fix). Changes since v3: - No changes. Changes since v2: - Fixed missing "static" identifier. Changes since v1: - No changes. drivers/platform/chrome/cros_typec_switch.c | 72 ++++++++++++++++++++- 1 file changed, 70 insertions(+), 2 deletions(-) diff --git a/drivers/platform/chrome/cros_typec_switch.c b/drivers/platform= /chrome/cros_typec_switch.c index befe35655a9a..a9e114391321 100644 --- a/drivers/platform/chrome/cros_typec_switch.c +++ b/drivers/platform/chrome/cros_typec_switch.c @@ -7,6 +7,8 @@ */ =20 #include +#include +#include #include #include #include @@ -63,6 +65,40 @@ static int cros_typec_get_mux_state(unsigned long mode, = struct typec_altmode *al return ret; } =20 +static int cros_typec_send_clear_event(struct cros_typec_switch_data *sdat= a, int port_num, + u32 events_mask) +{ + struct ec_params_typec_control req =3D { + .port =3D port_num, + .command =3D TYPEC_CONTROL_COMMAND_CLEAR_EVENTS, + .clear_events_mask =3D events_mask, + }; + + return cros_ec_cmd(sdata->ec, 0, EC_CMD_TYPEC_CONTROL, &req, + sizeof(req), NULL, 0); +} + +static bool cros_typec_check_event(struct cros_typec_switch_data *sdata, i= nt port_num, u32 mask) +{ + struct ec_response_typec_status resp; + struct ec_params_typec_status req =3D { + .port =3D port_num, + }; + int ret; + + ret =3D cros_ec_cmd(sdata->ec, 0, EC_CMD_TYPEC_STATUS, &req, sizeof(req), + &resp, sizeof(resp)); + if (ret < 0) { + dev_warn(sdata->dev, "EC_CMD_TYPEC_STATUS failed for port: %d\n", port_n= um); + return false; + } + + if (resp.events & mask) + return true; + + return false; +} + /* * The Chrome EC treats both mode-switches and retimers as "muxes" for the= purposes of the * host command API. This common function configures and verifies the reti= mer/mode-switch @@ -71,12 +107,44 @@ static int cros_typec_get_mux_state(unsigned long mode= , struct typec_altmode *al static int cros_typec_configure_mux(struct cros_typec_switch_data *sdata, = int port_num, int index, unsigned long mode, struct typec_altmode *alt) { - int ret =3D cros_typec_get_mux_state(mode, alt); + unsigned long end; + u32 event_mask; + u8 mux_state; + int ret; + + ret =3D cros_typec_get_mux_state(mode, alt); + if (ret < 0) + return ret; + mux_state =3D (u8)ret; =20 + /* Clear any old mux set done event. */ + if (index =3D=3D 0) + event_mask =3D PD_STATUS_EVENT_MUX_0_SET_DONE; + else + event_mask =3D PD_STATUS_EVENT_MUX_1_SET_DONE; + + ret =3D cros_typec_send_clear_event(sdata, port_num, event_mask); + if (ret < 0) + return ret; + + /* Send the set command. */ + ret =3D cros_typec_cmd_mux_set(sdata, port_num, index, mux_state); if (ret < 0) return ret; =20 - return cros_typec_cmd_mux_set(sdata, port_num, index, (u8)ret); + /* Check for the mux set done event. */ + end =3D jiffies + msecs_to_jiffies(1000); + do { + if (cros_typec_check_event(sdata, port_num, event_mask)) + return 0; + + usleep_range(500, 1000); + } while (time_before(jiffies, end)); + + dev_err(sdata->dev, "Timed out waiting for mux set done on index: %d, sta= te: %d\n", + index, mux_state); + + return -ETIMEDOUT; } =20 static int cros_typec_retimer_set(struct typec_retimer *retimer, struct ty= pec_retimer_state *state) --=20 2.37.1.595.g718a3a8f04-goog From nobody Sat Apr 11 06:32:07 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9A30DC00140 for ; Mon, 15 Aug 2022 06:46:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240926AbiHOGqB (ORCPT ); Mon, 15 Aug 2022 02:46:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48782 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240921AbiHOGp5 (ORCPT ); Mon, 15 Aug 2022 02:45:57 -0400 Received: from mail-pg1-x533.google.com (mail-pg1-x533.google.com [IPv6:2607:f8b0:4864:20::533]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0560312744 for ; Sun, 14 Aug 2022 23:45:56 -0700 (PDT) Received: by mail-pg1-x533.google.com with SMTP id q16so5831490pgq.6 for ; Sun, 14 Aug 2022 23:45:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=gDBcg0wiSt3vt58MkrYOdJVnzrhs/iuSr5KaWkfmmJs=; b=Rpg2cHfn9geuKVw2PWXcGPrGGPdoOcCuc2mzQtFYXHUc1NFqJoHD+Q65LeIDlTAkZh Ho+BCTnrV1FW7s+DXLxQ86XaSgG7uTc0Kbtduz27bdUQ1Z+6tQ/JEgkYxGBgyePQESfo VyQ4VUkp78/Jr5UqUfUJ2o7oIlrxzC6oSoZeY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=gDBcg0wiSt3vt58MkrYOdJVnzrhs/iuSr5KaWkfmmJs=; b=QULnA6iIKe7z1lBB7ONReVn/0QbaS4lNrKrH1dSIKnwV/Z8+8/qlOw+CxOOuG6bU4C lLR76E2bQ7k6Phdd3uYL+buCI1lWM2eu+MC7Y5BOrpVTLBFDZMuihcVIr5q5N/4pYJfh 4zEHd+8tNekbLyPoktTeCWVY7RH1gl5Gu6iQ3Muo4lKAYCjKPg056LtY3c+TPMa7M/5s +AUmzYQTBDzWj2DDT+y/KpshVX5OHL6AoLU0LQu0cLya3OtWjJnBGJ+yV7ckhcEzgPKY MkKcV7U/MKRco3eIcObVUYaOt1H1xdrNDih7RqhapbgmJevPPfWnVuAPMErO9M2GcBvU uvnQ== X-Gm-Message-State: ACgBeo2vVtTBdk7SvqOFgvtgy6K4xZ8YCAio1RSfP9aMw6UO1yeWVFgU dWmLynaSAgD2DEQQj7Ynr7DsXvu78EgP5g== X-Google-Smtp-Source: AA6agR6+QNzJvVOPc6SO6E5AvT3N2Uy4ByBUAkDC38sn+9xFIB7EdYtQAcgRJhYAz/madR1QwA0M7w== X-Received: by 2002:a65:57c8:0:b0:41c:fa29:ae1d with SMTP id q8-20020a6557c8000000b0041cfa29ae1dmr13125889pgr.136.1660545955347; Sun, 14 Aug 2022 23:45:55 -0700 (PDT) Received: from pmalani.c.googlers.com.com (137.22.168.34.bc.googleusercontent.com. [34.168.22.137]) by smtp.gmail.com with ESMTPSA id 200-20020a6214d1000000b0052db82ad8b2sm5988233pfu.123.2022.08.14.23.45.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Aug 2022 23:45:54 -0700 (PDT) From: Prashant Malani To: linux-kernel@vger.kernel.org, chrome-platform@lists.linux.dev Cc: bleung@chromium.org, Prashant Malani , Daisuke Nojiri , "Dustin L. Howett" , Greg Kroah-Hartman , Guenter Roeck , "Gustavo A. R. Silva" , Kees Cook , Sebastian Reichel , Tinghan Shen , Tzung-Bi Shih , Xiang wangx Subject: [PATCH v5 5/7] platform/chrome: cros_typec_switch: Register mode switches Date: Mon, 15 Aug 2022 06:34:26 +0000 Message-Id: <20220815063555.1384505-6-pmalani@chromium.org> X-Mailer: git-send-email 2.37.1.595.g718a3a8f04-goog In-Reply-To: <20220815063555.1384505-1-pmalani@chromium.org> References: <20220815063555.1384505-1-pmalani@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Register mode switch devices for Type C connectors, when they are specified by firmware. These control Type C configuration for any USB Type-C mode switches (sometimes known as "muxes") which are controlled by the Chrome EC. Signed-off-by: Prashant Malani --- Changes since v4: - No changes. Changes since v3: - No changes. Changes since v2: - Fixed missing "static" identifier. Changes since v1: - No changes. drivers/platform/chrome/cros_typec_switch.c | 40 +++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/drivers/platform/chrome/cros_typec_switch.c b/drivers/platform= /chrome/cros_typec_switch.c index a9e114391321..9eb37b3b754f 100644 --- a/drivers/platform/chrome/cros_typec_switch.c +++ b/drivers/platform/chrome/cros_typec_switch.c @@ -15,6 +15,7 @@ #include #include #include +#include #include =20 #define DRV_NAME "cros-typec-switch" @@ -22,6 +23,7 @@ /* Handles and other relevant data required for each port's switches. */ struct cros_typec_port { int port_num; + struct typec_mux_dev *mode_switch; struct typec_retimer *retimer; struct cros_typec_switch_data *sdata; }; @@ -147,6 +149,15 @@ static int cros_typec_configure_mux(struct cros_typec_= switch_data *sdata, int po return -ETIMEDOUT; } =20 +static int cros_typec_mode_switch_set(struct typec_mux_dev *mode_switch, + struct typec_mux_state *state) +{ + struct cros_typec_port *port =3D typec_mux_get_drvdata(mode_switch); + + /* Mode switches have index 0. */ + return cros_typec_configure_mux(port->sdata, port->port_num, 0, state->mo= de, state->alt); +} + static int cros_typec_retimer_set(struct typec_retimer *retimer, struct ty= pec_retimer_state *state) { struct cros_typec_port *port =3D typec_retimer_get_drvdata(retimer); @@ -163,9 +174,27 @@ static void cros_typec_unregister_switches(struct cros= _typec_switch_data *sdata) if (!sdata->ports[i]) continue; typec_retimer_unregister(sdata->ports[i]->retimer); + typec_mux_unregister(sdata->ports[i]->mode_switch); } } =20 +static int cros_typec_register_mode_switch(struct cros_typec_port *port, + struct fwnode_handle *fwnode) +{ + struct typec_mux_desc mode_switch_desc =3D { + .fwnode =3D fwnode, + .drvdata =3D port, + .name =3D fwnode_get_name(fwnode), + .set =3D cros_typec_mode_switch_set, + }; + + port->mode_switch =3D typec_mux_register(port->sdata->dev, &mode_switch_d= esc); + if (IS_ERR(port->mode_switch)) + return PTR_ERR(port->mode_switch); + + return 0; +} + static int cros_typec_register_retimer(struct cros_typec_port *port, struc= t fwnode_handle *fwnode) { struct typec_retimer_desc retimer_desc =3D { @@ -235,6 +264,17 @@ static int cros_typec_register_switches(struct cros_ty= pec_switch_data *sdata) } =20 dev_dbg(dev, "Retimer switch registered for index %llu\n", index); + + if (!fwnode_property_read_bool(fwnode, "mode-switch")) + continue; + + ret =3D cros_typec_register_mode_switch(port, fwnode); + if (ret) { + dev_err(dev, "Mode switch register failed\n"); + goto err_switch; + } + + dev_dbg(dev, "Mode switch registered for index %llu\n", index); } =20 return 0; --=20 2.37.1.595.g718a3a8f04-goog From nobody Sat Apr 11 06:32:07 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E8F8CC00140 for ; Mon, 15 Aug 2022 06:46:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240960AbiHOGqy (ORCPT ); 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[34.168.22.137]) by smtp.gmail.com with ESMTPSA id 200-20020a6214d1000000b0052db82ad8b2sm5988233pfu.123.2022.08.14.23.46.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Aug 2022 23:46:49 -0700 (PDT) From: Prashant Malani To: linux-kernel@vger.kernel.org, chrome-platform@lists.linux.dev Cc: bleung@chromium.org, Prashant Malani , Daisuke Nojiri , "Dustin L. Howett" , Greg Kroah-Hartman , Guenter Roeck , "Gustavo A. R. Silva" , Kees Cook , Tinghan Shen , Tzung-Bi Shih , Xiang wangx Subject: [PATCH v5 6/7] platform/chrome: cros_ec_typec: Cleanup switch handle return paths Date: Mon, 15 Aug 2022 06:34:28 +0000 Message-Id: <20220815063555.1384505-7-pmalani@chromium.org> X-Mailer: git-send-email 2.37.1.595.g718a3a8f04-goog In-Reply-To: <20220815063555.1384505-1-pmalani@chromium.org> References: <20220815063555.1384505-1-pmalani@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Some of the return paths for the cros_typec_get_switch_handles() aren't necessary. Clean up the return paths to only undo the handle get's which succeeded. Signed-off-by: Prashant Malani Reviewed-by: Tzung-Bi Shih --- Changes since v4: - No changes. Changes since v3: - No changes. Changes since v2: - No changes. Changes since v1: - No changes. drivers/platform/chrome/cros_ec_typec.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/platform/chrome/cros_ec_typec.c b/drivers/platform/chr= ome/cros_ec_typec.c index de6ee0f926a6..ee54add992db 100644 --- a/drivers/platform/chrome/cros_ec_typec.c +++ b/drivers/platform/chrome/cros_ec_typec.c @@ -158,12 +158,10 @@ static int cros_typec_get_switch_handles(struct cros_= typec_port *port, return 0; =20 role_sw_err: - usb_role_switch_put(port->role_sw); -ori_sw_err: typec_switch_put(port->ori_sw); -mux_err: +ori_sw_err: typec_mux_put(port->mux); - +mux_err: return -ENODEV; } =20 --=20 2.37.1.595.g718a3a8f04-goog From nobody Sat Apr 11 06:32:07 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1764FC00140 for ; Mon, 15 Aug 2022 06:48:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241002AbiHOGsW (ORCPT ); Mon, 15 Aug 2022 02:48:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50484 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231261AbiHOGsV (ORCPT ); Mon, 15 Aug 2022 02:48:21 -0400 Received: from mail-pl1-x62e.google.com (mail-pl1-x62e.google.com [IPv6:2607:f8b0:4864:20::62e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CE6791B79C for ; Sun, 14 Aug 2022 23:48:19 -0700 (PDT) Received: by mail-pl1-x62e.google.com with SMTP id w14so5651262plp.9 for ; Sun, 14 Aug 2022 23:48:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=r7FHO3XSuRcskZp9JaJ6GVlL/Z/2G05O5vC3OEP7QDc=; b=Skn62wd5hBqRH3K5HWiW94KGZmlsT3eBTTRKk3eQNYRMDJJhQh+HkXW5WcHd2TWd5Y you7kkNVhWXzXmMj5OLpOIPadbrrf4+C2XabfCPLnyo/LNh/LlahIpWUZaXvIZdxkoDu lo5RwLnwtZ0ySIWZPxsDd89uehq21KSiaxj+w= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=r7FHO3XSuRcskZp9JaJ6GVlL/Z/2G05O5vC3OEP7QDc=; b=vBGsDqli10iSlImaxms9i84QD0K6ICtNswMKFrm6N+2rR9PjNy0vZJfX9m4MLZ/fmk DRourUzSLxMI/VhXkJq9gOBWqfrsBoTYvm0H3Iqf6nHNzzmQns9sEN557zdYwaFGUtKE tNBjT+c2UHHmOg6b4y7SUnBtuNIGG2nO2l9pY0nOAYulV0/vbzi3iInmwP+Lo8RrWD5D BwLJO4uqhLnGyft+MNGsx//qtdCXbEQhlFSq7xfmlh4tp2rprLzU0V4j4VFcMCxsOXRj bTzMukJ4g+HirEllmF3Il0aDSvg7Q3wdgOcNWFmVCH/eevrp6rAztwpqg44kKs+oIWJ/ Zcpg== X-Gm-Message-State: ACgBeo1IW8iHClQPjLZP9/FgIvmKT+ulFHvSVyB7fBSrCC9/hJzs2mFm qCtphK2vi/T2m7FgBhIx221Af0rrSXT6IA== X-Google-Smtp-Source: AA6agR5fy9u+V+Zan5Q6cd+Rp1a+74ywHxOVM8U2haZGSKhWMngCa/oPeFKR/lJ+uXJRZ0dAliu8Bw== X-Received: by 2002:a17:90b:4ccb:b0:1f5:20b4:fc9e with SMTP id nd11-20020a17090b4ccb00b001f520b4fc9emr17006992pjb.69.1660546099182; Sun, 14 Aug 2022 23:48:19 -0700 (PDT) Received: from pmalani.c.googlers.com.com (137.22.168.34.bc.googleusercontent.com. [34.168.22.137]) by smtp.gmail.com with ESMTPSA id 200-20020a6214d1000000b0052db82ad8b2sm5988233pfu.123.2022.08.14.23.48.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Aug 2022 23:48:18 -0700 (PDT) From: Prashant Malani To: linux-kernel@vger.kernel.org, chrome-platform@lists.linux.dev Cc: bleung@chromium.org, Prashant Malani , Daisuke Nojiri , "Dustin L. Howett" , Greg Kroah-Hartman , Guenter Roeck , "Gustavo A. R. Silva" , Kees Cook , Tinghan Shen , Tzung-Bi Shih , Xiang wangx Subject: [PATCH v5 7/7] platform/chrome: cros_ec_typec: Get retimer handle Date: Mon, 15 Aug 2022 06:34:30 +0000 Message-Id: <20220815063555.1384505-8-pmalani@chromium.org> X-Mailer: git-send-email 2.37.1.595.g718a3a8f04-goog In-Reply-To: <20220815063555.1384505-1-pmalani@chromium.org> References: <20220815063555.1384505-1-pmalani@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Where available, obtain the handle to retimer switch specified via firmware, and update the mux configuration callsites to add retimer support for supported modes. Signed-off-by: Prashant Malani Reviewed-by: Tzung-Bi Shih --- Changes since v4: - No changes. Changes since v3: - No changes. Changes since v2: - No changes. Changes since v1: - No changes. drivers/platform/chrome/cros_ec_typec.c | 44 +++++++++++++++++++++++-- 1 file changed, 41 insertions(+), 3 deletions(-) diff --git a/drivers/platform/chrome/cros_ec_typec.c b/drivers/platform/chr= ome/cros_ec_typec.c index ee54add992db..a1f804ba9dca 100644 --- a/drivers/platform/chrome/cros_ec_typec.c +++ b/drivers/platform/chrome/cros_ec_typec.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include =20 @@ -55,6 +56,7 @@ struct cros_typec_port { struct usb_pd_identity c_identity; struct typec_switch *ori_sw; struct typec_mux *mux; + struct typec_retimer *retimer; struct usb_role_switch *role_sw; =20 /* Variables keeping track of switch state. */ @@ -143,6 +145,12 @@ static int cros_typec_get_switch_handles(struct cros_t= ypec_port *port, goto mux_err; } =20 + port->retimer =3D fwnode_typec_retimer_get(fwnode); + if (IS_ERR(port->retimer)) { + dev_dbg(dev, "Retimer handle not found.\n"); + goto retimer_sw_err; + } + port->ori_sw =3D fwnode_typec_switch_get(fwnode); if (IS_ERR(port->ori_sw)) { dev_dbg(dev, "Orientation switch handle not found.\n"); @@ -160,6 +168,8 @@ static int cros_typec_get_switch_handles(struct cros_ty= pec_port *port, role_sw_err: typec_switch_put(port->ori_sw); ori_sw_err: + typec_retimer_put(port->retimer); +retimer_sw_err: typec_mux_put(port->mux); mux_err: return -ENODEV; @@ -204,6 +214,21 @@ static void cros_typec_unregister_altmodes(struct cros= _typec_data *typec, int po } } =20 +/* + * Map the Type-C Mux state to retimer state and call the retimer set func= tion. We need this + * because we re-use the Type-C mux state for retimers. + */ +static int cros_typec_retimer_set(struct typec_retimer *retimer, struct t= ypec_mux_state state) +{ + struct typec_retimer_state rstate =3D { + .alt =3D state.alt, + .mode =3D state.mode, + .data =3D state.data, + }; + + return typec_retimer_set(retimer, &rstate); +} + static int cros_typec_usb_disconnect_state(struct cros_typec_port *port) { port->state.alt =3D NULL; @@ -212,6 +237,7 @@ static int cros_typec_usb_disconnect_state(struct cros_= typec_port *port) =20 usb_role_switch_set_role(port->role_sw, USB_ROLE_NONE); typec_switch_set(port->ori_sw, TYPEC_ORIENTATION_NONE); + cros_typec_retimer_set(port->retimer, port->state); =20 return typec_mux_set(port->mux, &port->state); } @@ -409,9 +435,14 @@ static int cros_typec_init_ports(struct cros_typec_dat= a *typec) =20 static int cros_typec_usb_safe_state(struct cros_typec_port *port) { + int ret; port->state.mode =3D TYPEC_STATE_SAFE; =20 - return typec_mux_set(port->mux, &port->state); + ret =3D cros_typec_retimer_set(port->retimer, port->state); + if (!ret) + ret =3D typec_mux_set(port->mux, &port->state); + + return ret; } =20 /* @@ -508,7 +539,11 @@ static int cros_typec_enable_dp(struct cros_typec_data= *typec, port->state.data =3D &dp_data; port->state.mode =3D TYPEC_MODAL_STATE(ffs(pd_ctrl->dp_mode)); =20 - return typec_mux_set(port->mux, &port->state); + ret =3D cros_typec_retimer_set(port->retimer, port->state); + if (!ret) + ret =3D typec_mux_set(port->mux, &port->state); + + return ret; } =20 static int cros_typec_enable_usb4(struct cros_typec_data *typec, @@ -597,7 +632,10 @@ static int cros_typec_configure_mux(struct cros_typec_= data *typec, int port_num, } else if (port->mux_flags & USB_PD_MUX_USB_ENABLED) { port->state.alt =3D NULL; port->state.mode =3D TYPEC_STATE_USB; - ret =3D typec_mux_set(port->mux, &port->state); + + ret =3D cros_typec_retimer_set(port->retimer, port->state); + if (!ret) + ret =3D typec_mux_set(port->mux, &port->state); } else { dev_dbg(typec->dev, "Unrecognized mode requested, mux flags: %x\n", --=20 2.37.1.595.g718a3a8f04-goog