From nobody Sat Apr 11 06:31:24 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 05708C00140 for ; Mon, 15 Aug 2022 05:08:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230188AbiHOFI1 (ORCPT ); Mon, 15 Aug 2022 01:08:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50096 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229912AbiHOFIX (ORCPT ); Mon, 15 Aug 2022 01:08:23 -0400 Received: from wout1-smtp.messagingengine.com (wout1-smtp.messagingengine.com [64.147.123.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C23C913FB8; Sun, 14 Aug 2022 22:08:22 -0700 (PDT) Received: from compute5.internal (compute5.nyi.internal [10.202.2.45]) by mailout.west.internal (Postfix) with ESMTP id 463CC32000F9; Mon, 15 Aug 2022 01:08:21 -0400 (EDT) Received: from mailfrontend1 ([10.202.2.162]) by compute5.internal (MEProxy); Mon, 15 Aug 2022 01:08:22 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sholland.org; h= cc:cc:content-transfer-encoding:date:date:from:from:in-reply-to :in-reply-to:message-id:mime-version:references:reply-to:sender :subject:subject:to:to; s=fm2; t=1660540100; x=1660626500; bh=82 aHbrLCSoT5U9kGABruP9x0FLrrxpsyk9rS6RQN/R4=; b=Is1nximSTVadIwS9Lx /ecE+EeEWF7G749+VQ8a+08/9suOTuMBm0M5ykij/IRS40pqjKD0NJCjy4BJgIWQ SggC1eCba4rTMoGViX+7lh2XKteJN2UsWTyR8okwd2DN1lVD8iDkZyXLuWNfP3Bg HA0gvt7hlreefRuPqn0FsfVi6vwbeEV/MKB6c1ozvDrk2qWLciZd/W+tzyPMbKuG pLhFD97bz0/q1oFz0Jt78mydf/ru5oui4THLkvglWY1qECyjK5wbYtz64dgzOqp/ yIUChmTbeO5EIg9HPBmuFX5VD7K0JbvkshMlNHZInj+VECzlNQAtGPX01W+u2IUf 2EJg== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding:date:date :feedback-id:feedback-id:from:from:in-reply-to:in-reply-to :message-id:mime-version:references:reply-to:sender:subject :subject:to:to:x-me-proxy:x-me-proxy:x-me-sender:x-me-sender :x-sasl-enc; s=fm1; t=1660540100; x=1660626500; bh=82aHbrLCSoT5U 9kGABruP9x0FLrrxpsyk9rS6RQN/R4=; b=HaF1KphRmbMy0fp8Ltfq7b2n7mKLo WfhnzesoiIY6MIeM4XwPUCJbop11SiJ03Podax6FfyCj8OoZnqP1SbO6pJ/DziGY aloS+2p05nW4uDkmjmWvumzzcNWhW9rD3hNRQWr1dLMsysXQ6OyF1m4dqYjZAI5K RJAvyXKR71etuYaslaer9OCZuyiHjPv34clnUGJLpTTzkLl2a5k1CKxt6M3Vibjz xEa7plxvBJOVoLSHhu8mpg8arslKepVgdI400TewgK+Q4kDksyvHDJhKbPjZ2tf/ cjN8URv+cXwwY3sBq7HCJmhKIHtONCtSTRb83F+nqVXx7ZrA8lmIcWA7A== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvfedrvdehuddgleehucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmne cujfgurhephffvvefufffkofgjfhgggfestdekredtredttdenucfhrhhomhepufgrmhhu vghlucfjohhllhgrnhguuceoshgrmhhuvghlsehshhholhhlrghnugdrohhrgheqnecugg ftrfgrthhtvghrnhepudekteeuudehtdelteevgfduvddvjefhfedulefgudevgeeghefg udefiedtveetnecuvehluhhsthgvrhfuihiivgeptdenucfrrghrrghmpehmrghilhhfrh homhepshgrmhhuvghlsehshhholhhlrghnugdrohhrgh X-ME-Proxy: Feedback-ID: i0ad843c9:Fastmail Received: by mail.messagingengine.com (Postfix) with ESMTPA; Mon, 15 Aug 2022 01:08:20 -0400 (EDT) From: Samuel Holland To: Chen-Yu Tsai , Jernej Skrabec , linux-sunxi@lists.linux.dev, Palmer Dabbelt , Paul Walmsley , Albert Ou , linux-riscv@lists.infradead.org Cc: Rob Herring , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Samuel Holland Subject: [PATCH 01/12] MAINTAINERS: Match the sun20i family of Allwinner SoCs Date: Mon, 15 Aug 2022 00:08:04 -0500 Message-Id: <20220815050815.22340-2-samuel@sholland.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220815050815.22340-1-samuel@sholland.org> References: <20220815050815.22340-1-samuel@sholland.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Allwinner sunxi SoCs with a RISC-V CPU use the sun20i designator. Match that pattern in addition to the designators for 32 and 64-bit ARM SoCs. Signed-off-by: Samuel Holland Reviewed-by: Heiko Stuebner --- MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index 8a5012ba6ff9..59bcaa405a6f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1800,7 +1800,7 @@ F: drivers/pinctrl/sunxi/ F: drivers/soc/sunxi/ N: allwinner N: sun[x456789]i -N: sun50i +N: sun[25]0i =20 ARM/Amlogic Meson SoC CLOCK FRAMEWORK M: Neil Armstrong --=20 2.35.1 From nobody Sat Apr 11 06:31:24 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CE893C25B0D for ; Mon, 15 Aug 2022 05:08:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229751AbiHOFId (ORCPT ); Mon, 15 Aug 2022 01:08:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50152 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230129AbiHOFI0 (ORCPT ); Mon, 15 Aug 2022 01:08:26 -0400 Received: from wout1-smtp.messagingengine.com (wout1-smtp.messagingengine.com [64.147.123.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B4DEF140FE; Sun, 14 Aug 2022 22:08:25 -0700 (PDT) Received: from compute3.internal (compute3.nyi.internal [10.202.2.43]) by mailout.west.internal (Postfix) with ESMTP id 2F79232004AE; Mon, 15 Aug 2022 01:08:24 -0400 (EDT) Received: from mailfrontend1 ([10.202.2.162]) by compute3.internal (MEProxy); Mon, 15 Aug 2022 01:08:25 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sholland.org; h= cc:cc:content-transfer-encoding:date:date:from:from:in-reply-to :in-reply-to:message-id:mime-version:references:reply-to:sender :subject:subject:to:to; s=fm2; t=1660540103; x=1660626503; bh=29 uAAq1TVY/O7ZEUaRe+3LcWY61wpaNsGqYURHUMEAQ=; b=Lv40otdXtr3OwindnT WjgvPehS8V6WPGFcblD/hR1waOQkqGMjINtWzTvfMc9n79ZAG2e8+RN0+L3rgPTj l/7hKUTjvkzNtdB1XFtc1eUgKTTecpVco3fZ/RYsB1P5m88BRDNxPoFuzqim+3D7 pf0eLDvwd5x9OC3PFPOHjYVR7XLyP69P3HHEUKgxAQwXp493L7cfUqqEl21gN9qx zp0BT269U1qhmj/3s9Pc6HhJC0ONNyj0QvYpyGkLLuQRQt2pwslDX7KgfmSWflhK pKmRPqyoaO3k//oYYrXO0ZW5zMRF4NM8Wdpe+QTj9VRW3ImjFnZBlirb7zSkFM7Y swtQ== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding:date:date :feedback-id:feedback-id:from:from:in-reply-to:in-reply-to :message-id:mime-version:references:reply-to:sender:subject :subject:to:to:x-me-proxy:x-me-proxy:x-me-sender:x-me-sender :x-sasl-enc; s=fm1; t=1660540103; x=1660626503; bh=29uAAq1TVY/O7 ZEUaRe+3LcWY61wpaNsGqYURHUMEAQ=; b=QE0kSkO9TDbjd71LqM6FjE1EYAG82 eyJNBrE6n0W3mOl1qwtdGRa+GsK6dreQ0ydKJNijL8TS4mSkA+d8KCQ/Tqe9FDnU a1K/Bs0LMG9BbcuJDFMygPaMjk+btMra8wcQKkLLKP5lHe5GZY7TVOb9GAlvvVRr 9YnKA/HP+BkVKXeMGlRgSPf99I0qEXXOlRN+efuuTy/+ctdx+kMEmP8U+ibxlliP tECM8hvYyG5l8iWonuWSWgMlsNa99Upe4oMWndA/26eAXc8qtmDyjIk4gQHN6IuV 13+wHLL6y10Y5bUxz3EI1L9ttQGLft5g30VPBetqS44H3Taj4DLyIiqaQ== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvfedrvdehuddgleehucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmne cujfgurhephffvvefufffkofgjfhgggfestdekredtredttdenucfhrhhomhepufgrmhhu vghlucfjohhllhgrnhguuceoshgrmhhuvghlsehshhholhhlrghnugdrohhrgheqnecugg ftrfgrthhtvghrnhepudekteeuudehtdelteevgfduvddvjefhfedulefgudevgeeghefg udefiedtveetnecuvehluhhsthgvrhfuihiivgeptdenucfrrghrrghmpehmrghilhhfrh homhepshgrmhhuvghlsehshhholhhlrghnugdrohhrgh X-ME-Proxy: Feedback-ID: i0ad843c9:Fastmail Received: by mail.messagingengine.com (Postfix) with ESMTPA; Mon, 15 Aug 2022 01:08:22 -0400 (EDT) From: Samuel Holland To: Chen-Yu Tsai , Jernej Skrabec , linux-sunxi@lists.linux.dev, Palmer Dabbelt , Paul Walmsley , Albert Ou , linux-riscv@lists.infradead.org Cc: Rob Herring , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Samuel Holland Subject: [PATCH 02/12] dt-bindings: riscv: Add T-HEAD C906 and C910 compatibles Date: Mon, 15 Aug 2022 00:08:05 -0500 Message-Id: <20220815050815.22340-3-samuel@sholland.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220815050815.22340-1-samuel@sholland.org> References: <20220815050815.22340-1-samuel@sholland.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The C906 and C910 are RISC-V CPU cores from T-HEAD Semiconductor. Notably, the C906 core is used in the Allwinner D1 SoC. Signed-off-by: Samuel Holland Acked-by: Rob Herring Reviewed-by: Heiko Stuebner --- Documentation/devicetree/bindings/riscv/cpus.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentat= ion/devicetree/bindings/riscv/cpus.yaml index 873dd12f6e89..ce2161d9115a 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -38,6 +38,8 @@ properties: - sifive,u5 - sifive,u7 - canaan,k210 + - thead,c906 + - thead,c910 - const: riscv - items: - enum: --=20 2.35.1 From nobody Sat Apr 11 06:31:24 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9F7BBC3F6B0 for ; Mon, 15 Aug 2022 05:08:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230326AbiHOFIi (ORCPT ); Mon, 15 Aug 2022 01:08:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50268 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229527AbiHOFI3 (ORCPT ); Mon, 15 Aug 2022 01:08:29 -0400 Received: from wout1-smtp.messagingengine.com (wout1-smtp.messagingengine.com [64.147.123.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8FFD5140FA; Sun, 14 Aug 2022 22:08:28 -0700 (PDT) Received: from compute3.internal (compute3.nyi.internal [10.202.2.43]) by mailout.west.internal (Postfix) with ESMTP id E802632000F9; Mon, 15 Aug 2022 01:08:26 -0400 (EDT) Received: from mailfrontend1 ([10.202.2.162]) by compute3.internal (MEProxy); Mon, 15 Aug 2022 01:08:28 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sholland.org; h= cc:cc:content-transfer-encoding:date:date:from:from:in-reply-to :in-reply-to:message-id:mime-version:references:reply-to:sender :subject:subject:to:to; s=fm2; t=1660540106; x=1660626506; bh=1b 8wvlOIqq08dzssrbjKws+JgmGzBWVPDh4Dm1RTFCU=; b=jWF0lvKSrnMxYNz01X 1WCXUHnk3Xx7veBUORmXijOreUbQeBMioHxw1iCFYTS9Dpj9XCnCghsIOmQYKE4c 7qKDJCtrE2M4Da0XxiGjL/cDVV5/f7vNCbTkUT6xLIY9ZA30wrLXMWLf81sJb6+q LJkn5xhph/bdZmkC2lbgN8/OuXAwfaqZbxGnprsIuQmrKT4EfzIstjiXg1PBLXYJ ZBd5jG4ZIBJmp9WLEG4a+buj4295tsOc3nLQHRtTT9+SXCl8vbkOwttSmuGyO5wE 1xuTQYEnJVZZs/ixtDkqPOEvz8xVOkUAU4DRXWLFjSQhYI+qqvtUR/adqav5pLNi 5qzQ== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding:date:date :feedback-id:feedback-id:from:from:in-reply-to:in-reply-to :message-id:mime-version:references:reply-to:sender:subject :subject:to:to:x-me-proxy:x-me-proxy:x-me-sender:x-me-sender :x-sasl-enc; s=fm1; t=1660540106; x=1660626506; bh=1b8wvlOIqq08d zssrbjKws+JgmGzBWVPDh4Dm1RTFCU=; b=DhBNH1UDadbs/vc2awR003MB7DSL3 j7PgSENLFy+gg4XtsE9Tk1uxiFtjhYTpnwsBmhOht5i0HRu97L0qbC7o76RH83c0 Eaa3Zg8JoS0hXxAbtLcbUzuW35oNccb3BRymKKZwp4hgzErSdTCmuCgqFT6+q3Vg qOVeB7K/wPkEyLL76gYA+931QMuOp+PV29rroAjojGposxO/SwqRBdnlO9enLyKG IEayl1qUMcUwVPm5Le36RAuQY3ZbefiRnau5uFfnm+IX75lu14AsygJKGF1vF80V ziHDC2okA2Tpk21pKcRdESc7atcutvfOuKIhfw2+h3DoGzp7IP1YVnNpw== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvfedrvdehuddgleehucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmne gfrhhlucfvnfffucdluddtmdenogevohgrshhtrghlqdfhgeduvddqtddvucdludehtddm necujfgurhephffvvefufffkofgjfhgggfestdekredtredttdenucfhrhhomhepufgrmh huvghlucfjohhllhgrnhguuceoshgrmhhuvghlsehshhholhhlrghnugdrohhrgheqnecu ggftrfgrthhtvghrnhepleevtddvvdevieekieffjefggfeuieetieelveelhfeukeejvd dvgfeiveekleefnecuffhomhgrihhnpegtlhhotghkfihorhhkphhirdgtohhmpdhmrghn ghhophhirdgttgenucevlhhushhtvghrufhiiigvpedtnecurfgrrhgrmhepmhgrihhlfh hrohhmpehsrghmuhgvlhesshhhohhllhgrnhgurdhorhhg X-ME-Proxy: Feedback-ID: i0ad843c9:Fastmail Received: by mail.messagingengine.com (Postfix) with ESMTPA; Mon, 15 Aug 2022 01:08:25 -0400 (EDT) From: Samuel Holland To: Chen-Yu Tsai , Jernej Skrabec , linux-sunxi@lists.linux.dev, Palmer Dabbelt , Paul Walmsley , Albert Ou , linux-riscv@lists.infradead.org Cc: Rob Herring , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Samuel Holland Subject: [PATCH 03/12] dt-bindings: vendor-prefixes: Add Allwinner D1 board vendors Date: Mon, 15 Aug 2022 00:08:06 -0500 Message-Id: <20220815050815.22340-4-samuel@sholland.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220815050815.22340-1-samuel@sholland.org> References: <20220815050815.22340-1-samuel@sholland.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Some boards using the Allwinner D1 SoC are made by vendors not previously documented. Clockwork Tech LLC (https://www.clockworkpi.com/) manufactures the ClockworkPi and DevTerm boards. Beijing Widora Technology Co., Ltd. (https://mangopi.cc/) manufactures the MangoPi family of boards. Signed-off-by: Samuel Holland Acked-by: Rob Herring Reviewed-by: Heiko Stuebner --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Docum= entation/devicetree/bindings/vendor-prefixes.yaml index 2f0151e9f6be..52d076ab6c48 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -258,6 +258,8 @@ patternProperties: description: Cirrus Logic, Inc. "^cisco,.*": description: Cisco Systems, Inc. + "^clockwork,.*": + description: Clockwork Tech LLC "^cloudengines,.*": description: Cloud Engines, Inc. "^cnm,.*": @@ -1412,6 +1414,8 @@ patternProperties: description: Shenzhen whwave Electronics, Inc. "^wi2wi,.*": description: Wi2Wi, Inc. + "^widora,.*": + description: Beijing Widora Technology Co., Ltd. "^wiligear,.*": description: Wiligear, Ltd. "^willsemi,.*": --=20 2.35.1 From nobody Sat Apr 11 06:31:24 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BFC6FC25B0E for ; Mon, 15 Aug 2022 05:08:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232588AbiHOFIj (ORCPT ); Mon, 15 Aug 2022 01:08:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50378 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230214AbiHOFIc (ORCPT ); Mon, 15 Aug 2022 01:08:32 -0400 Received: from wout1-smtp.messagingengine.com (wout1-smtp.messagingengine.com [64.147.123.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 65A4E15724; Sun, 14 Aug 2022 22:08:31 -0700 (PDT) Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.west.internal (Postfix) with ESMTP id B248A320077A; Mon, 15 Aug 2022 01:08:29 -0400 (EDT) Received: from mailfrontend1 ([10.202.2.162]) by compute4.internal (MEProxy); Mon, 15 Aug 2022 01:08:30 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sholland.org; h= cc:cc:content-transfer-encoding:date:date:from:from:in-reply-to :in-reply-to:message-id:mime-version:references:reply-to:sender :subject:subject:to:to; s=fm2; t=1660540109; x=1660626509; bh=VC iO+1/7gvQvfqsvEh3J7OZy4FYDY6eHNsrcKm6S1VI=; b=NVQX3Q3w3uHTAPcC7W NPtExPv1e1twycdJUHl7SiOQfBvifOvS8dSv9N9D2VYa3xyeikcPnFmzwHW0r6Ep ueZOmNkizyiRg7sXLb9hj7ENf50oX6MCq7GXErvM3s5n5CEv9HlJtylC9uCa8vL0 +gZThwQM448diXT9HufTtvkzYmdzUf8GTR4ABxBEy4PNGZl0ky+ID4nljjKBNQzn w2H0k5GPcldUTLnBp5SkD90RCdLvxgRDYVgn0T4sOgvKEfx9T0ju5OLc3ensTtUT AIEUQI6k98LtsWJFa9JJ/lg9sZ9mB/9ng78+ux3q0qipJNRPDLWtbrBDxhI/rD2+ oeCQ== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding:date:date :feedback-id:feedback-id:from:from:in-reply-to:in-reply-to :message-id:mime-version:references:reply-to:sender:subject :subject:to:to:x-me-proxy:x-me-proxy:x-me-sender:x-me-sender :x-sasl-enc; s=fm1; t=1660540109; x=1660626509; bh=VCiO+1/7gvQvf qsvEh3J7OZy4FYDY6eHNsrcKm6S1VI=; b=OFR9ujqQn+kqfkjG9hhYbNG3hnjeI gfrEqTzTjDoBYPWAJsCmXY00l5DniVL/l7xOeQSNSqTz7J1lsP4s5nmjJg4uweVe u0hveejBPAC+NqLz37k8uO2LOPZKhGTsbfsG/120O4bPJg7iVQ+1ZyLVDO/bZ7Cs vm+UhEfnidPSLaq4WeKNHV1ngApWCGZgI8ZkIFcdCdhJDGgxao7HRtlNho8aDfmG NhDwnI7USFgh6vS9tPt6Ce77H9/uD0hWZtQ+4+3lsgj8vn42babyXn/Mb1cJTqds 6hR7ro878HfrRp8Gh+RRLLpWJQY4FoCnn5SUM5enOues7lyl3vkVZ+6kA== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvfedrvdehuddgleehucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmne cujfgurhephffvvefufffkofgjfhgggfestdekredtredttdenucfhrhhomhepufgrmhhu vghlucfjohhllhgrnhguuceoshgrmhhuvghlsehshhholhhlrghnugdrohhrgheqnecugg ftrfgrthhtvghrnhepgffhvefhgfehjeehgfekheeuffegheffjeegheeuudeufeffhffh ueeihfeufffhnecuffhomhgrihhnpeguvghvihgtvghtrhgvvgdrohhrghenucevlhhush htvghrufhiiigvpedtnecurfgrrhgrmhepmhgrihhlfhhrohhmpehsrghmuhgvlhesshhh ohhllhgrnhgurdhorhhg X-ME-Proxy: Feedback-ID: i0ad843c9:Fastmail Received: by mail.messagingengine.com (Postfix) with ESMTPA; Mon, 15 Aug 2022 01:08:28 -0400 (EDT) From: Samuel Holland To: Chen-Yu Tsai , Jernej Skrabec , linux-sunxi@lists.linux.dev, Palmer Dabbelt , Paul Walmsley , Albert Ou , linux-riscv@lists.infradead.org Cc: Rob Herring , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Samuel Holland Subject: [PATCH 04/12] dt-bindings: riscv: Add Allwinner D1 board compatibles Date: Mon, 15 Aug 2022 00:08:07 -0500 Message-Id: <20220815050815.22340-5-samuel@sholland.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220815050815.22340-1-samuel@sholland.org> References: <20220815050815.22340-1-samuel@sholland.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Several SoMs and boards are available that feature the Allwinner D1 SoC. Document their compatible strings. Signed-off-by: Samuel Holland Acked-by: Rob Herring Reviewed-by: Heiko Stuebner Tested-by: Heiko Stuebner --- .../devicetree/bindings/riscv/sunxi.yaml | 64 +++++++++++++++++++ 1 file changed, 64 insertions(+) create mode 100644 Documentation/devicetree/bindings/riscv/sunxi.yaml diff --git a/Documentation/devicetree/bindings/riscv/sunxi.yaml b/Documenta= tion/devicetree/bindings/riscv/sunxi.yaml new file mode 100644 index 000000000000..564a89499894 --- /dev/null +++ b/Documentation/devicetree/bindings/riscv/sunxi.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/riscv/sunxi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner RISC-V SoC-based boards + +maintainers: + - Chen-Yu Tsai + - Jernej Skrabec + - Samuel Holland + +description: + Allwinner RISC-V SoC-based boards + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - description: Dongshan Nezha STU SoM + items: + - const: 100ask,dongshan-nezha-stu + - const: allwinner,sun20i-d1 + + - description: D1 Nezha board + items: + - const: allwinner,d1-nezha + - const: allwinner,sun20i-d1 + + - description: ClockworkPi R-01 SoM and v3.14 board + items: + - const: clockwork,r-01-clockworkpi-v3.14 + - const: allwinner,sun20i-d1 + + - description: ClockworkPi R-01 SoM, v3.14 board, and DevTerm expans= ion + items: + - const: clockwork,r-01-devterm-v3.14 + - const: clockwork,r-01-clockworkpi-v3.14 + - const: allwinner,sun20i-d1 + + - description: Lichee RV SoM + items: + - const: sipeed,lichee-rv + - const: allwinner,sun20i-d1 + + - description: Carrier boards for the Lichee RV SoM + items: + - enum: + - sipeed,lichee-rv-86-panel-480p + - sipeed,lichee-rv-86-panel-720p + - sipeed,lichee-rv-dock + - const: sipeed,lichee-rv + - const: allwinner,sun20i-d1 + + - description: MangoPi MQ Pro board + items: + - const: widora,mangopi-mq-pro + - const: allwinner,sun20i-d1 + +additionalProperties: true + +... --=20 2.35.1 From nobody Sat Apr 11 06:31:24 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B3538C00140 for ; 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Mon, 15 Aug 2022 01:08:31 -0400 (EDT) From: Samuel Holland To: Chen-Yu Tsai , Jernej Skrabec , linux-sunxi@lists.linux.dev, Palmer Dabbelt , Paul Walmsley , Albert Ou , linux-riscv@lists.infradead.org Cc: Rob Herring , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Samuel Holland Subject: [PATCH 05/12] riscv: Add the Allwinner SoC family Kconfig option Date: Mon, 15 Aug 2022 00:08:08 -0500 Message-Id: <20220815050815.22340-6-samuel@sholland.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220815050815.22340-1-samuel@sholland.org> References: <20220815050815.22340-1-samuel@sholland.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Allwinner manufactures the sunxi family of application processors. This includes the "sun8i" series of ARMv7 SoCs, the "sun50i" series of ARMv8 SoCs, and now the "sun20i" series of 64-bit RISC-V SoCs. The first SoC in the sun20i series is D1, containing a single T-HEAD C906 core. D1s is a low-pin-count variant of D1 with co-packaged DRAM. Most peripherals are shared across the entire chip family. In fact, the ARMv7 T113 SoC is pin-compatible and almost entirely register-compatible with the D1s. This means many existing device drivers can be reused. To facilitate this reuse, name the symbol ARCH_SUNXI, since that is what the existing drivers have as their dependency. Signed-off-by: Samuel Holland Reviewed-by: Heiko Stuebner Tested-by: Heiko Stuebner --- arch/riscv/Kconfig.socs | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index 69774bb362d6..1caacbfac1a5 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -1,5 +1,14 @@ menu "SoC selection" =20 +config ARCH_SUNXI + bool "Allwinner sun20i SoCs" + select ERRATA_THEAD if MMU && !XIP_KERNEL + select SIFIVE_PLIC + select SUN4I_TIMER + help + This enables support for Allwinner sun20i platform hardware, + including boards based on the D1 and D1s SoCs. + config SOC_MICROCHIP_POLARFIRE bool "Microchip PolarFire SoCs" select MCHP_CLK_MPFS --=20 2.35.1 From nobody Sat Apr 11 06:31:24 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 68D43C282E7 for ; Mon, 15 Aug 2022 05:09:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240588AbiHOFJI (ORCPT ); Mon, 15 Aug 2022 01:09:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50444 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233043AbiHOFIl (ORCPT ); Mon, 15 Aug 2022 01:08:41 -0400 Received: from wout1-smtp.messagingengine.com (wout1-smtp.messagingengine.com [64.147.123.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5C3C815718; Sun, 14 Aug 2022 22:08:37 -0700 (PDT) Received: from compute5.internal (compute5.nyi.internal [10.202.2.45]) by mailout.west.internal (Postfix) with ESMTP id 436183200065; Mon, 15 Aug 2022 01:08:35 -0400 (EDT) Received: from mailfrontend1 ([10.202.2.162]) by compute5.internal (MEProxy); Mon, 15 Aug 2022 01:08:36 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sholland.org; h= cc:cc:content-transfer-encoding:date:date:from:from:in-reply-to :in-reply-to:message-id:mime-version:references:reply-to:sender :subject:subject:to:to; s=fm2; t=1660540114; x=1660626514; bh=LR yhxzc9+XafRvM9niU1BPEaijXGlQspuEydv1PgoYs=; b=T9F7wPM6xRCWK46gqG NlzUbFoLwKHJb/Y9uylwIFIxxuLI1H+Fk6nLVJeHB0hUp/A4h8oOLG7p1izQux7W ZbxlaoFfskls88Y1seaaD4c4Ry9bBO08LZ+xaNOb4pXnLX2etCB9xU02G+jCoFq6 QJnwXsTTrp/5Y3NefsLHsvjdokGA79m17vZfKSgtuwSjRryQWwcCBBbS+D37v7+N wqn6dQWyMU5AuSgyDogX7tS8BjReH0iIknxfyvesjndAM54iYf98Yg2MzlbEPvqe EtnjG5INj8GsUxO5T/gzqyBUFOnrgxEs9M34rbAzbvCjaMI/l5uCjxpvJBW7hBvf T1Gw== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding:date:date :feedback-id:feedback-id:from:from:in-reply-to:in-reply-to :message-id:mime-version:references:reply-to:sender:subject :subject:to:to:x-me-proxy:x-me-proxy:x-me-sender:x-me-sender :x-sasl-enc; s=fm1; t=1660540114; x=1660626514; bh=LRyhxzc9+XafR vM9niU1BPEaijXGlQspuEydv1PgoYs=; b=vLwLcXcGwtJcjFSsWIPr4ZWl/aWru 1Q2dqiNkddzXr7WtlB9cM5HF03IoB87su1L9A8Pk90LlJBUeQ6SFsQgB6ipNq3Tr UJ6xhNbPO1JG5wlW++g5rZKcN4IAPzDacdV5vg7lBDSKxqAUL6OY8+QLa/F4CmdQ 74umtIrh9xPFZ2JTUVZnpbuOE18demD0MT4TOpmSpkcYBvuri5VLheiopzCCpgqr U8Hcs2C0D6MqD1RGe1RjLCJC+anRqU94L93FBZLfsAhlKCDPFG9PpEOhIz1hIM+v i5pfY8fyh6UQwwJZ6NlVpWPxALdTSL3n8RLpdPGM7Bo0+u+E47vA1mqpQ== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvfedrvdehuddgleehucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmne cujfgurhephffvvefufffkofgjfhgggfestdekredtredttdenucfhrhhomhepufgrmhhu vghlucfjohhllhgrnhguuceoshgrmhhuvghlsehshhholhhlrghnugdrohhrgheqnecugg ftrfgrthhtvghrnhepudekteeuudehtdelteevgfduvddvjefhfedulefgudevgeeghefg udefiedtveetnecuvehluhhsthgvrhfuihiivgepudenucfrrghrrghmpehmrghilhhfrh homhepshgrmhhuvghlsehshhholhhlrghnugdrohhrgh X-ME-Proxy: Feedback-ID: i0ad843c9:Fastmail Received: by mail.messagingengine.com (Postfix) with ESMTPA; Mon, 15 Aug 2022 01:08:34 -0400 (EDT) From: Samuel Holland To: Chen-Yu Tsai , Jernej Skrabec , linux-sunxi@lists.linux.dev, Palmer Dabbelt , Paul Walmsley , Albert Ou , linux-riscv@lists.infradead.org Cc: Rob Herring , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Samuel Holland Subject: [PATCH 06/12] riscv: dts: allwinner: Add the D1 SoC base devicetree Date: Mon, 15 Aug 2022 00:08:09 -0500 Message-Id: <20220815050815.22340-7-samuel@sholland.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220815050815.22340-1-samuel@sholland.org> References: <20220815050815.22340-1-samuel@sholland.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" D1 is a SoC containing a single-core T-HEAD Xuantie C906 CPU, as well as one HiFi 4 DSP. The SoC is based on a design that additionally contained a pair of Cortex A7's. For that reason, some peripherals are duplicated. This devicetree includes all of the peripherals that already have a documented binding. Signed-off-by: Samuel Holland Tested-by: Conor Dooley # Nezha D1 Tested-by: Heiko Stuebner --- arch/riscv/boot/dts/Makefile | 1 + arch/riscv/boot/dts/allwinner/Makefile | 1 + arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi | 900 +++++++++++++++++++ 3 files changed, 902 insertions(+) create mode 100644 arch/riscv/boot/dts/allwinner/Makefile create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile index ff174996cdfd..f292e31bdb2c 100644 --- a/arch/riscv/boot/dts/Makefile +++ b/arch/riscv/boot/dts/Makefile @@ -1,4 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 +subdir-y +=3D allwinner subdir-y +=3D sifive subdir-y +=3D starfive subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) +=3D canaan diff --git a/arch/riscv/boot/dts/allwinner/Makefile b/arch/riscv/boot/dts/a= llwinner/Makefile new file mode 100644 index 000000000000..f66554cd5c45 --- /dev/null +++ b/arch/riscv/boot/dts/allwinner/Makefile @@ -0,0 +1 @@ +# SPDX-License-Identifier: GPL-2.0 diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi b/arch/riscv/boot= /dts/allwinner/sun20i-d1.dtsi new file mode 100644 index 000000000000..d1429274f22e --- /dev/null +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi @@ -0,0 +1,900 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +// Copyright (C) 2021-2022 Samuel Holland + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/ { + #address-cells =3D <1>; + #size-cells =3D <1>; + + cpus { + timebase-frequency =3D <24000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu0: cpu@0 { + compatible =3D "thead,c906", "riscv"; + device_type =3D "cpu"; + reg =3D <0>; + clocks =3D <&ccu CLK_RISCV>; + clock-frequency =3D <24000000>; + d-cache-block-size =3D <64>; + d-cache-sets =3D <256>; + d-cache-size =3D <32768>; + i-cache-block-size =3D <64>; + i-cache-sets =3D <128>; + i-cache-size =3D <32768>; + mmu-type =3D "riscv,sv39"; + riscv,isa =3D "rv64imafdc"; + #cooling-cells =3D <2>; + + cpu0_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + }; + }; + }; + + de: display-engine { + compatible =3D "allwinner,sun20i-d1-display-engine"; + allwinner,pipelines =3D <&mixer0>, <&mixer1>; + status =3D "disabled"; + }; + + osc24M: osc24M-clk { + compatible =3D "fixed-clock"; + clock-frequency =3D <24000000>; + clock-output-names =3D "osc24M"; + #clock-cells =3D <0>; + }; + + soc { + compatible =3D "simple-bus"; + ranges; + interrupt-parent =3D <&plic>; + dma-noncoherent; + #address-cells =3D <1>; + #size-cells =3D <1>; + + dsp_wdt: watchdog@1700400 { + compatible =3D "allwinner,sun20i-d1-wdt"; + reg =3D <0x1700400 0x20>; + interrupts =3D <138 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&osc24M>, <&rtc CLK_OSC32K>; + clock-names =3D "hosc", "losc"; + status =3D "reserved"; + }; + + pio: pinctrl@2000000 { + compatible =3D "allwinner,sun20i-d1-pinctrl"; + reg =3D <0x2000000 0x800>; + interrupts =3D <85 IRQ_TYPE_LEVEL_HIGH>, + <87 IRQ_TYPE_LEVEL_HIGH>, + <89 IRQ_TYPE_LEVEL_HIGH>, + <91 IRQ_TYPE_LEVEL_HIGH>, + <93 IRQ_TYPE_LEVEL_HIGH>, + <95 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&ccu CLK_APB0>, + <&osc24M>, + <&rtc CLK_OSC32K>; + clock-names =3D "apb", "hosc", "losc"; + gpio-controller; + interrupt-controller; + #gpio-cells =3D <3>; + #interrupt-cells =3D <3>; + + /omit-if-no-ref/ + i2c0_pb10_pins: i2c0-pb10-pins { + pins =3D "PB10", "PB11"; + function =3D "i2c0"; + }; + + /omit-if-no-ref/ + i2c2_pb0_pins: i2c2-pb0-pins { + pins =3D "PB0", "PB1"; + function =3D "i2c2"; + }; + + /omit-if-no-ref/ + lcd_rgb666_pins: lcd-rgb666-pins { + pins =3D "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", + "PD6", "PD7", "PD8", "PD9", "PD10", "PD11", + "PD12", "PD13", "PD14", "PD15", "PD16", "PD17", + "PD18", "PD19", "PD20", "PD21"; + function =3D "lcd0"; + }; + + /omit-if-no-ref/ + mmc0_pins: mmc0-pins { + pins =3D "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; + function =3D "mmc0"; + }; + + /omit-if-no-ref/ + mmc1_pins: mmc1-pins { + pins =3D "PG0", "PG1", "PG2", "PG3", "PG4", "PG5"; + function =3D "mmc1"; + }; + + /omit-if-no-ref/ + mmc2_pins: mmc2-pins { + pins =3D "PC2", "PC3", "PC4", "PC5", "PC6", "PC7"; + function =3D "mmc2"; + }; + + /omit-if-no-ref/ + rgmii_pe_pins: rgmii-pe-pins { + pins =3D "PE0", "PE1", "PE2", "PE3", "PE4", + "PE5", "PE6", "PE7", "PE8", "PE9", + "PE11", "PE12", "PE13", "PE14", "PE15"; + function =3D "emac"; + }; + + /omit-if-no-ref/ + rmii_pe_pins: rmii-pe-pins { + pins =3D "PE0", "PE1", "PE2", "PE3", "PE4", + "PE5", "PE6", "PE7", "PE8", "PE9"; + function =3D "emac"; + }; + + /omit-if-no-ref/ + uart0_pb8_pins: uart0-pb8-pins { + pins =3D "PB8", "PB9"; + function =3D "uart0"; + }; + + /omit-if-no-ref/ + uart1_pg6_pins: uart1-pg6-pins { + pins =3D "PG6", "PG7"; + function =3D "uart1"; + }; + + /omit-if-no-ref/ + uart1_pg8_rts_cts_pins: uart1-pg8-rts-cts-pins { + pins =3D "PG8", "PG9"; + function =3D "uart1"; + }; + }; + + ccu: clock-controller@2001000 { + compatible =3D "allwinner,sun20i-d1-ccu"; + reg =3D <0x2001000 0x1000>; + clocks =3D <&osc24M>, + <&rtc CLK_OSC32K>, + <&rtc CLK_IOSC>; + clock-names =3D "hosc", "losc", "iosc"; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; + + lradc: keys@2009800 { + compatible =3D "allwinner,sun20i-d1-lradc", + "allwinner,sun50i-r329-lradc"; + reg =3D <0x2009800 0x400>; + interrupts =3D <77 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&ccu CLK_BUS_LRADC>; + resets =3D <&ccu RST_BUS_LRADC>; + status =3D "disabled"; + }; + + codec: audio-codec@2030000 { + compatible =3D "simple-mfd", "syscon"; + reg =3D <0x2030000 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + regulators@2030348 { + compatible =3D "allwinner,sun20i-d1-analog-ldos"; + reg =3D <0x2030348 0x4>; + nvmem-cells =3D <&bg_trim>; + nvmem-cell-names =3D "bg_trim"; + + reg_aldo: aldo { + }; + + reg_hpldo: hpldo { + }; + }; + }; + + i2s0: i2s@2032000 { + compatible =3D "allwinner,sun20i-d1-i2s", + "allwinner,sun50i-r329-i2s"; + reg =3D <0x2032000 0x1000>; + interrupts =3D <42 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&ccu CLK_BUS_I2S0>, + <&ccu CLK_I2S0>; + clock-names =3D "apb", "mod"; + resets =3D <&ccu RST_BUS_I2S0>; + dmas =3D <&dma 3>, <&dma 3>; + dma-names =3D "rx", "tx"; + status =3D "disabled"; + #sound-dai-cells =3D <0>; + }; + + i2s1: i2s@2033000 { + compatible =3D "allwinner,sun20i-d1-i2s", + "allwinner,sun50i-r329-i2s"; + reg =3D <0x2033000 0x1000>; + interrupts =3D <43 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&ccu CLK_BUS_I2S1>, + <&ccu CLK_I2S1>; + clock-names =3D "apb", "mod"; + resets =3D <&ccu RST_BUS_I2S1>; + dmas =3D <&dma 4>, <&dma 4>; + dma-names =3D "rx", "tx"; + status =3D "disabled"; + #sound-dai-cells =3D <0>; + }; + + i2s2: i2s@2034000 { + compatible =3D "allwinner,sun20i-d1-i2s", + "allwinner,sun50i-r329-i2s"; + reg =3D <0x2034000 0x1000>; + interrupts =3D <44 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&ccu CLK_BUS_I2S2>, + <&ccu CLK_I2S2>; + clock-names =3D "apb", "mod"; + resets =3D <&ccu RST_BUS_I2S2>; + dmas =3D <&dma 5>, <&dma 5>; + dma-names =3D "rx", "tx"; + status =3D "disabled"; + #sound-dai-cells =3D <0>; + }; + + timer: timer@2050000 { + compatible =3D "allwinner,sun20i-d1-timer", + "allwinner,sun8i-a23-timer"; + reg =3D <0x2050000 0xa0>; + interrupts =3D <75 IRQ_TYPE_LEVEL_HIGH>, + <76 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&osc24M>; + }; + + wdt: watchdog@20500a0 { + compatible =3D "allwinner,sun20i-d1-wdt-reset", + "allwinner,sun20i-d1-wdt"; + reg =3D <0x20500a0 0x20>; + interrupts =3D <79 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&osc24M>, <&rtc CLK_OSC32K>; + clock-names =3D "hosc", "losc"; + status =3D "reserved"; + }; + + uart0: serial@2500000 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x2500000 0x400>; + reg-io-width =3D <4>; + reg-shift =3D <2>; + interrupts =3D <18 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&ccu CLK_BUS_UART0>; + resets =3D <&ccu RST_BUS_UART0>; + dmas =3D <&dma 14>, <&dma 14>; + dma-names =3D "rx", "tx"; + status =3D "disabled"; + }; + + uart1: serial@2500400 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x2500400 0x400>; + reg-io-width =3D <4>; + reg-shift =3D <2>; + interrupts =3D <19 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&ccu CLK_BUS_UART1>; + resets =3D <&ccu RST_BUS_UART1>; + dmas =3D <&dma 15>, <&dma 15>; + dma-names =3D "rx", "tx"; + status =3D "disabled"; + }; + + uart2: serial@2500800 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x2500800 0x400>; + reg-io-width =3D <4>; + reg-shift =3D <2>; + interrupts =3D <20 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&ccu CLK_BUS_UART2>; + resets =3D <&ccu RST_BUS_UART2>; + dmas =3D <&dma 16>, <&dma 16>; + dma-names =3D "rx", "tx"; + status =3D "disabled"; + }; + + uart3: serial@2500c00 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x2500c00 0x400>; + reg-io-width =3D <4>; + reg-shift =3D <2>; + interrupts =3D <21 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&ccu CLK_BUS_UART3>; + resets =3D <&ccu RST_BUS_UART3>; + dmas =3D <&dma 17>, <&dma 17>; + dma-names =3D "rx", "tx"; + status =3D "disabled"; + }; + + uart4: serial@2501000 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x2501000 0x400>; + reg-io-width =3D <4>; + reg-shift =3D <2>; + interrupts =3D <22 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&ccu CLK_BUS_UART4>; + resets =3D <&ccu RST_BUS_UART4>; + dmas =3D <&dma 18>, <&dma 18>; + dma-names =3D "rx", "tx"; + status =3D "disabled"; + }; + + uart5: serial@2501400 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x2501400 0x400>; + reg-io-width =3D <4>; + reg-shift =3D <2>; + interrupts =3D <23 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&ccu CLK_BUS_UART5>; + resets =3D <&ccu RST_BUS_UART5>; + dmas =3D <&dma 19>, <&dma 19>; + dma-names =3D "rx", "tx"; + status =3D "disabled"; + }; + + i2c0: i2c@2502000 { + compatible =3D "allwinner,sun20i-d1-i2c", + "allwinner,sun8i-v536-i2c", + "allwinner,sun6i-a31-i2c"; + reg =3D <0x2502000 0x400>; + interrupts =3D <25 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&ccu CLK_BUS_I2C0>; + resets =3D <&ccu RST_BUS_I2C0>; + dmas =3D <&dma 43>, <&dma 43>; + dma-names =3D "rx", "tx"; + status =3D "disabled"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c1: i2c@2502400 { + compatible =3D "allwinner,sun20i-d1-i2c", + "allwinner,sun8i-v536-i2c", + "allwinner,sun6i-a31-i2c"; + reg =3D <0x2502400 0x400>; + interrupts =3D <26 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&ccu CLK_BUS_I2C1>; + resets =3D <&ccu RST_BUS_I2C1>; + dmas =3D <&dma 44>, <&dma 44>; + dma-names =3D "rx", "tx"; + status =3D "disabled"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c2: i2c@2502800 { + compatible =3D "allwinner,sun20i-d1-i2c", + "allwinner,sun8i-v536-i2c", + "allwinner,sun6i-a31-i2c"; + reg =3D <0x2502800 0x400>; + interrupts =3D <27 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&ccu CLK_BUS_I2C2>; + resets =3D <&ccu RST_BUS_I2C2>; + dmas =3D <&dma 45>, <&dma 45>; + dma-names =3D "rx", "tx"; + status =3D "disabled"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c3: i2c@2502c00 { + compatible =3D "allwinner,sun20i-d1-i2c", + "allwinner,sun8i-v536-i2c", + "allwinner,sun6i-a31-i2c"; + reg =3D <0x2502c00 0x400>; + interrupts =3D <28 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&ccu CLK_BUS_I2C3>; + resets =3D <&ccu RST_BUS_I2C3>; + dmas =3D <&dma 46>, <&dma 46>; + dma-names =3D "rx", "tx"; + status =3D "disabled"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + syscon: syscon@3000000 { + compatible =3D "allwinner,sun20i-d1-system-control"; + reg =3D <0x3000000 0x1000>; + ranges; + #address-cells =3D <1>; + #size-cells =3D <1>; + + regulators@3000150 { + compatible =3D "allwinner,sun20i-d1-system-ldos"; + reg =3D <0x3000150 0x4>; + + reg_ldoa: ldoa { + }; + + reg_ldob: ldob { + }; + }; + }; + + dma: dma-controller@3002000 { + compatible =3D "allwinner,sun20i-d1-dma"; + reg =3D <0x3002000 0x1000>; + interrupts =3D <66 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>; + clock-names =3D "bus", "mbus"; + resets =3D <&ccu RST_BUS_DMA>; + dma-channels =3D <16>; + dma-requests =3D <48>; + #dma-cells =3D <1>; + }; + + sid: efuse@3006000 { + compatible =3D "allwinner,sun20i-d1-sid"; + reg =3D <0x3006000 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + ths_calib: ths-calib@14 { + reg =3D <0x14 0x4>; + }; + + bg_trim: bg-trim@28 { + reg =3D <0x28 0x4>; + bits =3D <16 8>; + }; + }; + + mbus: dram-controller@3102000 { + compatible =3D "allwinner,sun20i-d1-mbus"; + reg =3D <0x3102000 0x1000>, + <0x3103000 0x1000>; + reg-names =3D "mbus", "dram"; + interrupts =3D <59 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&ccu CLK_MBUS>, + <&ccu CLK_DRAM>, + <&ccu CLK_BUS_DRAM>; + clock-names =3D "mbus", "dram", "bus"; + dma-ranges =3D <0 0x40000000 0x80000000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + #interconnect-cells =3D <1>; + }; + + mmc0: mmc@4020000 { + compatible =3D "allwinner,sun20i-d1-mmc"; + reg =3D <0x4020000 0x1000>; + interrupts =3D <56 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; + clock-names =3D "ahb", "mmc"; + resets =3D <&ccu RST_BUS_MMC0>; + reset-names =3D "ahb"; + cap-sd-highspeed; + max-frequency =3D <150000000>; + no-mmc; + status =3D "disabled"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + mmc1: mmc@4021000 { + compatible =3D "allwinner,sun20i-d1-mmc"; + reg =3D <0x4021000 0x1000>; + interrupts =3D <57 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; + clock-names =3D "ahb", "mmc"; + resets =3D <&ccu RST_BUS_MMC1>; + reset-names =3D "ahb"; + cap-sd-highspeed; + max-frequency =3D <150000000>; + no-mmc; + status =3D "disabled"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + mmc2: mmc@4022000 { + compatible =3D "allwinner,sun20i-d1-emmc", + "allwinner,sun50i-a100-emmc"; + reg =3D <0x4022000 0x1000>; + interrupts =3D <58 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; + clock-names =3D "ahb", "mmc"; + resets =3D <&ccu RST_BUS_MMC2>; + reset-names =3D "ahb"; + cap-mmc-highspeed; + max-frequency =3D <150000000>; + mmc-ddr-1_8v; + mmc-ddr-3_3v; + no-sd; + no-sdio; + status =3D "disabled"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + usb_otg: usb@4100000 { + compatible =3D "allwinner,sun20i-d1-musb", + "allwinner,sun8i-a33-musb"; + reg =3D <0x4100000 0x400>; + interrupts =3D <45 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names =3D "mc"; + clocks =3D <&ccu CLK_BUS_OTG>; + resets =3D <&ccu RST_BUS_OTG>; + extcon =3D <&usbphy 0>; + phys =3D <&usbphy 0>; + phy-names =3D "usb"; + status =3D "disabled"; + }; + + usbphy: phy@4100400 { + compatible =3D "allwinner,sun20i-d1-usb-phy"; + reg =3D <0x4100400 0x100>, + <0x4101800 0x100>, + <0x4200800 0x100>; + reg-names =3D "phy_ctrl", + "pmu0", + "pmu1"; + clocks =3D <&osc24M>, + <&osc24M>; + clock-names =3D "usb0_phy", + "usb1_phy"; + resets =3D <&ccu RST_USB_PHY0>, + <&ccu RST_USB_PHY1>; + reset-names =3D "usb0_reset", + "usb1_reset"; + status =3D "disabled"; + #phy-cells =3D <1>; + }; + + ehci0: usb@4101000 { + compatible =3D "allwinner,sun20i-d1-ehci", + "generic-ehci"; + reg =3D <0x4101000 0x100>; + interrupts =3D <46 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&ccu CLK_BUS_OHCI0>, + <&ccu CLK_BUS_EHCI0>, + <&ccu CLK_USB_OHCI0>; + resets =3D <&ccu RST_BUS_OHCI0>, + <&ccu RST_BUS_EHCI0>; + phys =3D <&usbphy 0>; + phy-names =3D "usb"; + status =3D "disabled"; + }; + + ohci0: usb@4101400 { + compatible =3D "allwinner,sun20i-d1-ohci", + "generic-ohci"; + reg =3D <0x4101400 0x100>; + interrupts =3D <47 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&ccu CLK_BUS_OHCI0>, + <&ccu CLK_USB_OHCI0>; + resets =3D <&ccu RST_BUS_OHCI0>; + phys =3D <&usbphy 0>; + phy-names =3D "usb"; + status =3D "disabled"; + }; + + ehci1: usb@4200000 { + compatible =3D "allwinner,sun20i-d1-ehci", + "generic-ehci"; + reg =3D <0x4200000 0x100>; + interrupts =3D <49 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&ccu CLK_BUS_OHCI1>, + <&ccu CLK_BUS_EHCI1>, + <&ccu CLK_USB_OHCI1>; + resets =3D <&ccu RST_BUS_OHCI1>, + <&ccu RST_BUS_EHCI1>; + phys =3D <&usbphy 1>; + phy-names =3D "usb"; + status =3D "disabled"; + }; + + ohci1: usb@4200400 { + compatible =3D "allwinner,sun20i-d1-ohci", + "generic-ohci"; + reg =3D <0x4200400 0x100>; + interrupts =3D <50 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&ccu CLK_BUS_OHCI1>, + <&ccu CLK_USB_OHCI1>; + resets =3D <&ccu RST_BUS_OHCI1>; + phys =3D <&usbphy 1>; + phy-names =3D "usb"; + status =3D "disabled"; + }; + + emac: ethernet@4500000 { + compatible =3D "allwinner,sun20i-d1-emac", + "allwinner,sun50i-a64-emac"; + reg =3D <0x4500000 0x10000>; + interrupts =3D <62 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names =3D "macirq"; + clocks =3D <&ccu CLK_BUS_EMAC>; + clock-names =3D "stmmaceth"; + resets =3D <&ccu RST_BUS_EMAC>; + reset-names =3D "stmmaceth"; + syscon =3D <&syscon>; + status =3D "disabled"; + + mdio: mdio { + compatible =3D "snps,dwmac-mdio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; + + display_clocks: clock-controller@5000000 { + compatible =3D "allwinner,sun20i-d1-de2-clk", + "allwinner,sun50i-h5-de2-clk"; + reg =3D <0x5000000 0x10000>; + clocks =3D <&ccu CLK_BUS_DE>, <&ccu CLK_DE>; + clock-names =3D "bus", "mod"; + resets =3D <&ccu RST_BUS_DE>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; + + mixer0: mixer@5100000 { + compatible =3D "allwinner,sun20i-d1-de2-mixer-0"; + reg =3D <0x5100000 0x100000>; + clocks =3D <&display_clocks CLK_BUS_MIXER0>, + <&display_clocks CLK_MIXER0>; + clock-names =3D "bus", "mod"; + resets =3D <&display_clocks RST_MIXER0>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + mixer0_out: port@1 { + reg =3D <1>; + + mixer0_out_tcon_top_mixer0: endpoint { + remote-endpoint =3D <&tcon_top_mixer0_in_mixer0>; + }; + }; + }; + }; + + mixer1: mixer@5200000 { + compatible =3D "allwinner,sun20i-d1-de2-mixer-1"; + reg =3D <0x5200000 0x100000>; + clocks =3D <&display_clocks CLK_BUS_MIXER1>, + <&display_clocks CLK_MIXER1>; + clock-names =3D "bus", "mod"; + resets =3D <&display_clocks RST_MIXER1>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + mixer1_out: port@1 { + reg =3D <1>; + + mixer1_out_tcon_top_mixer1: endpoint { + remote-endpoint =3D <&tcon_top_mixer1_in_mixer1>; + }; + }; + }; + }; + + tcon_top: tcon-top@5460000 { + compatible =3D "allwinner,sun20i-d1-tcon-top"; + reg =3D <0x5460000 0x1000>; + clocks =3D <&ccu CLK_BUS_DPSS_TOP>, + <&ccu CLK_TCON_TV>, + <&ccu CLK_TVE>, + <&ccu CLK_MIPI_DSI>; + clock-names =3D "bus", "tcon-tv0", "tve0", "dsi"; + clock-output-names =3D "tcon-top-tv0", "tcon-top-dsi"; + resets =3D <&ccu RST_BUS_DPSS_TOP>; + #clock-cells =3D <1>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + tcon_top_mixer0_in: port@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + tcon_top_mixer0_in_mixer0: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&mixer0_out_tcon_top_mixer0>; + }; + }; + + tcon_top_mixer0_out: port@1 { + reg =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + tcon_top_mixer0_out_tcon_lcd0: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&tcon_lcd0_in_tcon_top_mixer0>; + }; + + tcon_top_mixer0_out_tcon_tv0: endpoint@2 { + reg =3D <2>; + remote-endpoint =3D <&tcon_tv0_in_tcon_top_mixer0>; + }; + }; + + tcon_top_mixer1_in: port@2 { + reg =3D <2>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + tcon_top_mixer1_in_mixer1: endpoint@1 { + reg =3D <1>; + remote-endpoint =3D <&mixer1_out_tcon_top_mixer1>; + }; + }; + + tcon_top_mixer1_out: port@3 { + reg =3D <3>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + tcon_top_mixer1_out_tcon_lcd0: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&tcon_lcd0_in_tcon_top_mixer1>; + }; + + tcon_top_mixer1_out_tcon_tv0: endpoint@2 { + reg =3D <2>; + remote-endpoint =3D <&tcon_tv0_in_tcon_top_mixer1>; + }; + }; + + tcon_top_hdmi_in: port@4 { + reg =3D <4>; + + tcon_top_hdmi_in_tcon_tv0: endpoint { + remote-endpoint =3D <&tcon_tv0_out_tcon_top_hdmi>; + }; + }; + + tcon_top_hdmi_out: port@5 { + reg =3D <5>; + }; + }; + }; + + tcon_lcd0: lcd-controller@5461000 { + compatible =3D "allwinner,sun20i-d1-tcon-lcd"; + reg =3D <0x5461000 0x1000>; + interrupts =3D <106 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&ccu CLK_BUS_TCON_LCD0>, + <&ccu CLK_TCON_LCD0>; + clock-names =3D "ahb", "tcon-ch0"; + clock-output-names =3D "tcon-pixel-clock"; + resets =3D <&ccu RST_BUS_TCON_LCD0>, + <&ccu RST_BUS_LVDS0>; + reset-names =3D "lcd", "lvds"; + #clock-cells =3D <0>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + tcon_lcd0_in: port@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + tcon_lcd0_in_tcon_top_mixer0: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&tcon_top_mixer0_out_tcon_lcd0>; + }; + + tcon_lcd0_in_tcon_top_mixer1: endpoint@1 { + reg =3D <1>; + remote-endpoint =3D <&tcon_top_mixer1_out_tcon_lcd0>; + }; + }; + + tcon_lcd0_out: port@1 { + reg =3D <1>; + }; + }; + }; + + tcon_tv0: lcd-controller@5470000 { + compatible =3D "allwinner,sun20i-d1-tcon-tv"; + reg =3D <0x5470000 0x1000>; + interrupts =3D <107 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&ccu CLK_BUS_TCON_TV>, + <&tcon_top CLK_TCON_TOP_TV0>; + clock-names =3D "ahb", "tcon-ch1"; + resets =3D <&ccu RST_BUS_TCON_TV>; + reset-names =3D "lcd"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + tcon_tv0_in: port@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + tcon_tv0_in_tcon_top_mixer0: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&tcon_top_mixer0_out_tcon_tv0>; + }; + + tcon_tv0_in_tcon_top_mixer1: endpoint@1 { + reg =3D <1>; + remote-endpoint =3D <&tcon_top_mixer1_out_tcon_tv0>; + }; + }; + + tcon_tv0_out: port@1 { + reg =3D <1>; + + tcon_tv0_out_tcon_top_hdmi: endpoint { + remote-endpoint =3D <&tcon_top_hdmi_in_tcon_tv0>; + }; + }; + }; + }; + + riscv_wdt: watchdog@6011000 { + compatible =3D "allwinner,sun20i-d1-wdt"; + reg =3D <0x6011000 0x20>; + interrupts =3D <147 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&osc24M>, <&rtc CLK_OSC32K>; + clock-names =3D "hosc", "losc"; + }; + + r_ccu: clock-controller@7010000 { + compatible =3D "allwinner,sun20i-d1-r-ccu"; + reg =3D <0x7010000 0x400>; + clocks =3D <&osc24M>, + <&rtc CLK_OSC32K>, + <&rtc CLK_IOSC>, + <&ccu CLK_PLL_PERIPH0_DIV3>; + clock-names =3D "hosc", "losc", "iosc", "pll-periph"; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; + + rtc: rtc@7090000 { + compatible =3D "allwinner,sun20i-d1-rtc", + "allwinner,sun50i-r329-rtc"; + reg =3D <0x7090000 0x400>; + interrupts =3D <160 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&r_ccu CLK_BUS_R_RTC>, + <&osc24M>, + <&r_ccu CLK_R_AHB>; + clock-names =3D "bus", "hosc", "ahb"; + #clock-cells =3D <1>; + }; + + plic: interrupt-controller@10000000 { + compatible =3D "allwinner,sun20i-d1-plic", + "thead,c900-plic"; + reg =3D <0x10000000 0x4000000>; + interrupts-extended =3D <&cpu0_intc 11>, + <&cpu0_intc 9>; + interrupt-controller; + riscv,ndev =3D <176>; + #address-cells =3D <0>; + #interrupt-cells =3D <2>; + }; + }; +}; --=20 2.35.1 From nobody Sat Apr 11 06:31:24 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3DAAAC00140 for ; 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Mon, 15 Aug 2022 01:08:36 -0400 (EDT) From: Samuel Holland To: Chen-Yu Tsai , Jernej Skrabec , linux-sunxi@lists.linux.dev, Palmer Dabbelt , Paul Walmsley , Albert Ou , linux-riscv@lists.infradead.org Cc: Rob Herring , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Samuel Holland Subject: [PATCH 07/12] riscv: dts: allwinner: Add Allwinner D1 Nezha devicetree Date: Mon, 15 Aug 2022 00:08:10 -0500 Message-Id: <20220815050815.22340-8-samuel@sholland.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220815050815.22340-1-samuel@sholland.org> References: <20220815050815.22340-1-samuel@sholland.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" "D1 Nezha" is Allwinner's first-party development board for the D1 SoC. It was shipped with 512M, 1G, or 2G of DDR3. It supports onboard audio, HDMI, gigabit Ethernet, WiFi and Bluetooth, USB 2.0 host and OTG ports, plus low-speed I/O from the SoC and a GPIO expander chip. Most other D1 boards copied the Nezha's power tree, with the 1.8V rail powered by the SoCs internal LDOA, analog domains powered by ALDO, and the rest of the board powered by always-on fixed regulators. Some (but not all) boards also copied the PWM CPU regulator. To avoid duplication, factor out the out the regulator references that are common across all known boards. Signed-off-by: Samuel Holland Reviewed-by: Heiko Stuebner Tested-by: Conor Dooley Tested-by: Heiko Stuebner --- arch/riscv/boot/dts/allwinner/Makefile | 1 + .../sun20i-d1-common-regulators.dtsi | 51 ++++++ .../boot/dts/allwinner/sun20i-d1-nezha.dts | 171 ++++++++++++++++++ 3 files changed, 223 insertions(+) create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-common-regulato= rs.dtsi create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts diff --git a/arch/riscv/boot/dts/allwinner/Makefile b/arch/riscv/boot/dts/a= llwinner/Makefile index f66554cd5c45..b0a15e8c8d82 100644 --- a/arch/riscv/boot/dts/allwinner/Makefile +++ b/arch/riscv/boot/dts/allwinner/Makefile @@ -1 +1,2 @@ # SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_SUNXI) +=3D sun20i-d1-nezha.dtb diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1-common-regulators.dtsi= b/arch/riscv/boot/dts/allwinner/sun20i-d1-common-regulators.dtsi new file mode 100644 index 000000000000..143a3e710c3c --- /dev/null +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-common-regulators.dtsi @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +// Copyright (C) 2021-2022 Samuel Holland + +/ { + reg_vcc: vcc { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + }; + + reg_vcc_3v3: vcc-3v3 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc-3v3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <®_vcc>; + }; +}; + +&lradc { + vref-supply =3D <®_aldo>; +}; + +&pio { + vcc-pb-supply =3D <®_vcc_3v3>; + vcc-pc-supply =3D <®_vcc_3v3>; + vcc-pd-supply =3D <®_vcc_3v3>; + vcc-pe-supply =3D <®_vcc_3v3>; + vcc-pf-supply =3D <®_vcc_3v3>; + vcc-pg-supply =3D <®_vcc_3v3>; +}; + +®_aldo { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + vdd33-supply =3D <®_vcc_3v3>; +}; + +®_hpldo { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + hpldoin-supply =3D <®_vcc_3v3>; +}; + +®_ldoa { + regulator-always-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + ldo-in-supply =3D <®_vcc_3v3>; +}; diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts b/arch/riscv= /boot/dts/allwinner/sun20i-d1-nezha.dts new file mode 100644 index 000000000000..df865ee15fcf --- /dev/null +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts @@ -0,0 +1,171 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +// Copyright (C) 2021-2022 Samuel Holland + +/dts-v1/; + +#include +#include + +#include "sun20i-d1.dtsi" +#include "sun20i-d1-common-regulators.dtsi" + +/ { + model =3D "Allwinner D1 Nezha"; + compatible =3D "allwinner,d1-nezha", "allwinner,sun20i-d1"; + + aliases { + ethernet0 =3D &emac; + ethernet1 =3D &xr829; + mmc0 =3D &mmc0; + serial0 =3D &uart0; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + reg_usbvbus: usbvbus { + compatible =3D "regulator-fixed"; + regulator-name =3D "usbvbus"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + gpio =3D <&pio 3 19 GPIO_ACTIVE_HIGH>; /* PD19 */ + enable-active-high; + vin-supply =3D <®_vcc>; + }; + + /* + * This regulator is PWM-controlled, but the PWM controller is not + * yet supported, so fix the regulator to its default voltage. + */ + reg_vdd_cpu: vdd-cpu { + compatible =3D "regulator-fixed"; + regulator-name =3D "vdd-cpu"; + regulator-min-microvolt =3D <1100000>; + regulator-max-microvolt =3D <1100000>; + vin-supply =3D <®_vcc>; + }; + + wifi_pwrseq: wifi-pwrseq { + compatible =3D "mmc-pwrseq-simple"; + reset-gpios =3D <&pio 6 12 GPIO_ACTIVE_LOW>; /* PG12 */ + }; +}; + +&cpu0 { + cpu-supply =3D <®_vdd_cpu>; +}; + +&ehci0 { + status =3D "okay"; +}; + +&ehci1 { + status =3D "okay"; +}; + +&emac { + pinctrl-0 =3D <&rgmii_pe_pins>; + pinctrl-names =3D "default"; + phy-handle =3D <&ext_rgmii_phy>; + phy-mode =3D "rgmii-id"; + phy-supply =3D <®_vcc_3v3>; + status =3D "okay"; +}; + +&i2c2 { + pinctrl-0 =3D <&i2c2_pb0_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; + + pcf8574a: gpio@38 { + compatible =3D "nxp,pcf8574a"; + reg =3D <0x38>; + interrupt-parent =3D <&pio>; + interrupts =3D <1 2 IRQ_TYPE_LEVEL_LOW>; /* PB2 */ + interrupt-controller; + gpio-controller; + #gpio-cells =3D <2>; + #interrupt-cells =3D <2>; + }; +}; + +&lradc { + status =3D "okay"; + + button-160 { + label =3D "OK"; + linux,code =3D ; + channel =3D <0>; + voltage =3D <160000>; + }; +}; + +&mdio { + ext_rgmii_phy: ethernet-phy@1 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <1>; + }; +}; + +&mmc0 { + bus-width =3D <4>; + cd-gpios =3D <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ + disable-wp; + vmmc-supply =3D <®_vcc_3v3>; + vqmmc-supply =3D <®_vcc_3v3>; + pinctrl-0 =3D <&mmc0_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&mmc1 { + bus-width =3D <4>; + mmc-pwrseq =3D <&wifi_pwrseq>; + non-removable; + vmmc-supply =3D <®_vcc_3v3>; + vqmmc-supply =3D <®_vcc_3v3>; + pinctrl-0 =3D <&mmc1_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; + + xr829: wifi@1 { + reg =3D <1>; + }; +}; + +&ohci0 { + status =3D "okay"; +}; + +&ohci1 { + status =3D "okay"; +}; + +&uart0 { + pinctrl-0 =3D <&uart0_pb8_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&uart1 { + uart-has-rtscts; + pinctrl-0 =3D <&uart1_pg6_pins>, <&uart1_pg8_rts_cts_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; + + /* XR829 bluetooth is connected here */ +}; + +&usb_otg { + dr_mode =3D "otg"; + status =3D "okay"; +}; + +&usbphy { + usb0_id_det-gpios =3D <&pio 3 21 GPIO_ACTIVE_HIGH>; /* PD21 */ + usb0_vbus_det-gpios =3D <&pio 3 20 GPIO_ACTIVE_HIGH>; /* PD20 */ + usb0_vbus-supply =3D <®_usbvbus>; + usb1_vbus-supply =3D <®_vcc>; + status =3D "okay"; +}; --=20 2.35.1 From nobody Sat Apr 11 06:31:24 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9EC0EC00140 for ; Mon, 15 Aug 2022 05:09:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240807AbiHOFJ2 (ORCPT ); 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Mon, 15 Aug 2022 01:08:40 -0400 (EDT) From: Samuel Holland To: Chen-Yu Tsai , Jernej Skrabec , linux-sunxi@lists.linux.dev, Palmer Dabbelt , Paul Walmsley , Albert Ou , linux-riscv@lists.infradead.org Cc: Rob Herring , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Samuel Holland , Jisheng Zhang Subject: [PATCH 08/12] riscv: dts: allwinner: Add Sipeed Lichee RV devicetrees Date: Mon, 15 Aug 2022 00:08:11 -0500 Message-Id: <20220815050815.22340-9-samuel@sholland.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220815050815.22340-1-samuel@sholland.org> References: <20220815050815.22340-1-samuel@sholland.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Sipeed manufactures a "Lichee RV" system-on-module, which provides a minimal working system on its own, as well as a few carrier boards. The "Dock" board provides audio, USB, and WiFi. The "86 Panel" additionally provides 100M Ethernet and a built-in display panel. The 86 Panel repurposes the USB ID and VBUS detection GPIOs for its RGB panel interface, since the USB OTG port is inaccessible inside the case. Co-developed-by: Jisheng Zhang Signed-off-by: Jisheng Zhang Signed-off-by: Samuel Holland --- arch/riscv/boot/dts/allwinner/Makefile | 4 + .../sun20i-d1-lichee-rv-86-panel-480p.dts | 29 ++++++ .../sun20i-d1-lichee-rv-86-panel-720p.dts | 10 ++ .../sun20i-d1-lichee-rv-86-panel.dtsi | 92 +++++++++++++++++++ .../allwinner/sun20i-d1-lichee-rv-dock.dts | 74 +++++++++++++++ .../dts/allwinner/sun20i-d1-lichee-rv.dts | 84 +++++++++++++++++ 6 files changed, 293 insertions(+) create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-pa= nel-480p.dts create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-pa= nel-720p.dts create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-pa= nel.dtsi create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-dock.= dts create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv.dts diff --git a/arch/riscv/boot/dts/allwinner/Makefile b/arch/riscv/boot/dts/a= llwinner/Makefile index b0a15e8c8d82..300ada20c735 100644 --- a/arch/riscv/boot/dts/allwinner/Makefile +++ b/arch/riscv/boot/dts/allwinner/Makefile @@ -1,2 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_SUNXI) +=3D sun20i-d1-lichee-rv-86-panel-480p.dtb +dtb-$(CONFIG_ARCH_SUNXI) +=3D sun20i-d1-lichee-rv-86-panel-720p.dtb +dtb-$(CONFIG_ARCH_SUNXI) +=3D sun20i-d1-lichee-rv-dock.dtb +dtb-$(CONFIG_ARCH_SUNXI) +=3D sun20i-d1-lichee-rv.dtb dtb-$(CONFIG_ARCH_SUNXI) +=3D sun20i-d1-nezha.dtb diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel-480= p.dts b/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel-480p.dts new file mode 100644 index 000000000000..4df8ffb71561 --- /dev/null +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel-480p.dts @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +// Copyright (C) 2022 Samuel Holland + +#include "sun20i-d1-lichee-rv-86-panel.dtsi" + +/ { + model =3D "Sipeed Lichee RV 86 Panel (480p)"; + compatible =3D "sipeed,lichee-rv-86-panel-480p", "sipeed,lichee-rv", + "allwinner,sun20i-d1"; +}; + +&i2c2 { + pinctrl-0 =3D <&i2c2_pb0_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; + + touchscreen@48 { + compatible =3D "focaltech,ft6236"; + reg =3D <0x48>; + interrupt-parent =3D <&pio>; + interrupts =3D <6 14 IRQ_TYPE_LEVEL_LOW>; /* PG14 */ + iovcc-supply =3D <®_vcc_3v3>; + reset-gpios =3D <&pio 6 15 GPIO_ACTIVE_LOW>; /* PG15 */ + touchscreen-size-x =3D <480>; + touchscreen-size-y =3D <480>; + vcc-supply =3D <®_vcc_3v3>; + wakeup-source; + }; +}; diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel-720= p.dts b/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel-720p.dts new file mode 100644 index 000000000000..1874fc05359f --- /dev/null +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel-720p.dts @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +// Copyright (C) 2022 Samuel Holland + +#include "sun20i-d1-lichee-rv-86-panel.dtsi" + +/ { + model =3D "Sipeed Lichee RV 86 Panel (720p)"; + compatible =3D "sipeed,lichee-rv-86-panel-720p", "sipeed,lichee-rv", + "allwinner,sun20i-d1"; +}; diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel.dts= i b/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel.dtsi new file mode 100644 index 000000000000..d89ed8047e80 --- /dev/null +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel.dtsi @@ -0,0 +1,92 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +// Copyright (C) 2022 Samuel Holland + +#include "sun20i-d1-lichee-rv.dts" + +/ { + aliases { + ethernet0 =3D &emac; + ethernet1 =3D &xr829; + }; + + /* PC1 is repurposed as BT_WAKE_AP */ + /delete-node/ leds; + + wifi_pwrseq: wifi-pwrseq { + compatible =3D "mmc-pwrseq-simple"; + clocks =3D <&ccu CLK_FANOUT1>; + clock-names =3D "ext_clock"; + reset-gpios =3D <&pio 6 12 GPIO_ACTIVE_LOW>; /* PG12 */ + assigned-clocks =3D <&ccu CLK_FANOUT1>; + assigned-clock-rates =3D <32768>; + pinctrl-0 =3D <&clk_pg11_pin>; + pinctrl-names =3D "default"; + }; +}; + +&ehci1 { + status =3D "okay"; +}; + +&emac { + pinctrl-0 =3D <&rmii_pe_pins>; + pinctrl-names =3D "default"; + phy-handle =3D <&ext_rmii_phy>; + phy-mode =3D "rmii"; + phy-supply =3D <®_vcc_3v3>; + status =3D "okay"; +}; + +&mdio { + ext_rmii_phy: ethernet-phy@1 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <1>; + reset-gpios =3D <&pio 4 16 GPIO_ACTIVE_LOW>; /* PE16 */ + }; +}; + +&mmc1 { + bus-width =3D <4>; + mmc-pwrseq =3D <&wifi_pwrseq>; + non-removable; + vmmc-supply =3D <®_vcc_3v3>; + vqmmc-supply =3D <®_vcc_3v3>; + pinctrl-0 =3D <&mmc1_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; + + xr829: wifi@1 { + reg =3D <1>; + }; +}; + +&ohci1 { + status =3D "okay"; +}; + +&pio { + clk_pg11_pin: clk-pg11-pin { + pins =3D "PG11"; + function =3D "clk"; + }; +}; + +&uart1 { + uart-has-rtscts; + pinctrl-0 =3D <&uart1_pg6_pins>, <&uart1_pg8_rts_cts_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; + + /* XR829 bluetooth is connected here */ +}; + +&usb_otg { + status =3D "disabled"; +}; + +&usbphy { + /* PD20 and PD21 are repurposed for the LCD panel */ + /delete-property/ usb0_id_det-gpios; + /delete-property/ usb0_vbus_det-gpios; + usb1_vbus-supply =3D <®_vcc>; +}; diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-dock.dts b/a= rch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-dock.dts new file mode 100644 index 000000000000..ca36a5d75a7f --- /dev/null +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-dock.dts @@ -0,0 +1,74 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +// Copyright (C) 2022 Jisheng Zhang +// Copyright (C) 2022 Samuel Holland + +#include + +#include "sun20i-d1-lichee-rv.dts" + +/ { + model =3D "Sipeed Lichee RV Dock"; + compatible =3D "sipeed,lichee-rv-dock", "sipeed,lichee-rv", + "allwinner,sun20i-d1"; + + aliases { + ethernet1 =3D &rtl8723ds; + }; + + wifi_pwrseq: wifi-pwrseq { + compatible =3D "mmc-pwrseq-simple"; + reset-gpios =3D <&pio 6 12 GPIO_ACTIVE_LOW>; /* PG12 */ + }; +}; + +&ehci1 { + status =3D "okay"; +}; + +&lradc { + status =3D "okay"; + + button-220 { + label =3D "OK"; + linux,code =3D ; + channel =3D <0>; + voltage =3D <220000>; + }; +}; + +&mmc1 { + bus-width =3D <4>; + mmc-pwrseq =3D <&wifi_pwrseq>; + non-removable; + vmmc-supply =3D <®_vcc_3v3>; + vqmmc-supply =3D <®_vcc_3v3>; + pinctrl-0 =3D <&mmc1_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; + + rtl8723ds: wifi@1 { + reg =3D <1>; + }; +}; + +&ohci1 { + status =3D "okay"; +}; + +&uart1 { + uart-has-rtscts; + pinctrl-0 =3D <&uart1_pg6_pins>, <&uart1_pg8_rts_cts_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; + + bluetooth { + compatible =3D "realtek,rtl8723ds-bt"; + device-wake-gpios =3D <&pio 6 15 GPIO_ACTIVE_HIGH>; /* PG16 */ + enable-gpios =3D <&pio 6 18 GPIO_ACTIVE_HIGH>; /* PG18 */ + host-wake-gpios =3D <&pio 6 17 GPIO_ACTIVE_HIGH>; /* PG17 */ + }; +}; + +&usbphy { + usb1_vbus-supply =3D <®_vcc>; +}; diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv.dts b/arch/r= iscv/boot/dts/allwinner/sun20i-d1-lichee-rv.dts new file mode 100644 index 000000000000..df653111b46c --- /dev/null +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv.dts @@ -0,0 +1,84 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +// Copyright (C) 2022 Jisheng Zhang +// Copyright (C) 2022 Samuel Holland + +/dts-v1/; + +#include +#include + +#include "sun20i-d1.dtsi" +#include "sun20i-d1-common-regulators.dtsi" + +/ { + model =3D "Sipeed Lichee RV"; + compatible =3D "sipeed,lichee-rv", "allwinner,sun20i-d1"; + + aliases { + mmc0 =3D &mmc0; + serial0 =3D &uart0; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + leds { + compatible =3D "gpio-leds"; + + led-0 { + color =3D ; + function =3D LED_FUNCTION_STATUS; + gpios =3D <&pio 2 1 GPIO_ACTIVE_HIGH>; /* PC1 */ + }; + }; + + reg_vdd_cpu: vdd-cpu { + compatible =3D "regulator-fixed"; + regulator-name =3D "vdd-cpu"; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <900000>; + vin-supply =3D <®_vcc>; + }; +}; + +&cpu0 { + cpu-supply =3D <®_vdd_cpu>; +}; + +&ehci0 { + status =3D "okay"; +}; + +&mmc0 { + broken-cd; + bus-width =3D <4>; + disable-wp; + vmmc-supply =3D <®_vcc_3v3>; + vqmmc-supply =3D <®_vcc_3v3>; + pinctrl-0 =3D <&mmc0_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&ohci0 { + status =3D "okay"; +}; + +&uart0 { + pinctrl-0 =3D <&uart0_pb8_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&usb_otg { + dr_mode =3D "otg"; + status =3D "okay"; +}; + +&usbphy { + usb0_id_det-gpios =3D <&pio 3 21 GPIO_ACTIVE_HIGH>; /* PD21 */ + usb0_vbus_det-gpios =3D <&pio 3 20 GPIO_ACTIVE_HIGH>; /* PD20 */ + usb0_vbus-supply =3D <®_vcc>; + status =3D "okay"; +}; --=20 2.35.1 From nobody Sat Apr 11 06:31:24 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EB8A3C282E7 for ; Mon, 15 Aug 2022 05:09:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240437AbiHOFJg (ORCPT ); Mon, 15 Aug 2022 01:09:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50780 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240377AbiHOFJD (ORCPT ); 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Mon, 15 Aug 2022 01:08:43 -0400 (EDT) From: Samuel Holland To: Chen-Yu Tsai , Jernej Skrabec , linux-sunxi@lists.linux.dev, Palmer Dabbelt , Paul Walmsley , Albert Ou , linux-riscv@lists.infradead.org Cc: Rob Herring , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Samuel Holland Subject: [PATCH 09/12] riscv: dts: allwinner: Add MangoPi MQ Pro devicetree Date: Mon, 15 Aug 2022 00:08:12 -0500 Message-Id: <20220815050815.22340-10-samuel@sholland.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220815050815.22340-1-samuel@sholland.org> References: <20220815050815.22340-1-samuel@sholland.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The MangoPi MQ Pro is a tiny SBC with a layout compatible to the Raspberry Pi Zero. It includes the Allwinner D1 SoC, 512M or 1G of DDR3, and an RTL8723DS-based WiFi/Bluetooth module. The board also exposes GPIO Port E via a connector on the end of the board, which can support either a camera or an RMII Ethernet PHY. The additional regulators supply that connector. Signed-off-by: Samuel Holland --- arch/riscv/boot/dts/allwinner/Makefile | 1 + .../allwinner/sun20i-d1-mangopi-mq-pro.dts | 128 ++++++++++++++++++ 2 files changed, 129 insertions(+) create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-mangopi-mq-pro.= dts diff --git a/arch/riscv/boot/dts/allwinner/Makefile b/arch/riscv/boot/dts/a= llwinner/Makefile index 300ada20c735..bcc304175753 100644 --- a/arch/riscv/boot/dts/allwinner/Makefile +++ b/arch/riscv/boot/dts/allwinner/Makefile @@ -3,4 +3,5 @@ dtb-$(CONFIG_ARCH_SUNXI) +=3D sun20i-d1-lichee-rv-86-panel-= 480p.dtb dtb-$(CONFIG_ARCH_SUNXI) +=3D sun20i-d1-lichee-rv-86-panel-720p.dtb dtb-$(CONFIG_ARCH_SUNXI) +=3D sun20i-d1-lichee-rv-dock.dtb dtb-$(CONFIG_ARCH_SUNXI) +=3D sun20i-d1-lichee-rv.dtb +dtb-$(CONFIG_ARCH_SUNXI) +=3D sun20i-d1-mangopi-mq-pro.dtb dtb-$(CONFIG_ARCH_SUNXI) +=3D sun20i-d1-nezha.dtb diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1-mangopi-mq-pro.dts b/a= rch/riscv/boot/dts/allwinner/sun20i-d1-mangopi-mq-pro.dts new file mode 100644 index 000000000000..61a26d3db521 --- /dev/null +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-mangopi-mq-pro.dts @@ -0,0 +1,128 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +// Copyright (C) 2022 Samuel Holland + +/dts-v1/; + +#include + +#include "sun20i-d1.dtsi" +#include "sun20i-d1-common-regulators.dtsi" + +/ { + model =3D "MangoPi MQ Pro"; + compatible =3D "widora,mangopi-mq-pro", "allwinner,sun20i-d1"; + + aliases { + ethernet0 =3D &rtl8723ds; + mmc0 =3D &mmc0; + serial0 =3D &uart0; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + reg_avdd2v8: avdd2v8 { + compatible =3D "regulator-fixed"; + regulator-name =3D "avdd2v8"; + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + vin-supply =3D <®_vcc_3v3>; + }; + + reg_dvdd: dvdd { + compatible =3D "regulator-fixed"; + regulator-name =3D "dvdd"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + vin-supply =3D <®_vcc_3v3>; + }; + + reg_vdd_cpu: vdd-cpu { + compatible =3D "regulator-fixed"; + regulator-name =3D "vdd-cpu"; + regulator-min-microvolt =3D <1100000>; + regulator-max-microvolt =3D <1100000>; + vin-supply =3D <®_vcc>; + }; + + wifi_pwrseq: wifi-pwrseq { + compatible =3D "mmc-pwrseq-simple"; + reset-gpios =3D <&pio 6 17 GPIO_ACTIVE_LOW>; /* PG17 */ + }; +}; + +&cpu0 { + cpu-supply =3D <®_vdd_cpu>; +}; + +&ehci1 { + status =3D "okay"; +}; + +&mmc0 { + bus-width =3D <4>; + cd-gpios =3D <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ + disable-wp; + vmmc-supply =3D <®_vcc_3v3>; + vqmmc-supply =3D <®_vcc_3v3>; + pinctrl-0 =3D <&mmc0_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&mmc1 { + bus-width =3D <4>; + mmc-pwrseq =3D <&wifi_pwrseq>; + non-removable; + vmmc-supply =3D <®_vcc_3v3>; + vqmmc-supply =3D <®_vcc_3v3>; + pinctrl-0 =3D <&mmc1_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; + + rtl8723ds: wifi@1 { + reg =3D <1>; + interrupt-parent =3D <&pio>; + interrupts =3D <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 */ + interrupt-names =3D "host-wake"; + }; +}; + +&ohci1 { + status =3D "okay"; +}; + +&pio { + vcc-pe-supply =3D <®_avdd2v8>; +}; + +&uart0 { + pinctrl-0 =3D <&uart0_pb8_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&uart1 { + uart-has-rtscts; + pinctrl-0 =3D <&uart1_pg6_pins>, <&uart1_pg8_rts_cts_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; + + bluetooth { + compatible =3D "realtek,rtl8723ds-bt"; + device-wake-gpios =3D <&pio 6 18 GPIO_ACTIVE_HIGH>; /* PG18 */ + enable-gpios =3D <&pio 6 15 GPIO_ACTIVE_HIGH>; /* PG15 */ + host-wake-gpios =3D <&pio 6 14 GPIO_ACTIVE_HIGH>; /* PG14 */ + }; +}; + +&usb_otg { + dr_mode =3D "peripheral"; + status =3D "okay"; +}; + +&usbphy { + usb0_vbus-supply =3D <®_vcc>; + status =3D "okay"; +}; --=20 2.35.1 From nobody Sat Apr 11 06:31:24 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A5424C00140 for ; Mon, 15 Aug 2022 05:09:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240475AbiHOFJj (ORCPT ); Mon, 15 Aug 2022 01:09:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50466 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240453AbiHOFJE (ORCPT ); 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Mon, 15 Aug 2022 01:08:46 -0400 (EDT) From: Samuel Holland To: Chen-Yu Tsai , Jernej Skrabec , linux-sunxi@lists.linux.dev, Palmer Dabbelt , Paul Walmsley , Albert Ou , linux-riscv@lists.infradead.org Cc: Rob Herring , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Samuel Holland Subject: [PATCH 10/12] riscv: dts: allwinner: Add Dongshan Nezha STU devicetree Date: Mon, 15 Aug 2022 00:08:13 -0500 Message-Id: <20220815050815.22340-11-samuel@sholland.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220815050815.22340-1-samuel@sholland.org> References: <20220815050815.22340-1-samuel@sholland.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The 100ask Dongshan Nezha STU is a system-on-module that can be used standalone or with a carrier board. The SoM provides gigabit Ethernet, HDMI, a USB peripheral port, and WiFi/Bluetooth via an RTL8723DS chip. The "DIY" carrier board exposes almost every pin from the D1 SoC to 0.1" headers, but contains no digital circuitry, so it does not have its own devicetree. Signed-off-by: Samuel Holland --- arch/riscv/boot/dts/allwinner/Makefile | 1 + .../sun20i-d1-dongshan-nezha-stu.dts | 114 ++++++++++++++++++ 2 files changed, 115 insertions(+) create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-dongshan-nezha-= stu.dts diff --git a/arch/riscv/boot/dts/allwinner/Makefile b/arch/riscv/boot/dts/a= llwinner/Makefile index bcc304175753..530ef8adb8b0 100644 --- a/arch/riscv/boot/dts/allwinner/Makefile +++ b/arch/riscv/boot/dts/allwinner/Makefile @@ -1,4 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_SUNXI) +=3D sun20i-d1-dongshan-nezha-stu.dtb dtb-$(CONFIG_ARCH_SUNXI) +=3D sun20i-d1-lichee-rv-86-panel-480p.dtb dtb-$(CONFIG_ARCH_SUNXI) +=3D sun20i-d1-lichee-rv-86-panel-720p.dtb dtb-$(CONFIG_ARCH_SUNXI) +=3D sun20i-d1-lichee-rv-dock.dtb diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1-dongshan-nezha-stu.dts= b/arch/riscv/boot/dts/allwinner/sun20i-d1-dongshan-nezha-stu.dts new file mode 100644 index 000000000000..c3d06dfaa7c3 --- /dev/null +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-dongshan-nezha-stu.dts @@ -0,0 +1,114 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +// Copyright (C) 2022 Samuel Holland + +/dts-v1/; + +#include +#include + +#include "sun20i-d1.dtsi" +#include "sun20i-d1-common-regulators.dtsi" + +/ { + model =3D "Dongshan Nezha STU"; + compatible =3D "100ask,dongshan-nezha-stu", "allwinner,sun20i-d1"; + + aliases { + ethernet0 =3D &emac; + mmc0 =3D &mmc0; + serial0 =3D &uart0; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + leds { + compatible =3D "gpio-leds"; + + led-0 { + color =3D ; + function =3D LED_FUNCTION_STATUS; + gpios =3D <&pio 2 1 GPIO_ACTIVE_HIGH>; /* PC1 */ + }; + }; + + reg_usbvbus: usbvbus { + compatible =3D "regulator-fixed"; + regulator-name =3D "usbvbus"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + gpio =3D <&pio 3 19 GPIO_ACTIVE_HIGH>; /* PD19 */ + enable-active-high; + vin-supply =3D <®_vcc>; + }; + + /* + * This regulator is PWM-controlled, but the PWM controller is not + * yet supported, so fix the regulator to its default voltage. + */ + reg_vdd_cpu: vdd-cpu { + compatible =3D "regulator-fixed"; + regulator-name =3D "vdd-cpu"; + regulator-min-microvolt =3D <1100000>; + regulator-max-microvolt =3D <1100000>; + vin-supply =3D <®_vcc>; + }; +}; + +&cpu0 { + cpu-supply =3D <®_vdd_cpu>; +}; + +&ehci0 { + status =3D "okay"; +}; + +&emac { + pinctrl-0 =3D <&rgmii_pe_pins>; + pinctrl-names =3D "default"; + phy-handle =3D <&ext_rgmii_phy>; + phy-mode =3D "rgmii-id"; + phy-supply =3D <®_vcc_3v3>; + status =3D "okay"; +}; + +&mdio { + ext_rgmii_phy: ethernet-phy@1 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <1>; + }; +}; + +&mmc0 { + broken-cd; + bus-width =3D <4>; + disable-wp; + vmmc-supply =3D <®_vcc_3v3>; + vqmmc-supply =3D <®_vcc_3v3>; + pinctrl-0 =3D <&mmc0_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&ohci0 { + status =3D "okay"; +}; + +&uart0 { + pinctrl-0 =3D <&uart0_pb8_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&usb_otg { + dr_mode =3D "otg"; + status =3D "okay"; +}; + +&usbphy { + usb0_id_det-gpios =3D <&pio 3 21 GPIO_ACTIVE_HIGH>; /* PD21 */ + usb0_vbus_det-gpios =3D <&pio 3 20 GPIO_ACTIVE_HIGH>; /* PD20 */ + usb0_vbus-supply =3D <®_usbvbus>; + status =3D "okay"; +}; --=20 2.35.1 From nobody Sat Apr 11 06:31:24 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 68605C25B0D for ; Mon, 15 Aug 2022 05:09:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240784AbiHOFJ5 (ORCPT ); Mon, 15 Aug 2022 01:09:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51298 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230214AbiHOFJJ (ORCPT ); Mon, 15 Aug 2022 01:09:09 -0400 Received: from wout1-smtp.messagingengine.com (wout1-smtp.messagingengine.com [64.147.123.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D0F6A15FF4; Sun, 14 Aug 2022 22:08:52 -0700 (PDT) Received: from compute2.internal (compute2.nyi.internal [10.202.2.46]) by mailout.west.internal (Postfix) with ESMTP id 7A1BB32000F9; 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Mon, 15 Aug 2022 01:08:49 -0400 (EDT) From: Samuel Holland To: Chen-Yu Tsai , Jernej Skrabec , linux-sunxi@lists.linux.dev, Palmer Dabbelt , Paul Walmsley , Albert Ou , linux-riscv@lists.infradead.org Cc: Rob Herring , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Samuel Holland Subject: [PATCH 11/12] riscv: dts: allwinner: Add ClockworkPi and DevTerm devicetrees Date: Mon, 15 Aug 2022 00:08:14 -0500 Message-Id: <20220815050815.22340-12-samuel@sholland.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220815050815.22340-1-samuel@sholland.org> References: <20220815050815.22340-1-samuel@sholland.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Clockwork Tech manufactures several SoMs for their RasPi CM3-compatible "ClockworkPi" mainboard. Their R-01 SoM features the Allwinner D1 SoC. The R-01 contains only the CPU, DRAM, and always-on voltage regulation; it does not merit a separate devicetree. The ClockworkPi mainboard features analog audio, a MIPI-DSI panel, USB host and peripheral ports, an Ampak AP6256 WiFi/Bluetooth module, and an X-Powers AXP228 PMIC for managing a Li-ion battery. The DevTerm is a complete system which extends the ClockworkPi mainboard with a pair of expansion boards. These expansion boards provide a fan, a keyboard, speakers, and a thermal printer. Signed-off-by: Samuel Holland --- arch/riscv/boot/dts/allwinner/Makefile | 2 + .../allwinner/sun20i-d1-clockworkpi-v3.14.dts | 242 ++++++++++++++++++ .../dts/allwinner/sun20i-d1-devterm-v3.14.dts | 37 +++ 3 files changed, 281 insertions(+) create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-clockworkpi-v3.= 14.dts create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-devterm-v3.14.d= ts diff --git a/arch/riscv/boot/dts/allwinner/Makefile b/arch/riscv/boot/dts/a= llwinner/Makefile index 530ef8adb8b0..25097da6fdb9 100644 --- a/arch/riscv/boot/dts/allwinner/Makefile +++ b/arch/riscv/boot/dts/allwinner/Makefile @@ -1,4 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_SUNXI) +=3D sun20i-d1-clockworkpi-v3.14.dtb +dtb-$(CONFIG_ARCH_SUNXI) +=3D sun20i-d1-devterm-v3.14.dtb dtb-$(CONFIG_ARCH_SUNXI) +=3D sun20i-d1-dongshan-nezha-stu.dtb dtb-$(CONFIG_ARCH_SUNXI) +=3D sun20i-d1-lichee-rv-86-panel-480p.dtb dtb-$(CONFIG_ARCH_SUNXI) +=3D sun20i-d1-lichee-rv-86-panel-720p.dtb diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1-clockworkpi-v3.14.dts = b/arch/riscv/boot/dts/allwinner/sun20i-d1-clockworkpi-v3.14.dts new file mode 100644 index 000000000000..74b4b6d8363a --- /dev/null +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-clockworkpi-v3.14.dts @@ -0,0 +1,242 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +// Copyright (C) 2022 Samuel Holland + +/dts-v1/; + +#include + +#include "sun20i-d1.dtsi" +#include "sun20i-d1-common-regulators.dtsi" + +/ { + model =3D "ClockworkPi v3.14 (R-01)"; + compatible =3D "clockwork,r-01-clockworkpi-v3.14", "allwinner,sun20i-d1"; + + aliases { + ethernet0 =3D &ap6256; + mmc0 =3D &mmc0; + serial0 =3D &uart0; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + /* + * This regulator is PWM-controlled, but the PWM controller is not + * yet supported, so fix the regulator to its default voltage. + */ + reg_vdd_cpu: vdd-cpu { + compatible =3D "regulator-fixed"; + regulator-name =3D "vdd-cpu"; + regulator-min-microvolt =3D <1100000>; + regulator-max-microvolt =3D <1100000>; + vin-supply =3D <®_vcc>; + }; + + wifi_pwrseq: wifi-pwrseq { + compatible =3D "mmc-pwrseq-simple"; + reset-gpios =3D <&pio 6 11 GPIO_ACTIVE_LOW>; /* PG11/GPIO3 */ + }; +}; + +&cpu0 { + cpu-supply =3D <®_vdd_cpu>; +}; + +&ehci1 { + status =3D "okay"; +}; + +&i2c0 { + pinctrl-0 =3D <&i2c0_pb10_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; + + axp221: pmic@34 { + compatible =3D "x-powers,axp228", "x-powers,axp221"; + reg =3D <0x34>; + interrupt-parent =3D <&pio>; + interrupts =3D <4 9 IRQ_TYPE_LEVEL_LOW>; /* PE9/GPIO2 */ + interrupt-controller; + #interrupt-cells =3D <1>; + + ac_power_supply: ac-power { + compatible =3D "x-powers,axp221-ac-power-supply"; + }; + + axp_adc: adc { + compatible =3D "x-powers,axp221-adc"; + #io-channel-cells =3D <1>; + }; + + battery_power_supply: battery-power { + compatible =3D "x-powers,axp221-battery-power-supply"; + }; + + regulators { + x-powers,dcdc-freq =3D <3000>; + + reg_dcdc1: dcdc1 { + regulator-name =3D "sys-3v3"; + regulator-always-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + }; + + reg_dcdc3: dcdc3 { + regulator-name =3D "sys-1v8"; + regulator-always-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + }; + + reg_aldo1: aldo1 { + regulator-name =3D "aud-3v3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + }; + + reg_aldo2: aldo2 { + regulator-name =3D "disp-3v3"; + regulator-always-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + }; + + reg_aldo3: aldo3 { + regulator-name =3D "vdd-wifi"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + }; + + /* DLDO1 and ELDO1-3 are connected in parallel. */ + reg_dldo1: dldo1 { + regulator-name =3D "vbat-wifi-a"; + regulator-always-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + }; + + /* DLDO2-DLDO4 are connected in parallel. */ + reg_dldo2: dldo2 { + regulator-name =3D "vcc-3v3-ext-a"; + regulator-always-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + }; + + reg_dldo3: dldo3 { + regulator-name =3D "vcc-3v3-ext-b"; + regulator-always-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + }; + + reg_dldo4: dldo4 { + regulator-name =3D "vcc-3v3-ext-c"; + regulator-always-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + }; + + reg_eldo1: eldo1 { + regulator-name =3D "vbat-wifi-b"; + regulator-always-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + }; + + reg_eldo2: eldo2 { + regulator-name =3D "vbat-wifi-c"; + regulator-always-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + }; + + reg_eldo3: eldo3 { + regulator-name =3D "vbat-wifi-d"; + regulator-always-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + }; + }; + + usb_power_supply: usb-power { + compatible =3D "x-powers,axp221-usb-power-supply"; + status =3D "disabled"; + }; + }; +}; + +&mmc0 { + broken-cd; + bus-width =3D <4>; + disable-wp; + vmmc-supply =3D <®_dcdc1>; + vqmmc-supply =3D <®_vcc_3v3>; + pinctrl-0 =3D <&mmc0_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&mmc1 { + bus-width =3D <4>; + mmc-pwrseq =3D <&wifi_pwrseq>; + non-removable; + vmmc-supply =3D <®_dldo1>; + vqmmc-supply =3D <®_aldo3>; + pinctrl-0 =3D <&mmc1_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; + + ap6256: wifi@1 { + compatible =3D "brcm,bcm43456-fmac", "brcm,bcm4329-fmac"; + reg =3D <1>; + interrupt-parent =3D <&pio>; + interrupts =3D <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10/GPIO4 */ + interrupt-names =3D "host-wake"; + }; +}; + +&ohci1 { + status =3D "okay"; +}; + +&pio { + vcc-pg-supply =3D <®_ldoa>; +}; + +&uart0 { + pinctrl-0 =3D <&uart0_pb8_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&uart1 { + uart-has-rtscts; + pinctrl-0 =3D <&uart1_pg6_pins>, <&uart1_pg8_rts_cts_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; + + bluetooth { + compatible =3D "brcm,bcm4345c5"; + interrupt-parent =3D <&pio>; + interrupts =3D <6 17 IRQ_TYPE_LEVEL_HIGH>; /* PG17/GPIO6 */ + device-wakeup-gpios =3D <&pio 6 16 GPIO_ACTIVE_HIGH>; /* PG16/GPIO7 */ + shutdown-gpios =3D <&pio 6 18 GPIO_ACTIVE_HIGH>; /* PG18/GPIO5 */ + max-speed =3D <1500000>; + vbat-supply =3D <®_dldo1>; + vddio-supply =3D <®_aldo3>; + }; +}; + +&usb_otg { + dr_mode =3D "peripheral"; + status =3D "okay"; +}; + +&usbphy { + usb0_vbus_power-supply =3D <&ac_power_supply>; + status =3D "okay"; +}; diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1-devterm-v3.14.dts b/ar= ch/riscv/boot/dts/allwinner/sun20i-d1-devterm-v3.14.dts new file mode 100644 index 000000000000..690bfa35a548 --- /dev/null +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-devterm-v3.14.dts @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +// Copyright (C) 2022 Samuel Holland + +/dts-v1/; + +#include "sun20i-d1-clockworkpi-v3.14.dts" + +/ { + model =3D "Clockwork DevTerm (R-01)"; + compatible =3D "clockwork,r-01-devterm-v3.14", + "clockwork,r-01-clockworkpi-v3.14", + "allwinner,sun20i-d1"; + + fan { + compatible =3D "gpio-fan"; + gpios =3D <&pio 3 10 GPIO_ACTIVE_HIGH>; /* PD10/GPIO41 */ + gpio-fan,speed-map =3D <0 0>, + <6000 1>; + #cooling-cells =3D <2>; + }; + + i2c-gpio-0 { + compatible =3D "i2c-gpio"; + sda-gpios =3D <&pio 3 14 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; /* PD14/GP= IO44 */ + scl-gpios =3D <&pio 3 15 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; /* PD15/GP= IO45 */ + #address-cells =3D <1>; + #size-cells =3D <0>; + + adc@54 { + compatible =3D "ti,adc101c"; + reg =3D <0x54>; + interrupt-parent =3D <&pio>; + interrupts =3D <4 12 IRQ_TYPE_LEVEL_LOW>; /* PE12/GPIO35 */ + vref-supply =3D <®_dldo2>; + }; + }; +}; --=20 2.35.1 From nobody Sat Apr 11 06:31:24 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2E1EBC00140 for ; Mon, 15 Aug 2022 05:10:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240334AbiHOFKD (ORCPT ); Mon, 15 Aug 2022 01:10:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51626 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240792AbiHOFJW (ORCPT ); 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Mon, 15 Aug 2022 01:08:52 -0400 (EDT) From: Samuel Holland To: Chen-Yu Tsai , Jernej Skrabec , linux-sunxi@lists.linux.dev, Palmer Dabbelt , Paul Walmsley , Albert Ou , linux-riscv@lists.infradead.org Cc: Rob Herring , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Samuel Holland Subject: [PATCH 12/12] riscv: defconfig: Enable the Allwinner D1 platform and drivers Date: Mon, 15 Aug 2022 00:08:15 -0500 Message-Id: <20220815050815.22340-13-samuel@sholland.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220815050815.22340-1-samuel@sholland.org> References: <20220815050815.22340-1-samuel@sholland.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Now that several D1-based boards are supported, enable the platform in our defconfig. Build in the drivers which are necessary to boot, such as the pinctrl, MMC, RTC (which provides critical clocks), SPI (for flash), and watchdog (which may be left enabled by the bootloader). Other common onboard peripherals are enabled as modules. Signed-off-by: Samuel Holland --- arch/riscv/configs/defconfig | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index aed332a9d4ea..8f856982da87 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -25,6 +25,7 @@ CONFIG_BLK_DEV_INITRD=3Dy CONFIG_EXPERT=3Dy # CONFIG_SYSFS_SYSCALL is not set CONFIG_PROFILING=3Dy +CONFIG_ARCH_SUNXI=3Dy CONFIG_SOC_MICROCHIP_POLARFIRE=3Dy CONFIG_SOC_SIFIVE=3Dy CONFIG_SOC_STARFIVE=3Dy @@ -118,22 +119,31 @@ CONFIG_VIRTIO_NET=3Dy CONFIG_MACB=3Dy CONFIG_E1000E=3Dy CONFIG_R8169=3Dy +CONFIG_STMMAC_ETH=3Dm CONFIG_MICROSEMI_PHY=3Dy CONFIG_INPUT_MOUSEDEV=3Dy +CONFIG_KEYBOARD_SUN4I_LRADC=3Dm CONFIG_SERIAL_8250=3Dy CONFIG_SERIAL_8250_CONSOLE=3Dy +CONFIG_SERIAL_8250_DW=3Dy CONFIG_SERIAL_OF_PLATFORM=3Dy CONFIG_VIRTIO_CONSOLE=3Dy CONFIG_HW_RANDOM=3Dy CONFIG_HW_RANDOM_VIRTIO=3Dy +CONFIG_I2C_MV64XXX=3Dm CONFIG_SPI=3Dy CONFIG_SPI_SIFIVE=3Dy +CONFIG_SPI_SUN6I=3Dy # CONFIG_PTP_1588_CLOCK is not set -CONFIG_GPIOLIB=3Dy CONFIG_GPIO_SIFIVE=3Dy +CONFIG_WATCHDOG=3Dy +CONFIG_SUNXI_WATCHDOG=3Dy +CONFIG_REGULATOR=3Dy +CONFIG_REGULATOR_FIXED_VOLTAGE=3Dy CONFIG_DRM=3Dm CONFIG_DRM_RADEON=3Dm CONFIG_DRM_NOUVEAU=3Dm +CONFIG_DRM_SUN4I=3Dm CONFIG_DRM_VIRTIO_GPU=3Dm CONFIG_FB=3Dy CONFIG_FRAMEBUFFER_CONSOLE=3Dy @@ -146,19 +156,30 @@ CONFIG_USB_OHCI_HCD=3Dy CONFIG_USB_OHCI_HCD_PLATFORM=3Dy CONFIG_USB_STORAGE=3Dy CONFIG_USB_UAS=3Dy +CONFIG_USB_MUSB_HDRC=3Dm +CONFIG_USB_MUSB_SUNXI=3Dm +CONFIG_NOP_USB_XCEIV=3Dm CONFIG_MMC=3Dy CONFIG_MMC_SDHCI=3Dy CONFIG_MMC_SDHCI_PLTFM=3Dy CONFIG_MMC_SDHCI_CADENCE=3Dy CONFIG_MMC_SPI=3Dy +CONFIG_MMC_SUNXI=3Dy CONFIG_RTC_CLASS=3Dy +CONFIG_RTC_DRV_SUN6I=3Dy +CONFIG_DMADEVICES=3Dy +CONFIG_DMA_SUN6I=3Dm CONFIG_VIRTIO_PCI=3Dy CONFIG_VIRTIO_BALLOON=3Dy CONFIG_VIRTIO_INPUT=3Dy CONFIG_VIRTIO_MMIO=3Dy +CONFIG_SUN8I_DE2_CCU=3Dm +CONFIG_SUN50I_IOMMU=3Dy CONFIG_RPMSG_CHAR=3Dy CONFIG_RPMSG_CTRL=3Dy CONFIG_RPMSG_VIRTIO=3Dy +CONFIG_PHY_SUN4I_USB=3Dm +CONFIG_NVMEM_SUNXI_SID=3Dy CONFIG_EXT4_FS=3Dy CONFIG_EXT4_FS_POSIX_ACL=3Dy CONFIG_EXT4_FS_SECURITY=3Dy --=20 2.35.1