From nobody Sat Sep 21 17:35:42 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 295F4C00140 for ; Mon, 15 Aug 2022 03:08:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231919AbiHODIC (ORCPT ); Sun, 14 Aug 2022 23:08:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52410 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229929AbiHODH4 (ORCPT ); Sun, 14 Aug 2022 23:07:56 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0695E11A26 for ; Sun, 14 Aug 2022 20:07:53 -0700 (PDT) X-UUID: ef832e57d9ba46239fadc31fa103fe3d-20220815 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; 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Mon, 15 Aug 2022 11:07:47 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 15 Aug 2022 11:07:46 +0800 From: Yongqiang Niu To: Chun-Kuang Hu CC: Jassi Brar , Matthias Brugger , , , , , Hsin-Yi Wang , Yongqiang Niu , Allen-kh Cheng Subject: [PATCH v1, 1/1] mailbox: mtk-cmdq: fix gce timeout issue Date: Mon, 15 Aug 2022 11:07:40 +0800 Message-ID: <20220815030740.28899-2-yongqiang.niu@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220815030740.28899-1-yongqiang.niu@mediatek.com> References: <20220815030740.28899-1-yongqiang.niu@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Yongqiang Niu 1. enable gce ddr enable(gce reigster offset 0x48, bit 16 to 18) when gce w= ork, and disable gce ddr enable when gce work job done 2. split cmdq clk enable/disable api, and control gce ddr enable/disable in clk enable/disable function to make sure it could protect when cmdq is multiple used by display and mdp Signed-off-by: Yongqiang Niu Signed-off-by: Allen-kh Cheng --- drivers/mailbox/mtk-cmdq-mailbox.c | 57 ++++++++++++++++++++++++++---- 1 file changed, 51 insertions(+), 6 deletions(-) diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-= mailbox.c index 2578e5aaa935..64a47470f062 100644 --- a/drivers/mailbox/mtk-cmdq-mailbox.c +++ b/drivers/mailbox/mtk-cmdq-mailbox.c @@ -81,6 +81,8 @@ struct cmdq { u8 shift_pa; bool control_by_sw; u32 gce_num; + atomic_t usage; + spinlock_t lock; }; =20 struct gce_plat { @@ -90,6 +92,46 @@ struct gce_plat { u32 gce_num; }; =20 +static s32 cmdq_clk_enable(struct cmdq *cmdq) +{ + s32 usage, ret; + unsigned long flags; + + spin_lock_irqsave(&cmdq->lock, flags); + + usage =3D atomic_inc_return(&cmdq->usage); + + ret =3D clk_bulk_enable(cmdq->gce_num, cmdq->clocks); + if (usage <=3D0 || ret < 0) { + dev_err(cmdq->mbox.dev, "ref count %d ret %d suspend %d\n", + usage, ret, cmdq->suspended); + } else if (usage =3D=3D 1) { + if (cmdq->control_by_sw) + writel((0x7 << 16) + 0x7, cmdq->base + GCE_GCTL_VALUE); + } + + spin_unlock_irqrestore(&cmdq->lock, flags); + + return ret; +} + +static void cmdq_clk_disable(struct cmdq *cmdq) +{ + s32 usage; + + usage =3D atomic_dec_return(&cmdq->usage); + + if (usage < 0) { + dev_err(cmdq->mbox.dev, "ref count %d suspend %d\n", + usage, cmdq->suspended); + } else if (usage =3D=3D 0) { + if (cmdq->control_by_sw) + writel(0x7, cmdq->base + GCE_GCTL_VALUE); + } + + clk_bulk_disable(cmdq->gce_num, cmdq->clocks); +} + u8 cmdq_get_shift_pa(struct mbox_chan *chan) { struct cmdq *cmdq =3D container_of(chan->mbox, struct cmdq, mbox); @@ -271,7 +313,8 @@ static void cmdq_thread_irq_handler(struct cmdq *cmdq, =20 if (list_empty(&thread->task_busy_list)) { cmdq_thread_disable(cmdq, thread); - clk_bulk_disable(cmdq->gce_num, cmdq->clocks); + + cmdq_clk_disable(cmdq); } } =20 @@ -360,8 +403,7 @@ static int cmdq_mbox_send_data(struct mbox_chan *chan, = void *data) task->pkt =3D pkt; =20 if (list_empty(&thread->task_busy_list)) { - WARN_ON(clk_bulk_enable(cmdq->gce_num, cmdq->clocks)); - + WARN_ON(cmdq_clk_enable(cmdq) < 0); /* * The thread reset will clear thread related register to 0, * including pc, end, priority, irq, suspend and enable. Thus @@ -433,7 +475,7 @@ static void cmdq_mbox_shutdown(struct mbox_chan *chan) } =20 cmdq_thread_disable(cmdq, thread); - clk_bulk_disable(cmdq->gce_num, cmdq->clocks); + cmdq_clk_disable(cmdq); =20 done: /* @@ -479,7 +521,8 @@ static int cmdq_mbox_flush(struct mbox_chan *chan, unsi= gned long timeout) =20 cmdq_thread_resume(thread); cmdq_thread_disable(cmdq, thread); - clk_bulk_disable(cmdq->gce_num, cmdq->clocks); + + cmdq_clk_disable(cmdq); =20 out: spin_unlock_irqrestore(&thread->chan->lock, flags); @@ -490,7 +533,8 @@ static int cmdq_mbox_flush(struct mbox_chan *chan, unsi= gned long timeout) spin_unlock_irqrestore(&thread->chan->lock, flags); if (readl_poll_timeout_atomic(thread->base + CMDQ_THR_ENABLE_TASK, enable, enable =3D=3D 0, 1, timeout)) { - dev_err(cmdq->mbox.dev, "Fail to wait GCE thread 0x%x done\n", + dev_err(cmdq->mbox.dev, + "Fail to wait GCE thread 0x%x done\n", (u32)(thread->base - cmdq->base)); =20 return -EFAULT; @@ -626,6 +670,7 @@ static int cmdq_probe(struct platform_device *pdev) =20 WARN_ON(clk_bulk_prepare(cmdq->gce_num, cmdq->clocks)); =20 + spin_lock_init(&cmdq->lock); cmdq_init(cmdq); =20 return 0; --=20 2.25.1