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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Aug 2022 18:00:10.9491 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d6b4697c-eefd-4c26-1423-08da7bc3558c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT029.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4053 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Need to protect DSC code with CONFIG_DRM_AMD_DC_DCN. Fixes the following build errors on arm64: ERROR: modpost: "dc_dsc_get_policy_for_timing" [drivers/gpu/drm/amd/amdgpu/= amdgpu.ko] undefined! ERROR: modpost: "dc_dsc_compute_bandwidth_range" [drivers/gpu/drm/amd/amdgp= u/amdgpu.ko] undefined! Fixes: 0087990a9f57 ("drm/amd/display: consider DSC pass-through during mod= e validation") Reported-by: Anders Roxell Signed-off-by: Hamza Mahfooz Reviewed-by: Alex Deucher Tested-by: Anders Roxell Tested-by: Sudip Mukherjee --- v2: Fix WERROR build failure by guarding unused variables --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/= drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index ef6c94cd852b..ce6929224a6e 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -1387,8 +1387,6 @@ bool pre_validate_dsc(struct drm_atomic_state *state, return (ret =3D=3D 0); } =20 -#endif - static unsigned int kbps_from_pbn(unsigned int pbn) { unsigned int kbps =3D pbn; @@ -1416,17 +1414,19 @@ static bool is_dsc_common_config_possible(struct dc= _stream_state *stream, =20 return bw_range->max_target_bpp_x16 && bw_range->min_target_bpp_x16; } +#endif /* CONFIG_DRM_AMD_DC_DCN */ =20 enum dc_status dm_dp_mst_is_port_support_mode( struct amdgpu_dm_connector *aconnector, struct dc_stream_state *stream) { + int bpp, pbn, branch_max_throughput_mps =3D 0; +#if defined(CONFIG_DRM_AMD_DC_DCN) struct dc_link_settings cur_link_settings; unsigned int end_to_end_bw_in_kbps =3D 0; unsigned int upper_link_bw_in_kbps =3D 0, down_link_bw_in_kbps =3D 0; unsigned int max_compressed_bw_in_kbps =3D 0; struct dc_dsc_bw_range bw_range =3D {0}; - int bpp, pbn, branch_max_throughput_mps =3D 0; =20 /* * check if the mode could be supported if DSC pass-through is supported @@ -1461,13 +1461,16 @@ enum dc_status dm_dp_mst_is_port_support_mode( return DC_FAIL_BANDWIDTH_VALIDATE; } } else { +#endif /* check if mode could be supported within full_pbn */ bpp =3D convert_dc_color_depth_into_bpc(stream->timing.display_color_dep= th) * 3; pbn =3D drm_dp_calc_pbn_mode(stream->timing.pix_clk_100hz / 10, bpp, fal= se); =20 if (pbn > aconnector->port->full_pbn) return DC_FAIL_BANDWIDTH_VALIDATE; +#if defined(CONFIG_DRM_AMD_DC_DCN) } +#endif =20 /* check is mst dsc output bandwidth branch_overall_throughput_0_mps */ switch (stream->timing.pixel_encoding) { --=20 2.37.1