From nobody Sat Apr 11 12:37:10 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 17D46C25B0C for ; Thu, 11 Aug 2022 10:09:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234969AbiHKKJ5 (ORCPT ); Thu, 11 Aug 2022 06:09:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46320 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234937AbiHKKJr (ORCPT ); Thu, 11 Aug 2022 06:09:47 -0400 Received: from mail-pl1-x62b.google.com (mail-pl1-x62b.google.com [IPv6:2607:f8b0:4864:20::62b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 900039352B for ; Thu, 11 Aug 2022 03:09:40 -0700 (PDT) Received: by mail-pl1-x62b.google.com with SMTP id z19so16561711plb.1 for ; Thu, 11 Aug 2022 03:09:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=Aj7bIRpBxLE/QbhIHFv2D/FvUghNvupNjdDm/EaW0wk=; b=DYDleXwOCYrNafDo5GTknws4qyaWdcZJC5pHMUT6MxD8vLe9dzIv0p5VcCtKAP5NrD IOR/4nX6nmc0lHwH7I0gC2+RpzpMmGgF+f4HsAQQNL91gbmXuuhEph1cbfwrK7IZ1BpC FutezzNK7GKH5Y5N56WKJAdkxbrWH/RL74Yh0N++x1tH5idG/pkA/JspCYc+4ci8cd11 1CTU2301kFtSPkNLUXA0fjEqUrNetZwDRrBP8urvs9WBNTDuG6HgknuV37c4mn8iVLRS mImomnsYdW7fvliKsGe7LmyTpjJkHoLtt/f+jSybyV7zx/q/iCHdRkviC0xhgABbm6Js dIiw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=Aj7bIRpBxLE/QbhIHFv2D/FvUghNvupNjdDm/EaW0wk=; b=WC5OfcoPD+8BO4TxOQ88JgPqlUfEO3UeP62L0hKJwJAHWkRgAMJweOzVX8jRxmtoc5 kxg0jPtjh9FWHIu+Zdna0TG1Dm1i2aA+hYxEbFGNhjdA5ykcciTYhugEnJVB9pwC/fBO rjNvlI78vMrMAYIHX89vLlGh4ncF1pPmaorB5KnTUwSgLLPmthq3O8TqXUNrf6CYH0TJ z+Qhf0l0cuPcSLhh2lZcfZnIxsGAg0fzznqjvnTQ/IB/mk3B8xwxaxF0+ZzK5a9DQk8S HiRqawt0fnSIDY2Zx/hjLrriV41zGqfw0XmM/C+5I8Sw5oEnTUM+z0EhRy4FWlJ1HEzc I/jQ== X-Gm-Message-State: ACgBeo2Jy0y4ru+9qFbPUYICX5HKhG0SVW1JWgRLS7KajJvgBVPQkXvQ R5sL6UpqOFKsXLiAAv1Pf2J5 X-Google-Smtp-Source: AA6agR5urAjbeR+oCpeOsDAG3lUolXvFDjzepvOgGtvARILTv9Et4w7Z6k7r7s0KasDqImWeJEh2cQ== X-Received: by 2002:a17:90a:bb96:b0:1f4:414a:d89e with SMTP id v22-20020a17090abb9600b001f4414ad89emr8230563pjr.240.1660212579470; Thu, 11 Aug 2022 03:09:39 -0700 (PDT) Received: from localhost.localdomain ([59.92.103.103]) by smtp.gmail.com with ESMTPSA id 1-20020a621501000000b0052b9351737fsm3714839pfv.92.2022.08.11.03.09.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Aug 2022 03:09:39 -0700 (PDT) From: Manivannan Sadhasivam To: bjorn.andersson@linaro.org, ckadabi@quicinc.com, vnkgutta@quicinc.com, bp@alien8.de, mchehab@kernel.org Cc: james.morse@arm.com, rric@kernel.org, linux-arm-msm@vger.kernel.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH 1/2] soc: qcom: llcc: Pass SoC specific EDAC register offsets to EDAC driver Date: Thu, 11 Aug 2022 15:39:23 +0530 Message-Id: <20220811100924.79505-2-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220811100924.79505-1-manivannan.sadhasivam@linaro.org> References: <20220811100924.79505-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The LLCC EDAC register offsets varies between each SoCs. Until now, the EDAC driver used the hardcoded register offsets. But this caused crash on SM8450 SoC where the register offsets has been changed. So to avoid this crash and also to make it easy to accommodate changes for new SoCs, let's pass the SoC specific register offsets to the EDAC driver. Currently, two set of offsets are used. One is SM8450 specific and another one is common to all SoCs. Signed-off-by: Manivannan Sadhasivam --- drivers/soc/qcom/llcc-qcom.c | 64 ++++++++++++++++++++++++++++++++++++ 1 file changed, 64 insertions(+) diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c index eecafeded56f..1aedbbb8e96f 100644 --- a/drivers/soc/qcom/llcc-qcom.c +++ b/drivers/soc/qcom/llcc-qcom.c @@ -104,6 +104,7 @@ struct qcom_llcc_config { int size; bool need_llcc_cfg; const u32 *reg_offset; + const struct llcc_edac_reg *edac_reg; }; =20 enum llcc_reg_offset { @@ -252,6 +253,60 @@ static const struct llcc_slice_config sm8450_data[] = =3D { {LLCC_AENPU, 8, 2048, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0 }, }; =20 +static const struct llcc_edac_reg common_edac_reg =3D { + .trp_ecc_error_status0 =3D 0x20344, + .trp_ecc_error_status1 =3D 0x20348, + .trp_ecc_sb_err_syn0 =3D 0x2304c, + .trp_ecc_db_err_syn0 =3D 0x20370, + .trp_ecc_error_cntr_clear =3D 0x20440, + .trp_interrupt_0_status =3D 0x20480, + .trp_interrupt_0_clear =3D 0x20484, + .trp_interrupt_0_enable =3D 0x20488, + + /* LLCC Common registers */ + .cmn_status0 =3D 0x3000c, + .cmn_interrupt_0_enable =3D 0x3001c, + .cmn_interrupt_2_enable =3D 0x3003c, + + /* LLCC DRP registers */ + .drp_ecc_error_cfg =3D 0x40000, + .drp_ecc_error_cntr_clear =3D 0x40004, + .drp_interrupt_status =3D 0x41000, + .drp_interrupt_clear =3D 0x41008, + .drp_interrupt_enable =3D 0x4100c, + .drp_ecc_error_status0 =3D 0x42044, + .drp_ecc_error_status1 =3D 0x42048, + .drp_ecc_sb_err_syn0 =3D 0x4204c, + .drp_ecc_db_err_syn0 =3D 0x42070, +}; + +static const struct llcc_edac_reg sm8450_edac_reg =3D { + .trp_ecc_error_status0 =3D 0x20344, + .trp_ecc_error_status1 =3D 0x20348, + .trp_ecc_sb_err_syn0 =3D 0x2034c, + .trp_ecc_db_err_syn0 =3D 0x20370, + .trp_ecc_error_cntr_clear =3D 0x20440, + .trp_interrupt_0_status =3D 0x20480, + .trp_interrupt_0_clear =3D 0x20484, + .trp_interrupt_0_enable =3D 0x20488, + + /* LLCC Common registers */ + .cmn_status0 =3D 0x3400c, + .cmn_interrupt_0_enable =3D 0x3401c, + .cmn_interrupt_2_enable =3D 0x3403c, + + /* LLCC DRP registers */ + .drp_ecc_error_cfg =3D 0x50000, + .drp_ecc_error_cntr_clear =3D 0x50004, + .drp_interrupt_status =3D 0x50020, + .drp_interrupt_clear =3D 0x50028, + .drp_interrupt_enable =3D 0x5002c, + .drp_ecc_error_status0 =3D 0x520f4, + .drp_ecc_error_status1 =3D 0x520f8, + .drp_ecc_sb_err_syn0 =3D 0x520fc, + .drp_ecc_db_err_syn0 =3D 0x52120, +}; + static const u32 llcc_v1_2_reg_offset[] =3D { [LLCC_COMMON_HW_INFO] =3D 0x00030000, [LLCC_COMMON_STATUS0] =3D 0x0003000c, @@ -267,6 +322,7 @@ static const struct qcom_llcc_config sc7180_cfg =3D { .size =3D ARRAY_SIZE(sc7180_data), .need_llcc_cfg =3D true, .reg_offset =3D llcc_v1_2_reg_offset, + .edac_reg =3D &common_edac_reg, }; =20 static const struct qcom_llcc_config sc7280_cfg =3D { @@ -274,6 +330,7 @@ static const struct qcom_llcc_config sc7280_cfg =3D { .size =3D ARRAY_SIZE(sc7280_data), .need_llcc_cfg =3D true, .reg_offset =3D llcc_v1_2_reg_offset, + .edac_reg =3D &common_edac_reg, }; =20 static const struct qcom_llcc_config sdm845_cfg =3D { @@ -281,6 +338,7 @@ static const struct qcom_llcc_config sdm845_cfg =3D { .size =3D ARRAY_SIZE(sdm845_data), .need_llcc_cfg =3D false, .reg_offset =3D llcc_v1_2_reg_offset, + .edac_reg =3D &common_edac_reg, }; =20 static const struct qcom_llcc_config sm6350_cfg =3D { @@ -288,6 +346,7 @@ static const struct qcom_llcc_config sm6350_cfg =3D { .size =3D ARRAY_SIZE(sm6350_data), .need_llcc_cfg =3D true, .reg_offset =3D llcc_v1_2_reg_offset, + .edac_reg =3D &common_edac_reg, }; =20 static const struct qcom_llcc_config sm8150_cfg =3D { @@ -295,6 +354,7 @@ static const struct qcom_llcc_config sm8150_cfg =3D { .size =3D ARRAY_SIZE(sm8150_data), .need_llcc_cfg =3D true, .reg_offset =3D llcc_v1_2_reg_offset, + .edac_reg =3D &common_edac_reg, }; =20 static const struct qcom_llcc_config sm8250_cfg =3D { @@ -302,6 +362,7 @@ static const struct qcom_llcc_config sm8250_cfg =3D { .size =3D ARRAY_SIZE(sm8250_data), .need_llcc_cfg =3D true, .reg_offset =3D llcc_v1_2_reg_offset, + .edac_reg =3D &common_edac_reg, }; =20 static const struct qcom_llcc_config sm8350_cfg =3D { @@ -309,6 +370,7 @@ static const struct qcom_llcc_config sm8350_cfg =3D { .size =3D ARRAY_SIZE(sm8350_data), .need_llcc_cfg =3D true, .reg_offset =3D llcc_v1_2_reg_offset, + .edac_reg =3D &common_edac_reg, }; =20 static const struct qcom_llcc_config sm8450_cfg =3D { @@ -316,6 +378,7 @@ static const struct qcom_llcc_config sm8450_cfg =3D { .size =3D ARRAY_SIZE(sm8450_data), .need_llcc_cfg =3D true, .reg_offset =3D llcc_v21_reg_offset, + .edac_reg =3D &sm8450_edac_reg, }; =20 static struct llcc_drv_data *drv_data =3D (void *) -EPROBE_DEFER; @@ -716,6 +779,7 @@ static int qcom_llcc_probe(struct platform_device *pdev) =20 drv_data->cfg =3D llcc_cfg; drv_data->cfg_size =3D sz; + drv_data->edac_reg =3D cfg->edac_reg; mutex_init(&drv_data->lock); platform_set_drvdata(pdev, drv_data); =20 --=20 2.25.1 From nobody Sat Apr 11 12:37:10 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 95C94C19F2A for ; Thu, 11 Aug 2022 10:10:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234989AbiHKKKL (ORCPT ); Thu, 11 Aug 2022 06:10:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46624 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234713AbiHKKJv (ORCPT ); Thu, 11 Aug 2022 06:09:51 -0400 Received: from mail-pj1-x102e.google.com (mail-pj1-x102e.google.com [IPv6:2607:f8b0:4864:20::102e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 50584923D1 for ; Thu, 11 Aug 2022 03:09:45 -0700 (PDT) Received: by mail-pj1-x102e.google.com with SMTP id w11-20020a17090a380b00b001f73f75a1feso4885015pjb.2 for ; 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Thu, 11 Aug 2022 03:09:44 -0700 (PDT) Received: from localhost.localdomain ([59.92.103.103]) by smtp.gmail.com with ESMTPSA id 1-20020a621501000000b0052b9351737fsm3714839pfv.92.2022.08.11.03.09.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Aug 2022 03:09:43 -0700 (PDT) From: Manivannan Sadhasivam To: bjorn.andersson@linaro.org, ckadabi@quicinc.com, vnkgutta@quicinc.com, bp@alien8.de, mchehab@kernel.org Cc: james.morse@arm.com, rric@kernel.org, linux-arm-msm@vger.kernel.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH 2/2] EDAC/qcom: Get rid of hardcoded register offsets Date: Thu, 11 Aug 2022 15:39:24 +0530 Message-Id: <20220811100924.79505-3-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220811100924.79505-1-manivannan.sadhasivam@linaro.org> References: <20220811100924.79505-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The LLCC EDAC register offsets varies between each SoC. Hardcoding the register offsets won't work and will often result in crash due to accessing the wrong locations. Hence, get the register offsets from the LLCC driver matching the individual SoCs. Signed-off-by: Manivannan Sadhasivam --- drivers/edac/qcom_edac.c | 112 ++++++++++++++--------------- include/linux/soc/qcom/llcc-qcom.h | 35 +++++++-- 2 files changed, 83 insertions(+), 64 deletions(-) diff --git a/drivers/edac/qcom_edac.c b/drivers/edac/qcom_edac.c index 97a27e42dd61..500360cc5258 100644 --- a/drivers/edac/qcom_edac.c +++ b/drivers/edac/qcom_edac.c @@ -21,30 +21,9 @@ #define TRP_SYN_REG_CNT 6 #define DRP_SYN_REG_CNT 8 =20 -#define LLCC_COMMON_STATUS0 0x0003000c #define LLCC_LB_CNT_MASK GENMASK(31, 28) #define LLCC_LB_CNT_SHIFT 28 =20 -/* Single & double bit syndrome register offsets */ -#define TRP_ECC_SB_ERR_SYN0 0x0002304c -#define TRP_ECC_DB_ERR_SYN0 0x00020370 -#define DRP_ECC_SB_ERR_SYN0 0x0004204c -#define DRP_ECC_DB_ERR_SYN0 0x00042070 - -/* Error register offsets */ -#define TRP_ECC_ERROR_STATUS1 0x00020348 -#define TRP_ECC_ERROR_STATUS0 0x00020344 -#define DRP_ECC_ERROR_STATUS1 0x00042048 -#define DRP_ECC_ERROR_STATUS0 0x00042044 - -/* TRP, DRP interrupt register offsets */ -#define DRP_INTERRUPT_STATUS 0x00041000 -#define TRP_INTERRUPT_0_STATUS 0x00020480 -#define DRP_INTERRUPT_CLEAR 0x00041008 -#define DRP_ECC_ERROR_CNTR_CLEAR 0x00040004 -#define TRP_INTERRUPT_0_CLEAR 0x00020484 -#define TRP_ECC_ERROR_CNTR_CLEAR 0x00020440 - /* Mask and shift macros */ #define ECC_DB_ERR_COUNT_MASK GENMASK(4, 0) #define ECC_DB_ERR_WAYS_MASK GENMASK(31, 16) @@ -60,15 +39,6 @@ #define DRP_TRP_INT_CLEAR GENMASK(1, 0) #define DRP_TRP_CNT_CLEAR GENMASK(1, 0) =20 -/* Config registers offsets*/ -#define DRP_ECC_ERROR_CFG 0x00040000 - -/* Tag RAM, Data RAM interrupt register offsets */ -#define CMN_INTERRUPT_0_ENABLE 0x0003001c -#define CMN_INTERRUPT_2_ENABLE 0x0003003c -#define TRP_INTERRUPT_0_ENABLE 0x00020488 -#define DRP_INTERRUPT_ENABLE 0x0004100c - #define SB_ERROR_THRESHOLD 0x1 #define SB_ERROR_THRESHOLD_SHIFT 24 #define SB_DB_TRP_INTERRUPT_ENABLE 0x3 @@ -86,9 +56,6 @@ enum { static const struct llcc_edac_reg_data edac_reg_data[] =3D { [LLCC_DRAM_CE] =3D { .name =3D "DRAM Single-bit", - .synd_reg =3D DRP_ECC_SB_ERR_SYN0, - .count_status_reg =3D DRP_ECC_ERROR_STATUS1, - .ways_status_reg =3D DRP_ECC_ERROR_STATUS0, .reg_cnt =3D DRP_SYN_REG_CNT, .count_mask =3D ECC_SB_ERR_COUNT_MASK, .ways_mask =3D ECC_SB_ERR_WAYS_MASK, @@ -96,9 +63,6 @@ static const struct llcc_edac_reg_data edac_reg_data[] = =3D { }, [LLCC_DRAM_UE] =3D { .name =3D "DRAM Double-bit", - .synd_reg =3D DRP_ECC_DB_ERR_SYN0, - .count_status_reg =3D DRP_ECC_ERROR_STATUS1, - .ways_status_reg =3D DRP_ECC_ERROR_STATUS0, .reg_cnt =3D DRP_SYN_REG_CNT, .count_mask =3D ECC_DB_ERR_COUNT_MASK, .ways_mask =3D ECC_DB_ERR_WAYS_MASK, @@ -106,9 +70,6 @@ static const struct llcc_edac_reg_data edac_reg_data[] = =3D { }, [LLCC_TRAM_CE] =3D { .name =3D "TRAM Single-bit", - .synd_reg =3D TRP_ECC_SB_ERR_SYN0, - .count_status_reg =3D TRP_ECC_ERROR_STATUS1, - .ways_status_reg =3D TRP_ECC_ERROR_STATUS0, .reg_cnt =3D TRP_SYN_REG_CNT, .count_mask =3D ECC_SB_ERR_COUNT_MASK, .ways_mask =3D ECC_SB_ERR_WAYS_MASK, @@ -116,9 +77,6 @@ static const struct llcc_edac_reg_data edac_reg_data[] = =3D { }, [LLCC_TRAM_UE] =3D { .name =3D "TRAM Double-bit", - .synd_reg =3D TRP_ECC_DB_ERR_SYN0, - .count_status_reg =3D TRP_ECC_ERROR_STATUS1, - .ways_status_reg =3D TRP_ECC_ERROR_STATUS0, .reg_cnt =3D TRP_SYN_REG_CNT, .count_mask =3D ECC_DB_ERR_COUNT_MASK, .ways_mask =3D ECC_DB_ERR_WAYS_MASK, @@ -126,7 +84,7 @@ static const struct llcc_edac_reg_data edac_reg_data[] = =3D { }, }; =20 -static int qcom_llcc_core_setup(struct regmap *llcc_bcast_regmap) +static int qcom_llcc_core_setup(struct llcc_drv_data *drv, struct regmap *= llcc_bcast_regmap) { u32 sb_err_threshold; int ret; @@ -135,31 +93,31 @@ static int qcom_llcc_core_setup(struct regmap *llcc_bc= ast_regmap) * Configure interrupt enable registers such that Tag, Data RAM related * interrupts are propagated to interrupt controller for servicing */ - ret =3D regmap_update_bits(llcc_bcast_regmap, CMN_INTERRUPT_2_ENABLE, + ret =3D regmap_update_bits(llcc_bcast_regmap, drv->edac_reg->cmn_interrup= t_2_enable, TRP0_INTERRUPT_ENABLE, TRP0_INTERRUPT_ENABLE); if (ret) return ret; =20 - ret =3D regmap_update_bits(llcc_bcast_regmap, TRP_INTERRUPT_0_ENABLE, + ret =3D regmap_update_bits(llcc_bcast_regmap, drv->edac_reg->trp_interrup= t_0_enable, SB_DB_TRP_INTERRUPT_ENABLE, SB_DB_TRP_INTERRUPT_ENABLE); if (ret) return ret; =20 sb_err_threshold =3D (SB_ERROR_THRESHOLD << SB_ERROR_THRESHOLD_SHIFT); - ret =3D regmap_write(llcc_bcast_regmap, DRP_ECC_ERROR_CFG, + ret =3D regmap_write(llcc_bcast_regmap, drv->edac_reg->drp_ecc_error_cfg, sb_err_threshold); if (ret) return ret; =20 - ret =3D regmap_update_bits(llcc_bcast_regmap, CMN_INTERRUPT_2_ENABLE, + ret =3D regmap_update_bits(llcc_bcast_regmap, drv->edac_reg->cmn_interrup= t_2_enable, DRP0_INTERRUPT_ENABLE, DRP0_INTERRUPT_ENABLE); if (ret) return ret; =20 - ret =3D regmap_write(llcc_bcast_regmap, DRP_INTERRUPT_ENABLE, + ret =3D regmap_write(llcc_bcast_regmap, drv->edac_reg->drp_interrupt_enab= le, SB_DB_DRP_INTERRUPT_ENABLE); return ret; } @@ -173,24 +131,24 @@ qcom_llcc_clear_error_status(int err_type, struct llc= c_drv_data *drv) switch (err_type) { case LLCC_DRAM_CE: case LLCC_DRAM_UE: - ret =3D regmap_write(drv->bcast_regmap, DRP_INTERRUPT_CLEAR, + ret =3D regmap_write(drv->bcast_regmap, drv->edac_reg->drp_interrupt_cle= ar, DRP_TRP_INT_CLEAR); if (ret) return ret; =20 - ret =3D regmap_write(drv->bcast_regmap, DRP_ECC_ERROR_CNTR_CLEAR, + ret =3D regmap_write(drv->bcast_regmap, drv->edac_reg->drp_ecc_error_cnt= r_clear, DRP_TRP_CNT_CLEAR); if (ret) return ret; break; case LLCC_TRAM_CE: case LLCC_TRAM_UE: - ret =3D regmap_write(drv->bcast_regmap, TRP_INTERRUPT_0_CLEAR, + ret =3D regmap_write(drv->bcast_regmap, drv->edac_reg->trp_interrupt_0_c= lear, DRP_TRP_INT_CLEAR); if (ret) return ret; =20 - ret =3D regmap_write(drv->bcast_regmap, TRP_ECC_ERROR_CNTR_CLEAR, + ret =3D regmap_write(drv->bcast_regmap, drv->edac_reg->trp_ecc_error_cnt= r_clear, DRP_TRP_CNT_CLEAR); if (ret) return ret; @@ -203,16 +161,54 @@ qcom_llcc_clear_error_status(int err_type, struct llc= c_drv_data *drv) return ret; } =20 +struct qcom_llcc_syn_regs { + u32 synd_reg; + u32 count_status_reg; + u32 ways_status_reg; +}; + +static void get_reg_offsets(struct llcc_drv_data *drv, int err_type, + struct qcom_llcc_syn_regs *syn_regs) +{ + const struct llcc_edac_reg *edac_reg =3D drv->edac_reg; + + switch (err_type) { + case LLCC_DRAM_CE: + syn_regs->synd_reg =3D edac_reg->drp_ecc_sb_err_syn0; + syn_regs->count_status_reg =3D edac_reg->drp_ecc_error_status1; + syn_regs->ways_status_reg =3D edac_reg->drp_ecc_error_status0; + break; + case LLCC_DRAM_UE: + syn_regs->synd_reg =3D edac_reg->drp_ecc_db_err_syn0; + syn_regs->count_status_reg =3D edac_reg->drp_ecc_error_status1; + syn_regs->ways_status_reg =3D edac_reg->drp_ecc_error_status0; + break; + case LLCC_TRAM_CE: + syn_regs->synd_reg =3D edac_reg->trp_ecc_sb_err_syn0; + syn_regs->count_status_reg =3D edac_reg->trp_ecc_error_status1; + syn_regs->ways_status_reg =3D edac_reg->trp_ecc_error_status0; + break; + case LLCC_TRAM_UE: + syn_regs->synd_reg =3D edac_reg->trp_ecc_db_err_syn0; + syn_regs->count_status_reg =3D edac_reg->trp_ecc_error_status1; + syn_regs->ways_status_reg =3D edac_reg->trp_ecc_error_status0; + break; + } +} + /* Dump Syndrome registers data for Tag RAM, Data RAM bit errors*/ static int dump_syn_reg_values(struct llcc_drv_data *drv, u32 bank, int err_type) { struct llcc_edac_reg_data reg_data =3D edac_reg_data[err_type]; + struct qcom_llcc_syn_regs regs =3D { }; int err_cnt, err_ways, ret, i; u32 synd_reg, synd_val; =20 + get_reg_offsets(drv, err_type, ®s); + for (i =3D 0; i < reg_data.reg_cnt; i++) { - synd_reg =3D reg_data.synd_reg + (i * 4); + synd_reg =3D regs.synd_reg + (i * 4); ret =3D regmap_read(drv->regmap, drv->offsets[bank] + synd_reg, &synd_val); if (ret) @@ -223,7 +219,7 @@ dump_syn_reg_values(struct llcc_drv_data *drv, u32 bank= , int err_type) } =20 ret =3D regmap_read(drv->regmap, - drv->offsets[bank] + reg_data.count_status_reg, + drv->offsets[bank] + regs.count_status_reg, &err_cnt); if (ret) goto clear; @@ -234,7 +230,7 @@ dump_syn_reg_values(struct llcc_drv_data *drv, u32 bank= , int err_type) reg_data.name, err_cnt); =20 ret =3D regmap_read(drv->regmap, - drv->offsets[bank] + reg_data.ways_status_reg, + drv->offsets[bank] + regs.ways_status_reg, &err_ways); if (ret) goto clear; @@ -297,7 +293,7 @@ llcc_ecc_irq_handler(int irq, void *edev_ctl) /* Iterate over the banks and look for Tag RAM or Data RAM errors */ for (i =3D 0; i < drv->num_banks; i++) { ret =3D regmap_read(drv->regmap, - drv->offsets[i] + DRP_INTERRUPT_STATUS, + drv->offsets[i] + drv->edac_reg->drp_interrupt_status, &drp_error); =20 if (!ret && (drp_error & SB_ECC_ERROR)) { @@ -313,7 +309,7 @@ llcc_ecc_irq_handler(int irq, void *edev_ctl) irq_rc =3D IRQ_HANDLED; =20 ret =3D regmap_read(drv->regmap, - drv->offsets[i] + TRP_INTERRUPT_0_STATUS, + drv->offsets[i] + drv->edac_reg->trp_interrupt_0_status, &trp_error); =20 if (!ret && (trp_error & SB_ECC_ERROR)) { @@ -340,7 +336,7 @@ static int qcom_llcc_edac_probe(struct platform_device = *pdev) int ecc_irq; int rc; =20 - rc =3D qcom_llcc_core_setup(llcc_driv_data->bcast_regmap); + rc =3D qcom_llcc_core_setup(llcc_driv_data, llcc_driv_data->bcast_regmap); if (rc) return rc; =20 diff --git a/include/linux/soc/qcom/llcc-qcom.h b/include/linux/soc/qcom/ll= cc-qcom.h index 0bc21ee58fac..a36ed7ffcb28 100644 --- a/include/linux/soc/qcom/llcc-qcom.h +++ b/include/linux/soc/qcom/llcc-qcom.h @@ -55,9 +55,6 @@ struct llcc_slice_desc { /** * struct llcc_edac_reg_data - llcc edac registers data for each error type * @name: Name of the error - * @synd_reg: Syndrome register address - * @count_status_reg: Status register address to read the error count - * @ways_status_reg: Status register address to read the error ways * @reg_cnt: Number of registers * @count_mask: Mask value to get the error count * @ways_mask: Mask value to get the error ways @@ -66,9 +63,6 @@ struct llcc_slice_desc { */ struct llcc_edac_reg_data { char *name; - u64 synd_reg; - u64 count_status_reg; - u64 ways_status_reg; u32 reg_cnt; u32 count_mask; u32 ways_mask; @@ -76,6 +70,34 @@ struct llcc_edac_reg_data { u8 ways_shift; }; =20 +struct llcc_edac_reg { + /* LLCC TRP registers */ + u32 trp_ecc_error_status0; + u32 trp_ecc_error_status1; + u32 trp_ecc_sb_err_syn0; + u32 trp_ecc_db_err_syn0; + u32 trp_ecc_error_cntr_clear; + u32 trp_interrupt_0_status; + u32 trp_interrupt_0_clear; + u32 trp_interrupt_0_enable; + + /* LLCC Common registers */ + u32 cmn_status0; + u32 cmn_interrupt_0_enable; + u32 cmn_interrupt_2_enable; + + /* LLCC DRP registers */ + u32 drp_ecc_error_cfg; + u32 drp_ecc_error_cntr_clear; + u32 drp_interrupt_status; + u32 drp_interrupt_clear; + u32 drp_interrupt_enable; + u32 drp_ecc_error_status0; + u32 drp_ecc_error_status1; + u32 drp_ecc_sb_err_syn0; + u32 drp_ecc_db_err_syn0; +}; + /** * struct llcc_drv_data - Data associated with the llcc driver * @regmap: regmap associated with the llcc device @@ -94,6 +116,7 @@ struct llcc_drv_data { struct regmap *regmap; struct regmap *bcast_regmap; const struct llcc_slice_config *cfg; + const struct llcc_edac_reg *edac_reg; struct mutex lock; u32 cfg_size; u32 max_slices; --=20 2.25.1