From nobody Sat Sep 21 12:34:15 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B8F8EC00140 for ; Thu, 11 Aug 2022 02:59:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233978AbiHKC7c (ORCPT ); Wed, 10 Aug 2022 22:59:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43618 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233857AbiHKC6a (ORCPT ); Wed, 10 Aug 2022 22:58:30 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A66A588DF0; Wed, 10 Aug 2022 19:58:28 -0700 (PDT) X-UUID: e6d3ceb71e3444ce91dfc2c5031b5a15-20220811 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=m3LxbjBoy1BY6MSqcBMbHIG1A6UL3+xTam2MqJhnv60=; b=L+ZUgAgtX4s+gU0xwcqyQhkzT34W8VL0Nzmndml/dZ/qIk7Lm/f1DBH31lTEHaCIxUf+QQv/u+2VYp+sv2jj4e9SUSGjsp56+aMcH4xV/NZvB0qeLCQiwIKnj1Bt5aBsErSKtLtXDltCJM1oL1f0AOQDPDeTn6Vow09DdsNfdVU=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.9,REQID:5872cff8-a929-41c3-a6e3-3462227f98ed,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_H am,ACTION:release,TS:0 X-CID-META: VersionHash:3d8acc9,CLOUDID:1f9afafc-9e71-4a0f-ba6b-417998daea35,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil ,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: e6d3ceb71e3444ce91dfc2c5031b5a15-20220811 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 702463917; Thu, 11 Aug 2022 10:58:16 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Thu, 11 Aug 2022 10:58:15 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Thu, 11 Aug 2022 10:58:15 +0800 From: Tinghan Shen To: Yong Wu , Joerg Roedel , Will Deacon , Robin Murphy , Rob Herring , Krzysztof Kozlowski , Lee Jones , Matthias Brugger , AngeloGioacchino Del Regno , Tinghan Shen , MandyJH Liu CC: , , , , , Subject: [PATCH v6 03/20] dt-bindings: power: mediatek: Refine multiple level power domain nodes Date: Thu, 11 Aug 2022 10:57:56 +0800 Message-ID: <20220811025813.21492-4-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220811025813.21492-1-tinghan.shen@mediatek.com> References: <20220811025813.21492-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Extract duplicated properties and support more levels of power domain nodes. This change fix following error when do dtbs_check, arch/arm64/boot/dts/mediatek/mt8195-evb.dtb: power-controller: power-do= main@15:power-domain@16:power-domain@18: 'power-domain@19', 'power-domain@2= 0', 'power-domain@21' do not match any of the regexes: 'pinctrl-[0-9]+' From schema: Documentation/devicetree/bindings/power/mediatek,power-contr= oller.yaml Signed-off-by: Tinghan Shen Reviewed-by: Krzysztof Kozlowski Reviewed-by: AngeloGioacchino Del Regno --- .../power/mediatek,power-controller.yaml | 131 +++--------------- 1 file changed, 17 insertions(+), 114 deletions(-) diff --git a/Documentation/devicetree/bindings/power/mediatek,power-control= ler.yaml b/Documentation/devicetree/bindings/power/mediatek,power-controlle= r.yaml index b448101fac43e..321802c95308f 100644 --- a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml +++ b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml @@ -42,6 +42,23 @@ properties: =20 patternProperties: "^power-domain@[0-9a-f]+$": + $ref: "#/$defs/power-domain-node" + patternProperties: + "^power-domain@[0-9a-f]+$": + $ref: "#/$defs/power-domain-node" + patternProperties: + "^power-domain@[0-9a-f]+$": + $ref: "#/$defs/power-domain-node" + patternProperties: + "^power-domain@[0-9a-f]+$": + $ref: "#/$defs/power-domain-node" + unevaluatedProperties: false + unevaluatedProperties: false + unevaluatedProperties: false + unevaluatedProperties: false + +$defs: + power-domain-node: type: object description: | Represents the power domains within the power controller node as doc= umented @@ -100,123 +117,9 @@ patternProperties: $ref: /schemas/types.yaml#/definitions/phandle description: phandle to the device containing the SMI register ran= ge. =20 - patternProperties: - "^power-domain@[0-9a-f]+$": - type: object - description: | - Represents a power domain child within a power domain parent nod= e. - - properties: - - '#power-domain-cells': - description: - Must be 0 for nodes representing a single PM domain and 1 fo= r nodes - providing multiple PM domains. - - '#address-cells': - const: 1 - - '#size-cells': - const: 0 - - reg: - maxItems: 1 - - clocks: - description: | - A number of phandles to clocks that need to be enabled durin= g domain - power-up sequencing. - - clock-names: - description: | - List of names of clocks, in order to match the power-up sequ= encing - for each power domain we need to group the clocks by name. B= ASIC - clocks need to be enabled before enabling the corresponding = power - domain, and should not have a '-' in their name (i.e mm, mfg= , venc). - SUSBYS clocks need to be enabled before releasing the bus pr= otection, - and should contain a '-' in their name (i.e mm-0, isp-0, cam= -0). - - In order to follow properly the power-up sequencing, the clo= cks must - be specified by order, adding first the BASIC clocks followe= d by the - SUSBSYS clocks. - - domain-supply: - description: domain regulator supply. - - mediatek,infracfg: - $ref: /schemas/types.yaml#/definitions/phandle - description: phandle to the device containing the INFRACFG reg= ister range. - - mediatek,smi: - $ref: /schemas/types.yaml#/definitions/phandle - description: phandle to the device containing the SMI register= range. - - patternProperties: - "^power-domain@[0-9a-f]+$": - type: object - description: | - Represents a power domain child within a power domain parent= node. - - properties: - - '#power-domain-cells': - description: - Must be 0 for nodes representing a single PM domain and = 1 for nodes - providing multiple PM domains. - - '#address-cells': - const: 1 - - '#size-cells': - const: 0 - - reg: - maxItems: 1 - - clocks: - description: | - A number of phandles to clocks that need to be enabled d= uring domain - power-up sequencing. - - clock-names: - description: | - List of names of clocks, in order to match the power-up = sequencing - for each power domain we need to group the clocks by nam= e. BASIC - clocks need to be enabled before enabling the correspond= ing power - domain, and should not have a '-' in their name (i.e mm,= mfg, venc). - SUSBYS clocks need to be enabled before releasing the bu= s protection, - and should contain a '-' in their name (i.e mm-0, isp-0,= cam-0). - - In order to follow properly the power-up sequencing, the= clocks must - be specified by order, adding first the BASIC clocks fol= lowed by the - SUSBSYS clocks. - - domain-supply: - description: domain regulator supply. - - mediatek,infracfg: - $ref: /schemas/types.yaml#/definitions/phandle - description: phandle to the device containing the INFRACFG= register range. - - mediatek,smi: - $ref: /schemas/types.yaml#/definitions/phandle - description: phandle to the device containing the SMI regi= ster range. - - required: - - reg - - additionalProperties: false - - required: - - reg - - additionalProperties: false - required: - reg =20 - additionalProperties: false - required: - compatible =20 --=20 2.18.0