From nobody Sat Sep 21 11:32:24 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 32FDBC00140 for ; Thu, 11 Aug 2022 02:59:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233922AbiHKC7M (ORCPT ); Wed, 10 Aug 2022 22:59:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43628 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233851AbiHKC63 (ORCPT ); Wed, 10 Aug 2022 22:58:29 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D4A9688DFE; Wed, 10 Aug 2022 19:58:27 -0700 (PDT) X-UUID: f8ba34885e03423bbde3b1333071baee-20220811 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=3FYR+5ZW4CIrtsZvCxAgmMQuxKgtGBhsYBdi1e7Felo=; b=rXrrttmJqMH2jlRTrYgctfU4f9v+uS9ojd09deVGP9exsDiUnCxqoN5Za95cjq3gAJEJUNAnxkK1o8shGFof5np/Q+6z7TgjZu5XjgOOOlANlKaItlggWChYHTrNI8nEWG+bKRmqmVwbmAbXfzSy4dPhKLvFCPMPht+JJUS4O4A=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.9,REQID:848a73cd-12ab-4315-a143-f5c0ed243e9f,OB:20,L OB:30,IP:0,URL:0,TC:0,Content:-5,EDM:0,RT:0,SF:100,FILE:0,BULK:0,RULE:Rele ase_Ham,ACTION:release,TS:95 X-CID-INFO: VERSION:1.1.9,REQID:848a73cd-12ab-4315-a143-f5c0ed243e9f,OB:20,LOB :30,IP:0,URL:0,TC:0,Content:-5,EDM:0,RT:0,SF:100,FILE:0,BULK:0,RULE:Spam_G S981B3D,ACTION:quarantine,TS:95 X-CID-META: VersionHash:3d8acc9,CLOUDID:d4a1559c-da39-4e3b-a854-56c7d2111b46,C OID:6b8a0955923b,Recheck:0,SF:28|17|19|48,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: f8ba34885e03423bbde3b1333071baee-20220811 Received: from mtkcas11.mediatek.inc [(172.21.101.40)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1588176073; Thu, 11 Aug 2022 10:58:17 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Thu, 11 Aug 2022 10:58:16 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Thu, 11 Aug 2022 10:58:16 +0800 From: Tinghan Shen To: Yong Wu , Joerg Roedel , "Will Deacon" , Robin Murphy , Rob Herring , Krzysztof Kozlowski , Lee Jones , "Matthias Brugger" , AngeloGioacchino Del Regno , Tinghan Shen , MandyJH Liu CC: , , , , , , Henry Chen Subject: [PATCH v6 13/20] arm64: dts: mt8195: Add spmi node Date: Thu, 11 Aug 2022 10:58:06 +0800 Message-ID: <20220811025813.21492-14-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220811025813.21492-1-tinghan.shen@mediatek.com> References: <20220811025813.21492-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add spmi node to mt8195. Signed-off-by: Henry Chen Signed-off-by: Tinghan Shen Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts= /mediatek/mt8195.dtsi index 7e77aecb1296e..da2d976ff8441 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -697,6 +697,21 @@ assigned-clock-parents =3D <&topckgen CLK_TOP_ULPOSC1_D10>; }; =20 + spmi: spmi@10027000 { + compatible =3D "mediatek,mt8195-spmi"; + reg =3D <0 0x10027000 0 0x000e00>, + <0 0x10029000 0 0x000100>; + reg-names =3D "pmif", "spmimst"; + clocks =3D <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, + <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>, + <&topckgen CLK_TOP_SPMI_M_MST>; + clock-names =3D "pmif_sys_ck", + "pmif_tmr_ck", + "spmimst_clk_mux"; + assigned-clocks =3D <&topckgen CLK_TOP_PWRAP_ULPOSC>; + assigned-clock-parents =3D <&topckgen CLK_TOP_ULPOSC1_D10>; + }; + scp_adsp: clock-controller@10720000 { compatible =3D "mediatek,mt8195-scp_adsp"; reg =3D <0 0x10720000 0 0x1000>; --=20 2.18.0