From nobody Sat Sep 21 11:28:51 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 136BDC00140 for ; Thu, 11 Aug 2022 02:58:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233652AbiHKC6r (ORCPT ); Wed, 10 Aug 2022 22:58:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43572 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233716AbiHKC62 (ORCPT ); Wed, 10 Aug 2022 22:58:28 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D305188DF0; Wed, 10 Aug 2022 19:58:23 -0700 (PDT) X-UUID: 73347a69569e4e9d8b2cd86a42b685fe-20220811 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=XB6G09LPib0ZkaoEMPxS1Y+0TeJFHDnmpB6acMqZQUA=; b=PW3YYkbt6Qo0/XzmrJYberDIABdr+AMSVVpQvhPV3nZA8VbGQWmg/jbc8TWQbSXj9mjzxCCuLlm+fCBKWbJUoNRCqWod0evyp63ojiZGwRJuZTmBsY7QLdodc8TiAeGm7Rdnh9CTb9wl+IfGmLuCBAzo1fnjlwAXmR2ar6EJzCU=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.9,REQID:19cc2a67-f352-4945-add0-a73180b716bb,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_H am,ACTION:release,TS:0 X-CID-META: VersionHash:3d8acc9,CLOUDID:1b9afafc-9e71-4a0f-ba6b-417998daea35,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil ,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: 73347a69569e4e9d8b2cd86a42b685fe-20220811 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 555475142; Thu, 11 Aug 2022 10:58:16 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Thu, 11 Aug 2022 10:58:16 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Thu, 11 Aug 2022 10:58:16 +0800 From: Tinghan Shen To: Yong Wu , Joerg Roedel , Will Deacon , Robin Murphy , Rob Herring , Krzysztof Kozlowski , Lee Jones , Matthias Brugger , AngeloGioacchino Del Regno , Tinghan Shen , MandyJH Liu CC: , , , , , Subject: [PATCH v6 11/20] arm64: dts: mt8195: Add vdosys and vppsys clock nodes Date: Thu, 11 Aug 2022 10:58:04 +0800 Message-ID: <20220811025813.21492-12-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220811025813.21492-1-tinghan.shen@mediatek.com> References: <20220811025813.21492-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add display clock nodes. Signed-off-by: Tinghan Shen Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts= /mediatek/mt8195.dtsi index 900aaa16f862f..8d59a7da32714 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -983,6 +983,12 @@ #clock-cells =3D <1>; }; =20 + vppsys0: clock-controller@14000000 { + compatible =3D "mediatek,mt8195-vppsys0"; + reg =3D <0 0x14000000 0 0x1000>; + #clock-cells =3D <1>; + }; + wpesys: clock-controller@14e00000 { compatible =3D "mediatek,mt8195-wpesys"; reg =3D <0 0x14e00000 0 0x1000>; @@ -1001,6 +1007,12 @@ #clock-cells =3D <1>; }; =20 + vppsys1: clock-controller@14f00000 { + compatible =3D "mediatek,mt8195-vppsys1"; + reg =3D <0 0x14f00000 0 0x1000>; + #clock-cells =3D <1>; + }; + imgsys: clock-controller@15000000 { compatible =3D "mediatek,mt8195-imgsys"; reg =3D <0 0x15000000 0 0x1000>; @@ -1108,5 +1120,17 @@ reg =3D <0 0x1b000000 0 0x1000>; #clock-cells =3D <1>; }; + + vdosys0: syscon@1c01a000 { + compatible =3D "mediatek,mt8195-mmsys", "syscon"; + reg =3D <0 0x1c01a000 0 0x1000>; + #clock-cells =3D <1>; + }; + + vdosys1: syscon@1c100000 { + compatible =3D "mediatek,mt8195-mmsys", "syscon"; + reg =3D <0 0x1c100000 0 0x1000>; + #clock-cells =3D <1>; + }; }; }; --=20 2.18.0