From nobody Sat Sep 21 11:55:00 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 63A4CC00140 for ; Thu, 11 Aug 2022 02:59:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233968AbiHKC71 (ORCPT ); Wed, 10 Aug 2022 22:59:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43590 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233846AbiHKC62 (ORCPT ); Wed, 10 Aug 2022 22:58:28 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8F74C88DF3; Wed, 10 Aug 2022 19:58:25 -0700 (PDT) X-UUID: 8aea3c5624204ba984639e88831d1977-20220811 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=2WoYmQrnfpmb4v8GtuXSjWUgeLGCFHbFVUEQVKxBuBc=; b=H6pcYHVOFg4+0MlvjKeTLEMemfnoWDyBevAWpJMG2XeAvld1P7r6yPXJrBZW7lKC2zeKR34w2CIKsSxS6IK6I4jhCjUqKV16T97G3wwOHgEn5juWw7lalaNmbITsVRXFF2B53EYzwG1v0SXm+BaOffwr3j/+xoKVcAYQPdhvCmI=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.9,REQID:560c25ab-c91e-48b3-adf1-290ad9bfe34b,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_H am,ACTION:release,TS:0 X-CID-META: VersionHash:3d8acc9,CLOUDID:ada1559c-da39-4e3b-a854-56c7d2111b46,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil ,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: 8aea3c5624204ba984639e88831d1977-20220811 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 2052867982; Thu, 11 Aug 2022 10:58:17 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Thu, 11 Aug 2022 10:58:16 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Thu, 11 Aug 2022 10:58:16 +0800 From: Tinghan Shen To: Yong Wu , Joerg Roedel , "Will Deacon" , Robin Murphy , Rob Herring , Krzysztof Kozlowski , Lee Jones , "Matthias Brugger" , AngeloGioacchino Del Regno , Tinghan Shen , MandyJH Liu CC: , , , , , , YT Lee Subject: [PATCH v6 10/20] arm64: dts: mt8195: Add cpufreq node Date: Thu, 11 Aug 2022 10:58:03 +0800 Message-ID: <20220811025813.21492-11-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220811025813.21492-1-tinghan.shen@mediatek.com> References: <20220811025813.21492-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: YT Lee Add cpufreq node for mt8195. Signed-off-by: YT Lee Signed-off-by: Tinghan Shen Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts= /mediatek/mt8195.dtsi index 8032b839dfe8d..900aaa16f862f 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -26,6 +26,7 @@ compatible =3D "arm,cortex-a55"; reg =3D <0x000>; enable-method =3D "psci"; + performance-domains =3D <&performance 0>; clock-frequency =3D <1701000000>; capacity-dmips-mhz =3D <578>; cpu-idle-states =3D <&cpu_off_l &cluster_off_l>; @@ -38,6 +39,7 @@ compatible =3D "arm,cortex-a55"; reg =3D <0x100>; enable-method =3D "psci"; + performance-domains =3D <&performance 0>; clock-frequency =3D <1701000000>; capacity-dmips-mhz =3D <578>; cpu-idle-states =3D <&cpu_off_l &cluster_off_l>; @@ -50,6 +52,7 @@ compatible =3D "arm,cortex-a55"; reg =3D <0x200>; enable-method =3D "psci"; + performance-domains =3D <&performance 0>; clock-frequency =3D <1701000000>; capacity-dmips-mhz =3D <578>; cpu-idle-states =3D <&cpu_off_l &cluster_off_l>; @@ -62,6 +65,7 @@ compatible =3D "arm,cortex-a55"; reg =3D <0x300>; enable-method =3D "psci"; + performance-domains =3D <&performance 0>; clock-frequency =3D <1701000000>; capacity-dmips-mhz =3D <578>; cpu-idle-states =3D <&cpu_off_l &cluster_off_l>; @@ -74,6 +78,7 @@ compatible =3D "arm,cortex-a78"; reg =3D <0x400>; enable-method =3D "psci"; + performance-domains =3D <&performance 1>; clock-frequency =3D <2171000000>; capacity-dmips-mhz =3D <1024>; cpu-idle-states =3D <&cpu_off_b &cluster_off_b>; @@ -86,6 +91,7 @@ compatible =3D "arm,cortex-a78"; reg =3D <0x500>; enable-method =3D "psci"; + performance-domains =3D <&performance 1>; clock-frequency =3D <2171000000>; capacity-dmips-mhz =3D <1024>; cpu-idle-states =3D <&cpu_off_b &cluster_off_b>; @@ -98,6 +104,7 @@ compatible =3D "arm,cortex-a78"; reg =3D <0x600>; enable-method =3D "psci"; + performance-domains =3D <&performance 1>; clock-frequency =3D <2171000000>; capacity-dmips-mhz =3D <1024>; cpu-idle-states =3D <&cpu_off_b &cluster_off_b>; @@ -110,6 +117,7 @@ compatible =3D "arm,cortex-a78"; reg =3D <0x700>; enable-method =3D "psci"; + performance-domains =3D <&performance 1>; clock-frequency =3D <2171000000>; capacity-dmips-mhz =3D <1024>; cpu-idle-states =3D <&cpu_off_b &cluster_off_b>; @@ -231,6 +239,12 @@ clock-output-names =3D "clk32k"; }; =20 + performance: performance-controller@11bc10 { + compatible =3D "mediatek,cpufreq-hw"; + reg =3D <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>; + #performance-domain-cells =3D <1>; + }; + pmu-a55 { compatible =3D "arm,cortex-a55-pmu"; interrupt-parent =3D <&gic>; --=20 2.18.0