From nobody Sat May 18 21:00:27 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DCA81C00140 for ; Thu, 11 Aug 2022 02:49:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233748AbiHKCtM (ORCPT ); Wed, 10 Aug 2022 22:49:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33792 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232987AbiHKCtI (ORCPT ); Wed, 10 Aug 2022 22:49:08 -0400 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 87BA588DE5 for ; Wed, 10 Aug 2022 19:49:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660186147; x=1691722147; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=3mtdp4qN/eR4cSknUV9LCDG9yQ6A0q0qYu0240TIDMY=; b=m70vrNtaQunnBQWw5wKEf0HAA6i+wRygruSjT1W9pUh5enPdjkrwF1v0 a4+1PX7g/hDzVOwJo6E2tw38wlpU7rdW2Dtek+zgYZrqeCo/GYvLJzQjh vw5z2GvoYXbiGrS7824ftTboeGaifqXyBra8uNxEpc2OR674tpf8Z7m1+ zqy78XtElbqB8HmqkDgMw6CSho2qRIW5WP3bEizN+U3whGQ/cAaPcEba4 NGhnl9aCZDykbXXH/M3V5WMtKq4rxYT+so7KlDEhcVJklz0Okfybzw62a lA37D+cRtITcHN2htbGL/fjsCq36JOwPIoDFfhDQN7RxXN+QCWEyfeYBi A==; X-IronPort-AV: E=McAfee;i="6400,9594,10435"; a="292033819" X-IronPort-AV: E=Sophos;i="5.93,228,1654585200"; d="scan'208";a="292033819" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Aug 2022 19:49:07 -0700 X-IronPort-AV: E=Sophos;i="5.93,228,1654585200"; d="scan'208";a="731712491" Received: from zjoseph-mobl3.amr.corp.intel.com (HELO localhost) ([10.209.123.207]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Aug 2022 19:49:06 -0700 From: ira.weiny@intel.com To: Rik van Riel , Borislav Petkov , Dave Hansen Cc: Ira Weiny , Dave Jones , x86@kernel.org, linux-kernel@vger.kernel.org, kernel-team@fb.com Subject: [PATCH 1/3] x86,mm: print likely CPU at segfault time Date: Wed, 10 Aug 2022 19:49:01 -0700 Message-Id: <20220811024903.178925-2-ira.weiny@intel.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220811024903.178925-1-ira.weiny@intel.com> References: <20220811024903.178925-1-ira.weiny@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Rik van Riel In a large enough fleet of computers, it is common to have a few bad CPUs. Those can often be identified by seeing that some commonly run kernel code, which runs fine everywhere else, keeps crashing on the same CPU core on one particular bad system. However, the failure modes in CPUs that have gone bad over the years are often oddly specific, and the only bad behavior seen might be segfaults in programs like bash, python, or various system daemons that run fine everywhere else. Add a printk() to show_signal_msg() to print the CPU, core, and socket at segfault time. This is not perfect, since the task might get rescheduled on another CPU between when the fault hit, and when the message is printed, but in practice this has been good enough to help us identify several bad CPU cores. segfault[1349]: segfault at 0 ip 000000000040113a sp 00007ffc6d32e360 error= 4 in segfault[401000+1000] on CPU 0 (core 0, socket 0) This printk can be controlled through /proc/sys/debug/exception-trace Tested-by: Ira Weiny Reviewed-by: Ira Weiny Signed-off-by: Rik van Riel CC: Dave Jones --- arch/x86/mm/fault.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/x86/mm/fault.c b/arch/x86/mm/fault.c index fa71a5d12e87..dbc6a2e08a96 100644 --- a/arch/x86/mm/fault.c +++ b/arch/x86/mm/fault.c @@ -769,6 +769,8 @@ show_signal_msg(struct pt_regs *regs, unsigned long err= or_code, unsigned long address, struct task_struct *tsk) { const char *loglvl =3D task_pid_nr(tsk) > 1 ? KERN_INFO : KERN_EMERG; + /* This is a racy snapshot, but it's better than nothing. */ + int cpu =3D raw_smp_processor_id(); =20 if (!unhandled_signal(tsk, SIGSEGV)) return; @@ -782,6 +784,14 @@ show_signal_msg(struct pt_regs *regs, unsigned long er= ror_code, =20 print_vma_addr(KERN_CONT " in ", regs->ip); =20 + /* + * Dump the likely CPU where the fatal segfault happened. + * This can help identify faulty hardware. + */ + printk(KERN_CONT " on CPU %d (core %d, socket %d)", cpu, + topology_core_id(cpu), topology_physical_package_id(cpu)); + + printk(KERN_CONT "\n"); =20 show_opcodes(regs, loglvl); --=20 2.35.3 From nobody Sat May 18 21:00:27 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7CC85C25B08 for ; Thu, 11 Aug 2022 02:49:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233785AbiHKCtS (ORCPT ); Wed, 10 Aug 2022 22:49:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33814 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233051AbiHKCtJ (ORCPT ); Wed, 10 Aug 2022 22:49:09 -0400 Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6431788DE9 for ; Wed, 10 Aug 2022 19:49:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660186148; x=1691722148; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=+aqelz7R2UObYo7+m0nAdTqLPIvz8yx3xgG4c//Qfbk=; b=N7GWXBA179vGPaDKylrXB7lXfZxZ5cDHfRgW//QY4OOFZjGQCs3Dzwlv Ig9s+J9ouzUJzXFz4XKWCyBg/eDxNj24Yx25fHMPPQ123zY0mgVJeX1wA cyUNv4mfkKisxiV3SKZGeKY3hjxP/Y5KIyrUcPFy2/mt6AfqsGbyEmVOD aVjqbVHf/fSlGlFgKeqOkVNmemFdJKDqnYtK9wISPg+QCNvkawfP2YZbn bqCnrjN1OsssLhtEnYo1kj+6/ItW42kxZ4H6Ipk8KO4VR4DgVTDF0Q8qD dU6tRuvkV+7hlc+15o5A5YekwvKQINPqmydIkgii0+XMC8RllsBfVqeSb w==; X-IronPort-AV: E=McAfee;i="6400,9594,10435"; a="352981561" X-IronPort-AV: E=Sophos;i="5.93,228,1654585200"; d="scan'208";a="352981561" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Aug 2022 19:49:07 -0700 X-IronPort-AV: E=Sophos;i="5.93,228,1654585200"; d="scan'208";a="638336677" Received: from zjoseph-mobl3.amr.corp.intel.com (HELO localhost) ([10.209.123.207]) by orsmga001-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Aug 2022 19:49:07 -0700 From: ira.weiny@intel.com To: Rik van Riel , Borislav Petkov , Dave Hansen Cc: Ira Weiny , Dave Hansen , Dan Williams , Peter Zijlstra , Thomas Gleixner , Andy Lutomirski , x86@kernel.org, linux-kernel@vger.kernel.org, kernel-team@fb.com Subject: [PATCH 2/3] x86/entry: Add auxiliary pt_regs space Date: Wed, 10 Aug 2022 19:49:02 -0700 Message-Id: <20220811024903.178925-3-ira.weiny@intel.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220811024903.178925-1-ira.weiny@intel.com> References: <20220811024903.178925-1-ira.weiny@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Ira Weiny Rik van Riel reports that knowledge of where a fault hits is valuable in detecting CPU failures in large data centers.[0] Having auxiliary pt_regs space is a useful place to store the CPU and avoids passing additional data through the exception call stacks. Two possible places for preserving this state were originally considered, irqentry_state_t or pt_regs.[1] pt_regs was much more complicated and was potentially fraught with unintended consequences.[2] However, Andy Lutomirski came up with a way to hide additional values on the stack which could be accessed as "extended_pt_regs".[3] This method allows any function with current access to pt_regs to obtain access to the extra information without expanding the use of irqentry_state_t and leaving pt_regs intact for compatibility with outside tools like BPF. Prepare the assembly code to add a hidden auxiliary pt_regs space. To simplify, the assembly code only adds space on the stack as defined by the C code which needs it. The use of this space is left to the C code which is required to select ARCH_HAS_PTREGS_AUXILIARY to enable this support. Each nested exception gets another copy of this auxiliary space allowing for any number of levels of exception handling. Initially the space is left empty and results in no code changes because ARCH_HAS_PTREGS_AUXILIARY is not set. Subsequent patches adding data to pt_regs_auxiliary must set ARCH_HAS_PTREGS_AUXILIARY or a build failure will occur. The use of ARCH_HAS_PTREGS_AUXILIARY also avoids the introduction of 2 instructions (addq/subq) on every entry call when the extra space is not needed. 32bit is specifically excluded. Peter, Thomas, Andy, Dave, and Dan all suggested parts of the patch or aided in the development of the patch.. [0] https://lore.kernel.org/all/20220805101644.2e674553@imladris.surriel.co= m/ [1] https://lore.kernel.org/lkml/CALCETrVe1i5JdyzD_BcctxQJn+ZE3T38EFPgjxN1F= 577M36g+w@mail.gmail.com/ [2] https://lore.kernel.org/lkml/874kpxx4jf.fsf@nanos.tec.linutronix.de/#t [3] https://lore.kernel.org/lkml/CALCETrUHwZPic89oExMMe-WyDY8-O3W68NcZvse3= =3DPGW+iW5=3Dw@mail.gmail.com/ Cc: Rik van Riel Cc: Dave Hansen Cc: Borislav Petkov Suggested-by: Dave Hansen Suggested-by: Dan Williams Suggested-by: Peter Zijlstra Suggested-by: Thomas Gleixner Suggested-by: Andy Lutomirski Signed-off-by: Ira Weiny --- Forward port from PKS series https://lore.kernel.org/lkml/20220419170649.1022246-18-ira.weiny@intel.com/ --- arch/x86/Kconfig | 4 ++++ arch/x86/entry/calling.h | 19 +++++++++++++++++++ arch/x86/entry/entry_64.S | 22 ++++++++++++++++++++++ arch/x86/entry/entry_64_compat.S | 6 ++++++ arch/x86/include/asm/ptrace.h | 18 ++++++++++++++++++ arch/x86/kernel/asm-offsets_64.c | 15 +++++++++++++++ arch/x86/kernel/head_64.S | 6 ++++++ 7 files changed, 90 insertions(+) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index f9920f1341c8..5a0b6ee49cb4 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -1872,6 +1872,10 @@ config X86_INTEL_MEMORY_PROTECTION_KEYS =20 If unsure, say y. =20 +config ARCH_HAS_PTREGS_AUXILIARY + depends on X86_64 + bool + choice prompt "TSX enable mode" depends on CPU_SUP_INTEL diff --git a/arch/x86/entry/calling.h b/arch/x86/entry/calling.h index f6907627172b..b7515f8b0092 100644 --- a/arch/x86/entry/calling.h +++ b/arch/x86/entry/calling.h @@ -65,6 +65,25 @@ For 32-bit we have the following conventions - kernel is= built with * for assembly code: */ =20 +#ifdef CONFIG_ARCH_HAS_PTREGS_AUXILIARY + +.macro PUSH_PTREGS_AUXILIARY + /* add space for pt_regs_auxiliary */ + subq $PTREGS_AUX_SIZE, %rsp +.endm + +.macro POP_PTREGS_AUXILIARY + /* remove space for pt_regs_auxiliary */ + addq $PTREGS_AUX_SIZE, %rsp +.endm + +#else + +#define PUSH_PTREGS_AUXILIARY +#define POP_PTREGS_AUXILIARY + +#endif + .macro PUSH_REGS rdx=3D%rdx rcx=3D%rcx rax=3D%rax save_ret=3D0 .if \save_ret pushq %rsi /* pt_regs->si */ diff --git a/arch/x86/entry/entry_64.S b/arch/x86/entry/entry_64.S index 9953d966d124..4f9f7f5cb563 100644 --- a/arch/x86/entry/entry_64.S +++ b/arch/x86/entry/entry_64.S @@ -362,7 +362,9 @@ SYM_CODE_END(xen_error_entry) movq $-1, ORIG_RAX(%rsp) /* no syscall to restart */ .endif =20 + PUSH_PTREGS_AUXILIARY call \cfunc + POP_PTREGS_AUXILIARY =20 /* For some configurations \cfunc ends up being a noreturn. */ REACHABLE @@ -472,7 +474,9 @@ SYM_CODE_START(\asmsym) =20 movq %rsp, %rdi /* pt_regs pointer */ =20 + PUSH_PTREGS_AUXILIARY call \cfunc + POP_PTREGS_AUXILIARY =20 jmp paranoid_exit =20 @@ -535,7 +539,9 @@ SYM_CODE_START(\asmsym) * stack. */ movq %rsp, %rdi /* pt_regs pointer */ + PUSH_PTREGS_AUXILIARY call vc_switch_off_ist + POP_PTREGS_AUXILIARY movq %rax, %rsp /* Switch to new stack */ =20 ENCODE_FRAME_POINTER @@ -547,7 +553,9 @@ SYM_CODE_START(\asmsym) =20 movq %rsp, %rdi /* pt_regs pointer */ =20 + PUSH_PTREGS_AUXILIARY call kernel_\cfunc + POP_PTREGS_AUXILIARY =20 /* * No need to switch back to the IST stack. The current stack is either @@ -584,7 +592,9 @@ SYM_CODE_START(\asmsym) movq %rsp, %rdi /* pt_regs pointer into first argument */ movq ORIG_RAX(%rsp), %rsi /* get error code into 2nd argument*/ movq $-1, ORIG_RAX(%rsp) /* no syscall to restart */ + PUSH_PTREGS_AUXILIARY call \cfunc + POP_PTREGS_AUXILIARY =20 /* For some configurations \cfunc ends up being a noreturn. */ REACHABLE @@ -838,7 +848,9 @@ SYM_CODE_START_LOCAL(exc_xen_hypervisor_callback) movq %rdi, %rsp /* we don't return, adjust the stack frame */ UNWIND_HINT_REGS =20 + PUSH_PTREGS_AUXILIARY call xen_pv_evtchn_do_upcall + POP_PTREGS_AUXILIARY =20 jmp error_return SYM_CODE_END(exc_xen_hypervisor_callback) @@ -1062,7 +1074,9 @@ SYM_CODE_START_LOCAL(error_entry) .Lerror_entry_from_usermode_after_swapgs: =20 /* Put us onto the real thread stack. */ + PUSH_PTREGS_AUXILIARY call sync_regs + POP_PTREGS_AUXILIARY RET =20 /* @@ -1119,7 +1133,9 @@ SYM_CODE_START_LOCAL(error_entry) * as if we faulted immediately after IRET. */ leaq 8(%rsp), %rdi /* arg0 =3D pt_regs pointer */ + PUSH_PTREGS_AUXILIARY call fixup_bad_iret + POP_PTREGS_AUXILIARY mov %rax, %rdi jmp .Lerror_entry_from_usermode_after_swapgs SYM_CODE_END(error_entry) @@ -1229,7 +1245,9 @@ SYM_CODE_START(asm_exc_nmi) =20 movq %rsp, %rdi movq $-1, %rsi + PUSH_PTREGS_AUXILIARY call exc_nmi + POP_PTREGS_AUXILIARY =20 /* * Return back to user mode. We must *not* do the normal exit @@ -1265,6 +1283,8 @@ SYM_CODE_START(asm_exc_nmi) * +---------------------------------------------------------+ * | pt_regs | * +---------------------------------------------------------+ + * | (Optionally) pt_regs_extended | + * +---------------------------------------------------------+ * * The "original" frame is used by hardware. Before re-enabling * NMIs, we need to be done with it, and we need to leave enough @@ -1443,7 +1463,9 @@ end_repeat_nmi: =20 movq %rsp, %rdi movq $-1, %rsi + PUSH_PTREGS_AUXILIARY call exc_nmi + POP_PTREGS_AUXILIARY =20 /* Always restore stashed SPEC_CTRL value (see paranoid_entry) */ IBRS_EXIT save_reg=3D%r15 diff --git a/arch/x86/entry/entry_64_compat.S b/arch/x86/entry/entry_64_com= pat.S index 682338e7e2a3..7f1e670f7b06 100644 --- a/arch/x86/entry/entry_64_compat.S +++ b/arch/x86/entry/entry_64_compat.S @@ -117,7 +117,9 @@ SYM_INNER_LABEL(entry_SYSENTER_compat_after_hwframe, SY= M_L_GLOBAL) .Lsysenter_flags_fixed: =20 movq %rsp, %rdi + PUSH_PTREGS_AUXILIARY call do_SYSENTER_32 + POP_PTREGS_AUXILIARY /* XEN PV guests always use IRET path */ ALTERNATIVE "testl %eax, %eax; jz swapgs_restore_regs_and_return_to_userm= ode", \ "jmp swapgs_restore_regs_and_return_to_usermode", X86_FEATURE_XENPV @@ -212,7 +214,9 @@ SYM_INNER_LABEL(entry_SYSCALL_compat_after_hwframe, SYM= _L_GLOBAL) UNTRAIN_RET =20 movq %rsp, %rdi + PUSH_PTREGS_AUXILIARY call do_fast_syscall_32 + POP_PTREGS_AUXILIARY /* XEN PV guests always use IRET path */ ALTERNATIVE "testl %eax, %eax; jz swapgs_restore_regs_and_return_to_userm= ode", \ "jmp swapgs_restore_regs_and_return_to_usermode", X86_FEATURE_XENPV @@ -351,6 +355,8 @@ SYM_CODE_START(entry_INT80_compat) UNTRAIN_RET =20 movq %rsp, %rdi + PUSH_PTREGS_AUXILIARY call do_int80_syscall_32 + POP_PTREGS_AUXILIARY jmp swapgs_restore_regs_and_return_to_usermode SYM_CODE_END(entry_INT80_compat) diff --git a/arch/x86/include/asm/ptrace.h b/arch/x86/include/asm/ptrace.h index f4db78b09c8f..5a9c85893459 100644 --- a/arch/x86/include/asm/ptrace.h +++ b/arch/x86/include/asm/ptrace.h @@ -2,6 +2,7 @@ #ifndef _ASM_X86_PTRACE_H #define _ASM_X86_PTRACE_H =20 +#include #include #include #include @@ -91,6 +92,23 @@ struct pt_regs { /* top of stack page */ }; =20 +/* + * NOTE: Features which add data to pt_regs_auxiliary must select + * ARCH_HAS_PTREGS_AUXILIARY. Failure to do so will result in a build fai= lure. + */ +struct pt_regs_auxiliary { +}; + +struct pt_regs_extended { + struct pt_regs_auxiliary aux; + struct pt_regs pt_regs __aligned(8); +}; + +static inline struct pt_regs_extended *to_extended_pt_regs(struct pt_regs = *regs) +{ + return container_of(regs, struct pt_regs_extended, pt_regs); +} + #endif /* !__i386__ */ =20 #ifdef CONFIG_PARAVIRT diff --git a/arch/x86/kernel/asm-offsets_64.c b/arch/x86/kernel/asm-offsets= _64.c index 9b698215d261..413fe632445b 100644 --- a/arch/x86/kernel/asm-offsets_64.c +++ b/arch/x86/kernel/asm-offsets_64.c @@ -4,6 +4,7 @@ #endif =20 #include +#include =20 #if defined(CONFIG_KVM_GUEST) #include @@ -60,5 +61,19 @@ int main(void) DEFINE(stack_canary_offset, offsetof(struct fixed_percpu_data, stack_cana= ry)); BLANK(); #endif + +#ifdef CONFIG_ARCH_HAS_PTREGS_AUXILIARY + /* Size of Auxiliary pt_regs data */ + DEFINE(PTREGS_AUX_SIZE, sizeof(struct pt_regs_extended) - + sizeof(struct pt_regs)); +#else + /* + * Adding data to struct pt_regs_auxiliary requires setting + * ARCH_HAS_PTREGS_AUXILIARY + */ + BUILD_BUG_ON((sizeof(struct pt_regs_extended) - + sizeof(struct pt_regs)) !=3D 0); +#endif + return 0; } diff --git a/arch/x86/kernel/head_64.S b/arch/x86/kernel/head_64.S index d860d437631b..3a41273acb1c 100644 --- a/arch/x86/kernel/head_64.S +++ b/arch/x86/kernel/head_64.S @@ -398,8 +398,10 @@ SYM_CODE_START_NOALIGN(vc_boot_ghcb) movq %rsp, %rdi movq ORIG_RAX(%rsp), %rsi movq initial_vc_handler(%rip), %rax + PUSH_PTREGS_AUXILIARY ANNOTATE_RETPOLINE_SAFE call *%rax + POP_PTREGS_AUXILIARY =20 /* Unwind pt_regs */ POP_REGS @@ -479,7 +481,9 @@ SYM_CODE_START_LOCAL(early_idt_handler_common) UNWIND_HINT_REGS =20 movq %rsp,%rdi /* RDI =3D pt_regs; RSI is already trapnr */ + PUSH_PTREGS_AUXILIARY call do_early_exception + POP_PTREGS_AUXILIARY =20 decl early_recursion_flag(%rip) jmp restore_regs_and_return_to_kernel @@ -508,7 +512,9 @@ SYM_CODE_START_NOALIGN(vc_no_ghcb) /* Call C handler */ movq %rsp, %rdi movq ORIG_RAX(%rsp), %rsi + PUSH_PTREGS_AUXILIARY call do_vc_no_ghcb + POP_PTREGS_AUXILIARY =20 /* Unwind pt_regs */ POP_REGS --=20 2.35.3 From nobody Sat May 18 21:00:27 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 54005C00140 for ; Thu, 11 Aug 2022 02:49:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233800AbiHKCtW (ORCPT ); Wed, 10 Aug 2022 22:49:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33832 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230006AbiHKCtK (ORCPT ); Wed, 10 Aug 2022 22:49:10 -0400 Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 77BCC88DEB for ; Wed, 10 Aug 2022 19:49:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660186149; x=1691722149; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=lH7D5nKGGmBjcycxHQUZmmg8Xl72TStupxWDAHhrpCA=; b=AIAudzuRB8hX2wPKTYDki8iKrXX0SyHhk2YOkqVY+yzOgU3n0jRq7Ais m8hB1iyYqwBCp9lkE32ZsWQs+HhnHrQ2uB9h87rOAN/gYhfh2HygSZlk9 uKcvRqZQZKHShj4sy+NUN0l6xsN2xAnD7tIM6GdsWvgumWJVQdl0Cm6uE DUZZHuEM7bonJFqeX3QpjdqQqb+6szv2rTBWBL8kSIi8+aSOg361PawaA jfrJzeufqjgcx6dMI+XZ7kDoUJGCEsar/+Y51yqJrFqTQ9udFIVgF63DI AjwAx0SSqJRsq8DVkda1Dj9lnDByLCTUfA0ldKuL16EM6A9lzyfd3CIYx Q==; X-IronPort-AV: E=McAfee;i="6400,9594,10435"; a="291242718" X-IronPort-AV: E=Sophos;i="5.93,228,1654585200"; d="scan'208";a="291242718" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Aug 2022 19:49:09 -0700 X-IronPort-AV: E=Sophos;i="5.93,228,1654585200"; d="scan'208";a="608777333" Received: from zjoseph-mobl3.amr.corp.intel.com (HELO localhost) ([10.209.123.207]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Aug 2022 19:49:08 -0700 From: ira.weiny@intel.com To: Rik van Riel , Borislav Petkov , Dave Hansen Cc: Ira Weiny , Thomas Gleixner , x86@kernel.org, linux-kernel@vger.kernel.org, kernel-team@fb.com Subject: [PATCH 3/3] x86/mm: Store CPU info on exception entry Date: Wed, 10 Aug 2022 19:49:03 -0700 Message-Id: <20220811024903.178925-4-ira.weiny@intel.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220811024903.178925-1-ira.weiny@intel.com> References: <20220811024903.178925-1-ira.weiny@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Ira Weiny x86 has auxiliary pt_regs space available to store information on the stack during exceptions. This information is easier to obtain and store within C code. The CPU information of a page fault is useful in determining where bad CPUs are in a large data center. Store the CPU on page fault entry and use it later. Cc: Rik van Riel Suggested-by: Borislav Petkov Suggested-by: Dave Hansen Suggested-by: Thomas Gleixner Signed-off-by: Ira Weiny --- Changes from RFC: New patch combining 2 and 5 from original series and modified. Boris/Thomas - eliminate generic calls to save the cpu and call only from exc_page_fault --- arch/x86/Kconfig | 2 +- arch/x86/include/asm/ptrace.h | 1 + arch/x86/mm/fault.c | 12 ++++++++++-- 3 files changed, 12 insertions(+), 3 deletions(-) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 5a0b6ee49cb4..e4a04406be2c 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -1874,7 +1874,7 @@ config X86_INTEL_MEMORY_PROTECTION_KEYS =20 config ARCH_HAS_PTREGS_AUXILIARY depends on X86_64 - bool + def_bool y =20 choice prompt "TSX enable mode" diff --git a/arch/x86/include/asm/ptrace.h b/arch/x86/include/asm/ptrace.h index 5a9c85893459..b403b469996f 100644 --- a/arch/x86/include/asm/ptrace.h +++ b/arch/x86/include/asm/ptrace.h @@ -97,6 +97,7 @@ struct pt_regs { * ARCH_HAS_PTREGS_AUXILIARY. Failure to do so will result in a build fai= lure. */ struct pt_regs_auxiliary { + int cpu; }; =20 struct pt_regs_extended { diff --git a/arch/x86/mm/fault.c b/arch/x86/mm/fault.c index dbc6a2e08a96..0aa420cd7874 100644 --- a/arch/x86/mm/fault.c +++ b/arch/x86/mm/fault.c @@ -768,9 +768,9 @@ static inline void show_signal_msg(struct pt_regs *regs, unsigned long error_code, unsigned long address, struct task_struct *tsk) { + struct pt_regs_auxiliary *aux_pt_regs =3D &to_extended_pt_regs(regs)->aux; const char *loglvl =3D task_pid_nr(tsk) > 1 ? KERN_INFO : KERN_EMERG; - /* This is a racy snapshot, but it's better than nothing. */ - int cpu =3D raw_smp_processor_id(); + int cpu =3D aux_pt_regs->cpu; =20 if (!unhandled_signal(tsk, SIGSEGV)) return; @@ -1507,6 +1507,13 @@ handle_page_fault(struct pt_regs *regs, unsigned lon= g error_code, } } =20 +noinstr static void aux_pt_regs_save_cpu(struct pt_regs *regs) +{ + struct pt_regs_auxiliary *aux_pt_regs =3D &to_extended_pt_regs(regs)->aux; + + aux_pt_regs->cpu =3D raw_smp_processor_id(); +} + DEFINE_IDTENTRY_RAW_ERRORCODE(exc_page_fault) { unsigned long address =3D read_cr2(); @@ -1550,6 +1557,7 @@ DEFINE_IDTENTRY_RAW_ERRORCODE(exc_page_fault) */ state =3D irqentry_enter(regs); =20 + aux_pt_regs_save_cpu(regs); instrumentation_begin(); handle_page_fault(regs, error_code, address); instrumentation_end(); --=20 2.35.3