From nobody Wed Apr 15 04:33:12 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0704AC25B07 for ; Wed, 10 Aug 2022 23:29:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233738AbiHJX3k (ORCPT ); Wed, 10 Aug 2022 19:29:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50734 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233722AbiHJX3f (ORCPT ); Wed, 10 Aug 2022 19:29:35 -0400 Received: from fanzine2.igalia.com (fanzine.igalia.com [178.60.130.6]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1DC5E7FE6B for ; Wed, 10 Aug 2022 16:29:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References: In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=7Xzpvuhbi4ekr/7p8HUj3VyVoX/X8rm9HPl/S0NCtoM=; b=Rp+UOPltCxSADeMjzcbrqeZHK8 6Q8oAbO4JfpCSXEESfJuYPPTxrx8fPEZxnHKHrXlXV/fG1MstZj/uCFNO0X/TBk4k+yR0R2N/Otct b0ipq/2Hlt5cb18MKD4tJ6SssLUiPjAtCkz3JTG4I11Ncebbh7Omuce8uF+vstS7irA/xh0Q+baXq HcFwNbfjb7k1oAooV5eGo8zPW2o6GqKUIrq6yVsGSLjCeXJLTvYsfduJbsJs5zixpoCoLtigb8PbZ UZyON1XP0ChreOwzXqmtEJrXQ4ni+Ql4BTBxYvnr62nWYu3tpBzyehI3qaJU76TIwXUKqkIMqdnrh bjxQcbgw==; Received: from [191.17.41.12] (helo=localhost.localdomain) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1oLv8i-004r9g-EK; Thu, 11 Aug 2022 01:29:28 +0200 From: =?UTF-8?q?Andr=C3=A9=20Almeida?= To: Alex Deucher , =?UTF-8?q?=27Christian=20K=C3=B6nig=27?= , 'Pan Xinhui' , David Airlie , Daniel Vetter , Hawking Zhang , Tao Zhou , Felix Kuehling , Jack Xiao , amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Tom St Denis , Rodrigo Siqueira Cc: kernel-dev@igalia.com, =?UTF-8?q?Andr=C3=A9=20Almeida?= Subject: [PATCH v3 1/4] drm/amd: Add detailed GFXOFF stats to debugfs Date: Wed, 10 Aug 2022 20:28:55 -0300 Message-Id: <20220810232858.11844-2-andrealmeid@igalia.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220810232858.11844-1-andrealmeid@igalia.com> References: <20220810232858.11844-1-andrealmeid@igalia.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add debugfs interface to log GFXOFF statistics: - Read amdgpu_gfxoff_count to get the total GFXOFF entry count at the time of query since system power-up - Write 1 to amdgpu_gfxoff_residency to start logging, and 0 to stop. Read it to get average GFXOFF residency % multiplied by 100 during the last logging interval. Both features are designed to be keep the values persistent between suspends. Signed-off-by: Andr=C3=A9 Almeida --- drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 168 ++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 + drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 39 ++++ drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 6 + drivers/gpu/drm/amd/pm/amdgpu_dpm.c | 45 +++++ drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h | 3 + drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 33 ++++ drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 22 +++ drivers/gpu/drm/amd/pm/swsmu/smu_internal.h | 3 + 9 files changed, 321 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c b/drivers/gpu/drm/= amd/amdgpu/amdgpu_debugfs.c index e2eec985adb3..e0eed087dba4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c @@ -1042,6 +1042,157 @@ static ssize_t amdgpu_debugfs_gpr_read(struct file = *f, char __user *buf, return r; } =20 +/** + * amdgpu_debugfs_gfxoff_residency_read - Read GFXOFF residency + * + * @f: open file handle + * @buf: User buffer to store read data in + * @size: Number of bytes to read + * @pos: Offset to seek to + * + * Read the last residency value logged. It doesn't auto update, one needs= to + * stop logging before getting the current value. + */ +static ssize_t amdgpu_debugfs_gfxoff_residency_read(struct file *f, char _= _user *buf, + size_t size, loff_t *pos) +{ + struct amdgpu_device *adev =3D file_inode(f)->i_private; + ssize_t result =3D 0; + int r; + + if (size & 0x3 || *pos & 0x3) + return -EINVAL; + + r =3D pm_runtime_get_sync(adev_to_drm(adev)->dev); + if (r < 0) { + pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); + return r; + } + + while (size) { + uint32_t value; + + r =3D amdgpu_get_gfx_off_residency(adev, &value); + if (r) + goto out; + + r =3D put_user(value, (uint32_t *)buf); + if (r) + goto out; + + result +=3D 4; + buf +=3D 4; + *pos +=3D 4; + size -=3D 4; + } + + r =3D result; +out: + pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); + pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); + + return r; +} + +/** + * amdgpu_debugfs_gfxoff_residency_write - Log GFXOFF Residency + * + * @f: open file handle + * @buf: User buffer to write data from + * @size: Number of bytes to write + * @pos: Offset to seek to + * + * Write a 32-bit non-zero to start logging; write a 32-bit zero to stop + */ +static ssize_t amdgpu_debugfs_gfxoff_residency_write(struct file *f, const= char __user *buf, + size_t size, loff_t *pos) +{ + struct amdgpu_device *adev =3D file_inode(f)->i_private; + ssize_t result =3D 0; + int r; + + if (size & 0x3 || *pos & 0x3) + return -EINVAL; + + r =3D pm_runtime_get_sync(adev_to_drm(adev)->dev); + if (r < 0) { + pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); + return r; + } + + while (size) { + u32 value; + + r =3D get_user(value, (uint32_t *)buf); + if (r) + goto out; + + amdgpu_set_gfx_off_residency(adev, value ? true : false); + + result +=3D 4; + buf +=3D 4; + *pos +=3D 4; + size -=3D 4; + } + + r =3D result; +out: + pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); + pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); + + return r; +} + + +/** + * amdgpu_debugfs_gfxoff_count_read - Read GFXOFF entry count + * + * @f: open file handle + * @buf: User buffer to store read data in + * @size: Number of bytes to read + * @pos: Offset to seek to + */ +static ssize_t amdgpu_debugfs_gfxoff_count_read(struct file *f, char __use= r *buf, + size_t size, loff_t *pos) +{ + struct amdgpu_device *adev =3D file_inode(f)->i_private; + ssize_t result =3D 0; + int r; + + if (size & 0x3 || *pos & 0x3) + return -EINVAL; + + r =3D pm_runtime_get_sync(adev_to_drm(adev)->dev); + if (r < 0) { + pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); + return r; + } + + while (size) { + u64 value =3D 0; + + r =3D amdgpu_get_gfx_off_entrycount(adev, &value); + if (r) + goto out; + + r =3D put_user(value, (u64 *)buf); + if (r) + goto out; + + result +=3D 4; + buf +=3D 4; + *pos +=3D 4; + size -=3D 4; + } + + r =3D result; +out: + pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); + pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); + + return r; +} + /** * amdgpu_debugfs_gfxoff_write - Enable/disable GFXOFF * @@ -1249,6 +1400,19 @@ static const struct file_operations amdgpu_debugfs_g= fxoff_status_fops =3D { .llseek =3D default_llseek }; =20 +static const struct file_operations amdgpu_debugfs_gfxoff_count_fops =3D { + .owner =3D THIS_MODULE, + .read =3D amdgpu_debugfs_gfxoff_count_read, + .llseek =3D default_llseek +}; + +static const struct file_operations amdgpu_debugfs_gfxoff_residency_fops = =3D { + .owner =3D THIS_MODULE, + .read =3D amdgpu_debugfs_gfxoff_residency_read, + .write =3D amdgpu_debugfs_gfxoff_residency_write, + .llseek =3D default_llseek +}; + static const struct file_operations *debugfs_regs[] =3D { &amdgpu_debugfs_regs_fops, &amdgpu_debugfs_regs2_fops, @@ -1261,6 +1425,8 @@ static const struct file_operations *debugfs_regs[] = =3D { &amdgpu_debugfs_gpr_fops, &amdgpu_debugfs_gfxoff_fops, &amdgpu_debugfs_gfxoff_status_fops, + &amdgpu_debugfs_gfxoff_count_fops, + &amdgpu_debugfs_gfxoff_residency_fops, }; =20 static const char *debugfs_regs_names[] =3D { @@ -1275,6 +1441,8 @@ static const char *debugfs_regs_names[] =3D { "amdgpu_gpr", "amdgpu_gfxoff", "amdgpu_gfxoff_status", + "amdgpu_gfxoff_count", + "amdgpu_gfxoff_residency", }; =20 /** diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/a= md/amdgpu/amdgpu_device.c index b79ee4ffb879..15a95bc2c211 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -3576,6 +3576,8 @@ int amdgpu_device_init(struct amdgpu_device *adev, INIT_WORK(&adev->xgmi_reset_work, amdgpu_device_xgmi_reset_func); =20 adev->gfx.gfx_off_req_count =3D 1; + adev->gfx.gfx_off_residency =3D 0; + adev->gfx.gfx_off_entrycount =3D 0; adev->pm.ac_power =3D power_supply_is_system_supplied() > 0; =20 atomic_set(&adev->throttling_logging_enabled, 1); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/= amdgpu/amdgpu_gfx.c index 222d3d7ea076..1c9fba71801e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c @@ -610,6 +610,45 @@ void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, b= ool enable) mutex_unlock(&adev->gfx.gfx_off_mutex); } =20 +int amdgpu_set_gfx_off_residency(struct amdgpu_device *adev, bool value) +{ + int r =3D 0; + + mutex_lock(&adev->gfx.gfx_off_mutex); + + r =3D amdgpu_dpm_set_residency_gfxoff(adev, value); + + mutex_unlock(&adev->gfx.gfx_off_mutex); + + return r; +} + +int amdgpu_get_gfx_off_residency(struct amdgpu_device *adev, u32 *value) +{ + int r =3D 0; + + mutex_lock(&adev->gfx.gfx_off_mutex); + + r =3D amdgpu_dpm_get_residency_gfxoff(adev, value); + + mutex_unlock(&adev->gfx.gfx_off_mutex); + + return r; +} + +int amdgpu_get_gfx_off_entrycount(struct amdgpu_device *adev, u64 *value) +{ + int r =3D 0; + + mutex_lock(&adev->gfx.gfx_off_mutex); + + r =3D amdgpu_dpm_get_entrycount_gfxoff(adev, value); + + mutex_unlock(&adev->gfx.gfx_off_mutex); + + return r; +} + int amdgpu_get_gfx_off_status(struct amdgpu_device *adev, uint32_t *value) { =20 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/= amdgpu/amdgpu_gfx.h index 23a696d38390..1b8b4a5270c9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h @@ -336,6 +336,8 @@ struct amdgpu_gfx { struct mutex gfx_off_mutex; uint32_t gfx_off_req_count; /* default 1, enable g= fx off: dec 1, disable gfx off: add 1 */ struct delayed_work gfx_off_delay_work; + uint32_t gfx_off_residency; + uint64_t gfx_off_entrycount; =20 /* pipe reservation */ struct mutex pipe_reserve_mutex; @@ -407,6 +409,10 @@ bool amdgpu_gfx_is_me_queue_enabled(struct amdgpu_devi= ce *adev, int me, void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable); int amdgpu_get_gfx_off_status(struct amdgpu_device *adev, uint32_t *value); int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev, struct ras_common= _if *ras_block); +void amdgpu_gfx_ras_fini(struct amdgpu_device *adev); +int amdgpu_get_gfx_off_entrycount(struct amdgpu_device *adev, u64 *value); +int amdgpu_get_gfx_off_residency(struct amdgpu_device *adev, u32 *residenc= y); +int amdgpu_set_gfx_off_residency(struct amdgpu_device *adev, bool value); int amdgpu_gfx_process_ras_data_cb(struct amdgpu_device *adev, void *err_data, struct amdgpu_iv_entry *entry); diff --git a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c b/drivers/gpu/drm/amd/pm/a= mdgpu_dpm.c index 956b6ce81c84..1b300c569faf 100644 --- a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c +++ b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c @@ -668,6 +668,51 @@ int amdgpu_dpm_wait_for_event(struct amdgpu_device *ad= ev, return ret; } =20 +int amdgpu_dpm_set_residency_gfxoff(struct amdgpu_device *adev, bool value) +{ + struct smu_context *smu =3D adev->powerplay.pp_handle; + int ret =3D 0; + + if (!is_support_sw_smu(adev)) + return -EOPNOTSUPP; + + mutex_lock(&adev->pm.mutex); + ret =3D smu_set_residency_gfxoff(smu, value); + mutex_unlock(&adev->pm.mutex); + + return ret; +} + +int amdgpu_dpm_get_residency_gfxoff(struct amdgpu_device *adev, u32 *value) +{ + struct smu_context *smu =3D adev->powerplay.pp_handle; + int ret =3D 0; + + if (!is_support_sw_smu(adev)) + return -EOPNOTSUPP; + + mutex_lock(&adev->pm.mutex); + ret =3D smu_get_residency_gfxoff(smu, value); + mutex_unlock(&adev->pm.mutex); + + return ret; +} + +int amdgpu_dpm_get_entrycount_gfxoff(struct amdgpu_device *adev, u64 *valu= e) +{ + struct smu_context *smu =3D adev->powerplay.pp_handle; + int ret =3D 0; + + if (!is_support_sw_smu(adev)) + return -EOPNOTSUPP; + + mutex_lock(&adev->pm.mutex); + ret =3D smu_get_entrycount_gfxoff(smu, value); + mutex_unlock(&adev->pm.mutex); + + return ret; +} + int amdgpu_dpm_get_status_gfxoff(struct amdgpu_device *adev, uint32_t *val= ue) { struct smu_context *smu =3D adev->powerplay.pp_handle; diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h b/drivers/gpu/drm/amd/= pm/inc/amdgpu_dpm.h index 65624d091ed2..cb5b9df78b4d 100644 --- a/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h +++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h @@ -435,6 +435,9 @@ int amdgpu_dpm_set_soft_freq_range(struct amdgpu_device= *adev, int amdgpu_dpm_write_watermarks_table(struct amdgpu_device *adev); int amdgpu_dpm_wait_for_event(struct amdgpu_device *adev, enum smu_event_t= ype event, uint64_t event_arg); +int amdgpu_dpm_get_residency_gfxoff(struct amdgpu_device *adev, u32 *value= ); +int amdgpu_dpm_set_residency_gfxoff(struct amdgpu_device *adev, bool value= ); +int amdgpu_dpm_get_entrycount_gfxoff(struct amdgpu_device *adev, u64 *valu= e); int amdgpu_dpm_get_status_gfxoff(struct amdgpu_device *adev, uint32_t *val= ue); uint64_t amdgpu_dpm_get_thermal_throttling_counter(struct amdgpu_device *a= dev); void amdgpu_dpm_gfx_state_change(struct amdgpu_device *adev, diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/am= d/pm/swsmu/amdgpu_smu.c index fd79b213fab4..4c7b8eb55299 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -90,6 +90,30 @@ static int smu_sys_set_pp_feature_mask(void *handle, return smu_set_pp_feature_mask(smu, new_mask); } =20 +int smu_set_residency_gfxoff(struct smu_context *smu, bool value) +{ + if (!smu->ppt_funcs->set_gfx_off_residency) + return -EINVAL; + + return smu_set_gfx_off_residency(smu, value); +} + +int smu_get_residency_gfxoff(struct smu_context *smu, u32 *value) +{ + if (!smu->ppt_funcs->get_gfx_off_residency) + return -EINVAL; + + return smu_get_gfx_off_residency(smu, value); +} + +int smu_get_entrycount_gfxoff(struct smu_context *smu, u64 *value) +{ + if (!smu->ppt_funcs->get_gfx_off_entrycount) + return -EINVAL; + + return smu_get_gfx_off_entrycount(smu, value); +} + int smu_get_status_gfxoff(struct smu_context *smu, uint32_t *value) { if (!smu->ppt_funcs->get_gfx_off_status) @@ -1574,6 +1598,7 @@ static int smu_suspend(void *handle) struct amdgpu_device *adev =3D (struct amdgpu_device *)handle; struct smu_context *smu =3D adev->powerplay.pp_handle; int ret; + uint64_t count; =20 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) return 0; @@ -1591,6 +1616,14 @@ static int smu_suspend(void *handle) =20 smu_set_gfx_cgpg(smu, false); =20 + /* + * pwfw resets entrycount when device is suspended, so we save the + * last value to be used when we resume to keep it consistent + */ + ret =3D smu_get_entrycount_gfxoff(smu, &count); + if (!ret) + adev->gfx.gfx_off_entrycount =3D count; + return 0; } =20 diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h b/drivers/gpu/dr= m/amd/pm/swsmu/inc/amdgpu_smu.h index b81c657c7386..e2fa3b066b96 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h @@ -1111,6 +1111,22 @@ struct pptable_funcs { */ uint32_t (*get_gfx_off_status)(struct smu_context *smu); =20 + /** + * @gfx_off_entrycount: total GFXOFF entry count at the time of + * query since system power-up + */ + u32 (*get_gfx_off_entrycount)(struct smu_context *smu, uint64_t *entrycou= nt); + + /** + * @set_gfx_off_residency: set 1 to start logging, 0 to stop logging + */ + u32 (*set_gfx_off_residency)(struct smu_context *smu, bool start); + + /** + * @get_gfx_off_residency: Average GFXOFF residency % during the logging = interval + */ + u32 (*get_gfx_off_residency)(struct smu_context *smu, uint32_t *residency= ); + /** * @register_irq_handler: Register interupt request handlers. */ @@ -1454,6 +1470,12 @@ int smu_set_ac_dc(struct smu_context *smu); =20 int smu_allow_xgmi_power_down(struct smu_context *smu, bool en); =20 +int smu_get_entrycount_gfxoff(struct smu_context *smu, u64 *value); + +int smu_get_residency_gfxoff(struct smu_context *smu, u32 *value); + +int smu_set_residency_gfxoff(struct smu_context *smu, bool value); + int smu_get_status_gfxoff(struct smu_context *smu, uint32_t *value); =20 int smu_handle_passthrough_sbr(struct smu_context *smu, bool enable); diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_internal.h b/drivers/gpu/drm/= amd/pm/swsmu/smu_internal.h index 7469bbfce1fb..ceb13c838067 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu_internal.h +++ b/drivers/gpu/drm/amd/pm/swsmu/smu_internal.h @@ -47,6 +47,9 @@ #define smu_notify_memory_pool_location(smu) smu_ppt_funcs(notify_memor= y_pool_location, 0, smu) #define smu_gfx_off_control(smu, enable) smu_ppt_funcs(gfx_off_control,= 0, smu, enable) #define smu_get_gfx_off_status(smu) smu_ppt_funcs(get_gfx_off_status,= 0, smu) +#define smu_get_gfx_off_entrycount(smu, value) smu_ppt_funcs(get_gfx_= off_entrycount, 0, smu, value) +#define smu_get_gfx_off_residency(smu, value) smu_ppt_funcs(get_gfx_o= ff_residency, 0, smu, value) +#define smu_set_gfx_off_residency(smu, value) smu_ppt_funcs(set_gfx_o= ff_residency, 0, smu, value) #define smu_set_last_dcef_min_deep_sleep_clk(smu) smu_ppt_funcs(set_last= _dcef_min_deep_sleep_clk, 0, smu) #define smu_system_features_control(smu, en) smu_ppt_funcs(system_featu= res_control, 0, smu, en) #define smu_init_max_sustainable_clocks(smu) smu_ppt_funcs(init_max_sus= tainable_clocks, 0, smu) --=20 2.37.1 From nobody Wed Apr 15 04:33:12 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3943AC25B06 for ; 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b=At07KXQAjbH2qq7NAW1khPT7kj gwrgPzptSNa7FIE0yyxcEjFA6zF0gENxjXEB7ty34+/X6KNJpgCejbLNMGAWCis5K7/G2eSduaYfk XY+gkrZBq/aAFAK64r0UIZyDPSLGr6/EIsjbyfwDRKT9Y4rw21SC1MZQk3vYM0IYoX2VWAc5cX9uL ZMOKLe0BAFGqM67HGWEOeYpY+M+XPsBrio9hioPjIBoUIgRRz+6v6L8yxQBxWwKKK56777IZGeWRh ZcM0QVZ6R3REEJAZlaInA5Q13oXZROihxdlBJdK3f5YUsIdO1igcF2TBhjbRmkYnAD3upm3EMMFif kmZ3GuiA==; Received: from [191.17.41.12] (helo=localhost.localdomain) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1oLv8p-004r9g-Sk; Thu, 11 Aug 2022 01:29:36 +0200 From: =?UTF-8?q?Andr=C3=A9=20Almeida?= To: Alex Deucher , =?UTF-8?q?=27Christian=20K=C3=B6nig=27?= , 'Pan Xinhui' , David Airlie , Daniel Vetter , Hawking Zhang , Tao Zhou , Felix Kuehling , Jack Xiao , amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Tom St Denis , Rodrigo Siqueira Cc: kernel-dev@igalia.com, =?UTF-8?q?Andr=C3=A9=20Almeida?= Subject: [PATCH v3 2/4] drm/amd/pm: Implement GFXOFF's entry count and residency for vangogh Date: Wed, 10 Aug 2022 20:28:56 -0300 Message-Id: <20220810232858.11844-3-andrealmeid@igalia.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220810232858.11844-1-andrealmeid@igalia.com> References: <20220810232858.11844-1-andrealmeid@igalia.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Implement functions to get and set GFXOFF's entry count and residency for vangogh. Signed-off-by: Andr=C3=A9 Almeida --- .../pm/swsmu/inc/pmfw_if/smu_v11_5_ppsmc.h | 5 +- drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h | 5 +- .../gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 76 +++++++++++++++++++ 3 files changed, 84 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v11_5_ppsmc.h b/d= rivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v11_5_ppsmc.h index fe130a497d6c..7471e2df2828 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v11_5_ppsmc.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v11_5_ppsmc.h @@ -108,7 +108,10 @@ #define PPSMC_MSG_SetSlowPPTLimit 0x4A #define PPSMC_MSG_GetFastPPTLimit 0x4B #define PPSMC_MSG_GetSlowPPTLimit 0x4C -#define PPSMC_Message_Count 0x4D +#define PPSMC_MSG_GetGfxOffStatus 0x50 +#define PPSMC_MSG_GetGfxOffEntryCount 0x51 +#define PPSMC_MSG_LogGfxOffResidency 0x52 +#define PPSMC_Message_Count 0x53 =20 //Argument for PPSMC_MSG_GfxDeviceDriverReset enum { diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h b/drivers/gpu/drm= /amd/pm/swsmu/inc/smu_types.h index 19084a4fcb2b..76fb6cbbc09c 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h @@ -235,7 +235,10 @@ __SMU_DUMMY_MAP(UnforceGfxVid), \ __SMU_DUMMY_MAP(HeavySBR), \ __SMU_DUMMY_MAP(SetBadHBMPagesRetiredFlagsPerChannel), \ - __SMU_DUMMY_MAP(EnableGfxImu), + __SMU_DUMMY_MAP(EnableGfxImu), \ + __SMU_DUMMY_MAP(GetGfxOffStatus), \ + __SMU_DUMMY_MAP(GetGfxOffEntryCount), \ + __SMU_DUMMY_MAP(LogGfxOffResidency), =20 #undef __SMU_DUMMY_MAP #define __SMU_DUMMY_MAP(type) SMU_MSG_##type diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c b/drivers/gpu= /drm/amd/pm/swsmu/smu11/vangogh_ppt.c index 89504ff8e9ed..847990145dcd 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c @@ -138,6 +138,9 @@ static struct cmn2asic_msg_mapping vangogh_message_map[= SMU_MSG_MAX_COUNT] =3D { MSG_MAP(SetSlowPPTLimit, PPSMC_MSG_SetSlowPPTLimit, = 0), MSG_MAP(GetFastPPTLimit, PPSMC_MSG_GetFastPPTLimit, = 0), MSG_MAP(GetSlowPPTLimit, PPSMC_MSG_GetSlowPPTLimit, = 0), + MSG_MAP(GetGfxOffStatus, PPSMC_MSG_GetGfxOffStatus, 0), + MSG_MAP(GetGfxOffEntryCount, PPSMC_MSG_GetGfxOffEntryCount, 0), + MSG_MAP(LogGfxOffResidency, PPSMC_MSG_LogGfxOffResidency, 0), }; =20 static struct cmn2asic_mapping vangogh_feature_mask_map[SMU_FEATURE_COUNT]= =3D { @@ -2200,6 +2203,76 @@ static int vangogh_set_power_limit(struct smu_contex= t *smu, return ret; } =20 +/** + * vangogh_set_gfxoff_residency + * + * @smu: amdgpu_device pointer + * @start: start/stop residency log + * + * This function will be used to log gfxoff residency + * + * + * Returns standard response codes. + */ +static u32 vangogh_set_gfxoff_residency(struct smu_context *smu, bool star= t) +{ + int ret =3D 0; + u32 residency; + struct amdgpu_device *adev =3D smu->adev; + + if (!(adev->pm.pp_feature & PP_GFXOFF_MASK)) + return 0; + + ret =3D smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_LogGfxOffResidency, + start, &residency); + + if (!start) + adev->gfx.gfx_off_residency =3D residency; + + return ret; +} + +/** + * vangogh_get_gfxoff_residency + * + * @smu: amdgpu_device pointer + * + * This function will be used to get gfxoff residency. + * + * Returns standard response codes. + */ +static u32 vangogh_get_gfxoff_residency(struct smu_context *smu, uint32_t = *residency) +{ + struct amdgpu_device *adev =3D smu->adev; + + *residency =3D adev->gfx.gfx_off_residency; + + return 0; +} + +/** + * vangogh_get_gfxoff_entrycount - get gfxoff entry count + * + * @smu: amdgpu_device pointer + * + * This function will be used to get gfxoff entry count + * + * Returns standard response codes. + */ +static u32 vangogh_get_gfxoff_entrycount(struct smu_context *smu, uint64_t= *entrycount) +{ + int ret =3D 0, value =3D 0; + struct amdgpu_device *adev =3D smu->adev; + + if (!(adev->pm.pp_feature & PP_GFXOFF_MASK)) + return 0; + + ret =3D smu_cmn_send_smc_msg(smu, SMU_MSG_GetGfxOffEntryCount, &value); + *entrycount =3D value + adev->gfx.gfx_off_entrycount; + + return ret; +} + static const struct pptable_funcs vangogh_ppt_funcs =3D { =20 .check_fw_status =3D smu_v11_0_check_fw_status, @@ -2237,6 +2310,9 @@ static const struct pptable_funcs vangogh_ppt_funcs = =3D { .mode2_reset =3D vangogh_mode2_reset, .gfx_off_control =3D smu_v11_0_gfx_off_control, .get_gfx_off_status =3D vangogh_get_gfxoff_status, + .get_gfx_off_entrycount =3D vangogh_get_gfxoff_entrycount, + .get_gfx_off_residency =3D vangogh_get_gfxoff_residency, + .set_gfx_off_residency =3D vangogh_set_gfxoff_residency, .get_ppt_limit =3D vangogh_get_ppt_limit, .get_power_limit =3D vangogh_get_power_limit, .set_power_limit =3D vangogh_set_power_limit, --=20 2.37.1 From nobody Wed Apr 15 04:33:12 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CFD6CC00140 for ; Wed, 10 Aug 2022 23:30:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233488AbiHJXa0 (ORCPT ); Wed, 10 Aug 2022 19:30:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50852 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233758AbiHJX3z (ORCPT ); Wed, 10 Aug 2022 19:29:55 -0400 Received: from fanzine2.igalia.com (fanzine.igalia.com [178.60.130.6]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 724D583F33 for ; Wed, 10 Aug 2022 16:29:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References: In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=ciDPhF07fS+tRj3SbXyJWbm9upDSDTB8l7rbsGiPQ3k=; b=RkaB8hBq3/R/1OYWjtaZU64XCX 3OmzaUdxiynm4exZuNrmc6p80Mw5Q6TYSSnSb/f1mTTaOmyzWraHCWxeISIq1a1ICOLOzZmlweG0o YOmSL381a0dVFwm5y1rNY8WU5GNzqwCjTruBEEV0GEyTjt4gRDE2hh+yRINWGSaTFlAi1r6sEUQBM DLld2kb46YIkOfVWUrCd61qLCINDWkePkLM9hWKCHeyfQMuPQ4RxM+rbHM2B8H7Lgj9+lvMGgr/nv B9KLN8qAnLDY6xslPCom9REx6WbYaVQXvAoCBquUIG8VXYXzipYvOf+Drhi1GLdT5TXFFv6zg5n1n qYTw7yMQ==; Received: from [191.17.41.12] (helo=localhost.localdomain) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1oLv8x-004r9g-62; Thu, 11 Aug 2022 01:29:43 +0200 From: =?UTF-8?q?Andr=C3=A9=20Almeida?= To: Alex Deucher , =?UTF-8?q?=27Christian=20K=C3=B6nig=27?= , 'Pan Xinhui' , David Airlie , Daniel Vetter , Hawking Zhang , Tao Zhou , Felix Kuehling , Jack Xiao , amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Tom St Denis , Rodrigo Siqueira Cc: kernel-dev@igalia.com, =?UTF-8?q?Andr=C3=A9=20Almeida?= Subject: [PATCH v3 3/4] Documentation/gpu: Document GFXOFF's count and residency Date: Wed, 10 Aug 2022 20:28:57 -0300 Message-Id: <20220810232858.11844-4-andrealmeid@igalia.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220810232858.11844-1-andrealmeid@igalia.com> References: <20220810232858.11844-1-andrealmeid@igalia.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add documentation explaining those two new files. While here, add a note about the value type. Signed-off-by: Andr=C3=A9 Almeida --- Documentation/gpu/amdgpu/thermal.rst | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/Documentation/gpu/amdgpu/thermal.rst b/Documentation/gpu/amdgp= u/thermal.rst index 997231b6adcf..5e27e4eb3959 100644 --- a/Documentation/gpu/amdgpu/thermal.rst +++ b/Documentation/gpu/amdgpu/thermal.rst @@ -72,7 +72,8 @@ card's RLC (RunList Controller) firmware powers off the g= fx engine dynamically when there is no workload on gfx or compute pipes. GFXOFF is o= n by default on supported GPUs. =20 -Userspace can interact with GFXOFF through a debugfs interface: +Userspace can interact with GFXOFF through a debugfs interface (all values= in +`uint32_t`, unless otherwise noted): =20 ``amdgpu_gfxoff`` ----------------- @@ -104,3 +105,18 @@ Read it to check current GFXOFF's status of a GPU:: If GFXOFF is enabled, the value will be transitioning around [0, 3], always getting into 0 when possible. When it's disabled, it's always at 2. Returns ``-EINVAL`` if it's not supported. + +``amdgpu_gfxoff_count`` +----------------------- + +Read it to get the total GFXOFF entry count at the time of query since sys= tem +power-up. The value is an `uint64_t` type, however, due to firmware limita= tions, +it can currently overflow as an `uint32_t`. *Only supported in vangogh* + +``amdgpu_gfxoff_residency`` +--------------------------- + +Write 1 to amdgpu_gfxoff_residency to start logging, and 0 to stop. Read i= t to +get average GFXOFF residency % multiplied by 100 during the last logging +interval. E.g. a value of 7854 means 78.54% of the time in the last logging +interval the GPU was in GFXOFF mode. *Only supported in vangogh* --=20 2.37.1 From nobody Wed Apr 15 04:33:12 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EDAADC25B06 for ; Wed, 10 Aug 2022 23:30:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233728AbiHJXa1 (ORCPT ); Wed, 10 Aug 2022 19:30:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51556 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233797AbiHJXaA (ORCPT ); Wed, 10 Aug 2022 19:30:00 -0400 Received: from fanzine2.igalia.com (fanzine.igalia.com [178.60.130.6]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 485498FD55 for ; Wed, 10 Aug 2022 16:29:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References: In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=+7t/7eAOvi8kAxMn65dXL5tgH7liqj/5NHPtUP/lMtI=; b=pYnj2wc3dKklpInsGJAB6JOMxK RisYrT54Mjn3hO7kYTNobeqKnjZeRV1LjM0LCfKx9FUuGDWMHLdwPeoO9Y2lM2zXRJQ5VpgSfR3wy PVjjHqoaOCu60lckijE5fAPa+ogOQ0RMyw/Q9fhi5Tlaq0dGouHesKsU/MRzAriDZ0f83iXpoNJyc B3ghaHF/kBAvOwRiMedh0MDLA+6z3lcGj47WLcsX1BNE0Jl2ihxaOtHyPu807Rhviy8yiAHVrXutJ gffrmqdSNoNuHJUUmC2rDWmGvNQP1YQ2Is33xeR53dPYd3ZDvD/uEaV0uZjVbvW+Gn+W5+RTY6peO 0MUNUnKg==; Received: from [191.17.41.12] (helo=localhost.localdomain) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1oLv94-004r9g-EZ; Thu, 11 Aug 2022 01:29:50 +0200 From: =?UTF-8?q?Andr=C3=A9=20Almeida?= To: Alex Deucher , =?UTF-8?q?=27Christian=20K=C3=B6nig=27?= , 'Pan Xinhui' , David Airlie , Daniel Vetter , Hawking Zhang , Tao Zhou , Felix Kuehling , Jack Xiao , amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Tom St Denis , Rodrigo Siqueira Cc: kernel-dev@igalia.com, =?UTF-8?q?Andr=C3=A9=20Almeida?= Subject: [PATCH v3 4/4] drm/amdgpu: Document gfx_off members of struct amdgpu_gfx Date: Wed, 10 Aug 2022 20:28:58 -0300 Message-Id: <20220810232858.11844-5-andrealmeid@igalia.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220810232858.11844-1-andrealmeid@igalia.com> References: <20220810232858.11844-1-andrealmeid@igalia.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add comments to document gfx_off related members of struct amdgpu_gfx. Signed-off-by: Andr=C3=A9 Almeida --- drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/= amdgpu/amdgpu_gfx.h index 1b8b4a5270c9..8abdf41d0f83 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h @@ -332,12 +332,12 @@ struct amdgpu_gfx { uint32_t srbm_soft_reset; =20 /* gfx off */ - bool gfx_off_state; /* true: enabled, false: d= isabled */ - struct mutex gfx_off_mutex; - uint32_t gfx_off_req_count; /* default 1, enable g= fx off: dec 1, disable gfx off: add 1 */ - struct delayed_work gfx_off_delay_work; - uint32_t gfx_off_residency; - uint64_t gfx_off_entrycount; + bool gfx_off_state; /* true: enabled, fal= se: disabled */ + struct mutex gfx_off_mutex; /* mutex to change gf= xoff state */ + uint32_t gfx_off_req_count; /* default 1, enable = gfx off: dec 1, disable gfx off: add 1 */ + struct delayed_work gfx_off_delay_work; /* async work to set = gfx block off */ + uint32_t gfx_off_residency; /* last logged reside= ncy */ + uint64_t gfx_off_entrycount; /* count of times GPU= has get into GFXOFF state */ =20 /* pipe reservation */ struct mutex pipe_reserve_mutex; --=20 2.37.1