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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DM6NAM11FT027.mail.protection.outlook.com (10.13.172.205) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5504.14 via Frontend Transport; Fri, 5 Aug 2022 21:51:58 +0000 Received: from fritz.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.28; Fri, 5 Aug 2022 16:51:57 -0500 From: Kim Phillips To: , , , , , , CC: , , Subject: [PATCH v2] x86/bugs: Enable STIBP for IBPB mitigated RetBleed Date: Fri, 5 Aug 2022 16:50:09 -0500 Message-ID: <20220805215009.498407-1-kim.phillips@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: aa44e9c2-5da5-47b4-d953-08da772cb890 X-MS-TrafficTypeDiagnostic: CY5PR12MB6060:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Aug 2022 21:51:58.4175 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: aa44e9c2-5da5-47b4-d953-08da772cb890 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT027.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6060 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" AMD's "Technical Guidance for Mitigating Branch Type Confusion, Rev. 1.0 2022-07-12" whitepaper, under section 6.1.2 "IBPB On Privileged Mode Entry / SMT Safety" says: "Similar to the Jmp2Ret mitigation, if the code on the sibling thread cannot be trusted, software should set STIBP to 1 or disable SMT to ensure SMT safety when using this mitigation." So, like already being done for retbleed=3Dunret, the also for retbleed=3Dibpb, force STIBP on machines that have it, and report its SMT vulnerability status accordingly. Link: https://bugzilla.kernel.org/show_bug.cgi?id=3D206537 Fixes: 3ebc17006888 ("x86/bugs: Add retbleed=3Dibpb") Signed-off-by: Kim Phillips --- .../admin-guide/kernel-parameters.txt | 20 ++++++++++++++----- arch/x86/kernel/cpu/bugs.c | 10 ++++++---- 2 files changed, 21 insertions(+), 9 deletions(-) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentatio= n/admin-guide/kernel-parameters.txt index ef9f80b1ddde..c1061e7df55d 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -5237,20 +5237,30 @@ Speculative Code Execution with Return Instructions) vulnerability. =20 + AMD-based unret and ibpb mitigations alone do not stop + sibling threads influencing the predictions of other sibling + threads. For that reason, we use STIBP on processors + that support it, and mitigate SMT on processors that don't. + off - no mitigation auto - automatically select a migitation auto,nosmt - automatically select a mitigation, disabling SMT if necessary for the full mitigation (only on Zen1 and older without STIBP). - ibpb - mitigate short speculation windows on + ibpb - [AMD] Mitigate short speculation windows on basic block boundaries too. Safe, highest - perf impact. - unret - force enable untrained return thunks, + perf impact. It also enables STIBP if + present. + ibpb,nosmt - [AMD] Like ibpb, but will disable SMT when STIBP + is not available. This is the alternative for + systems which do not have STIBP. + unret - [AMD] Force enable untrained return thunks, only effective on AMD f15h-f17h based systems. - unret,nosmt - like unret, will disable SMT when STIBP - is not available. + unret,nosmt - [AMD] Like unret, but will disable SMT when STIBP + is not available. This is the alternative for + systems which do not have STIBP. =20 Selecting 'auto' will choose a mitigation method at run time according to the CPU. diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index 6761668100b9..d50686ca5870 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -152,7 +152,7 @@ void __init check_bugs(void) /* * spectre_v2_user_select_mitigation() relies on the state set by * retbleed_select_mitigation(); specifically the STIBP selection is - * forced for UNRET. + * forced for UNRET or IBPB. */ spectre_v2_user_select_mitigation(); ssb_select_mitigation(); @@ -1179,7 +1179,8 @@ spectre_v2_user_select_mitigation(void) boot_cpu_has(X86_FEATURE_AMD_STIBP_ALWAYS_ON)) mode =3D SPECTRE_V2_USER_STRICT_PREFERRED; =20 - if (retbleed_mitigation =3D=3D RETBLEED_MITIGATION_UNRET) { + if (retbleed_mitigation =3D=3D RETBLEED_MITIGATION_UNRET || + retbleed_mitigation =3D=3D RETBLEED_MITIGATION_IBPB) { if (mode !=3D SPECTRE_V2_USER_STRICT && mode !=3D SPECTRE_V2_USER_STRICT_PREFERRED) pr_info("Selecting STIBP always-on mode to complement retbleed mitigati= on\n"); @@ -2320,10 +2321,11 @@ static ssize_t srbds_show_state(char *buf) =20 static ssize_t retbleed_show_state(char *buf) { - if (retbleed_mitigation =3D=3D RETBLEED_MITIGATION_UNRET) { + if (retbleed_mitigation =3D=3D RETBLEED_MITIGATION_UNRET || + retbleed_mitigation =3D=3D RETBLEED_MITIGATION_IBPB) { if (boot_cpu_data.x86_vendor !=3D X86_VENDOR_AMD && boot_cpu_data.x86_vendor !=3D X86_VENDOR_HYGON) - return sprintf(buf, "Vulnerable: untrained return thunk on non-Zen u= arch\n"); + return sprintf(buf, "Vulnerable: untrained return thunk / IBPB on no= n-AMD based uarch\n"); =20 return sprintf(buf, "%s; SMT %s\n", retbleed_strings[retbleed_mitigation], --=20 2.34.1