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([93.107.66.220]) by smtp.gmail.com with ESMTPSA id b10-20020a056000054a00b00220633d96f2sm5210086wrf.72.2022.08.05.09.29.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Aug 2022 09:29:04 -0700 (PDT) From: Conor Dooley To: Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Palmer Dabbelt , Paul Walmsley , Albert Ou Cc: Daniel Lezcano , Anup Patel , Conor Dooley , Guo Ren , Sagar Kadam , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, qemu-riscv@nongnu.org, Rob Herring Subject: [PATCH 1/3] dt-bindings: timer: sifive,clint: add legacy riscv compatible Date: Fri, 5 Aug 2022 17:28:43 +0100 Message-Id: <20220805162844.1554247-2-mail@conchuod.ie> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220805162844.1554247-1-mail@conchuod.ie> References: <20220805162844.1554247-1-mail@conchuod.ie> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Conor Dooley While "real" hardware might not use the compatible string "riscv,clint0" it is present in the driver & QEMU uses it for automatically generated virt machine dtbs. To avoid dt-validate problems with QEMU produced dtbs, such as the following, add it to the binding. riscv-virt.dtb: clint@2000000: compatible:0: 'sifive,clint0' is not one of = ['sifive,fu540-c000-clint', 'starfive,jh7100-clint', 'canaan,k210-clint'] Reported-by: Rob Herring Link: https://lore.kernel.org/linux-riscv/20220803170552.GA2250266-robh@ker= nel.org/ Signed-off-by: Conor Dooley --- .../bindings/timer/sifive,clint.yaml | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Do= cumentation/devicetree/bindings/timer/sifive,clint.yaml index e64f46339079..9fcf20942582 100644 --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml @@ -22,12 +22,18 @@ description: =20 properties: compatible: - items: - - enum: - - sifive,fu540-c000-clint - - starfive,jh7100-clint - - canaan,k210-clint - - const: sifive,clint0 + oneOf: + - items: + - enum: + - sifive,fu540-c000-clint + - starfive,jh7100-clint + - canaan,k210-clint + - const: sifive,clint0 + - items: + - const: sifive,clint0 + - const: riscv,clint0 + deprecated: true + description: For legacy systems & the qemu virt machine only =20 description: Should be ",-clint" and "sifive,clint". --=20 2.37.1 From nobody Sat Apr 11 21:03:41 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 52AB4C00140 for ; Fri, 5 Aug 2022 16:29:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241281AbiHEQ3T (ORCPT ); Fri, 5 Aug 2022 12:29:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58862 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240999AbiHEQ3I (ORCPT ); Fri, 5 Aug 2022 12:29:08 -0400 Received: from mail-wm1-x333.google.com (mail-wm1-x333.google.com [IPv6:2a00:1450:4864:20::333]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 395201116B for ; Fri, 5 Aug 2022 09:29:07 -0700 (PDT) Received: by mail-wm1-x333.google.com with SMTP id i128-20020a1c3b86000000b003a3a22178beso4199151wma.3 for ; Fri, 05 Aug 2022 09:29:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=conchuod.ie; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=XYwLdkCxi/i5yAItJxUUyXuQNOjzCE2mt/Ff4B2y6Cs=; b=D3jxpRS5zNs90vY2YI73WI0Sebg+PIYbtdcLdZdVJEXt3MBup6LCK2JIBzVVc9luf/ y+mycZVPceDjrWQVGmfZ+sxZXcbWaL3763eF+Q+DVIutHNzi0RLCew0mxmG7/kIfLpZ7 vd2UHhO6bKZq2M2BwoTDjQ3+TgKGoGMYtrEJ7e6B1dAuq64Hny8AXJO4zU7fKCqwp9Y4 XqNFWxfQxCabjC6uSb/6FW+5T/zzzug2dsC9ovC7y6kN2H0bGhe/mof5pv9jfOu9lrLj Jx8RXO1fH6Lhe+YFFJEXwg8WmUhG2kUGCItPfw3nN1RjSrrl4qMrjHweVP2pn41EcyL1 yILg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=XYwLdkCxi/i5yAItJxUUyXuQNOjzCE2mt/Ff4B2y6Cs=; b=tf0bKVjv4nNfNHjuYV8Zry3l5mD9r1UQ/ypFxTxTrbUG6cJRZ9TX8nnD5i6YZcGjyg RiuCsA42pgznMTn9gsk2X3OWOkThIAvp/Dh3ZM8VjbpqcAbuJ1LYUSUbR9fA4t9Rjj3/ R0Nt9I4pl7ABZeyp6TgTbVAfnUmk09lRoNb68xHmoDY23BM4msXClXwThH0ARcDmhpMP h8vr928C7MIomPvLHbK3RZLOtduqGJnThXB0OL3Z8LnQ0M+/pmZPkakfbZdVUZJ75mA6 TDjS9VJDAnnLESbz6QDeqGjIWTS07Qp9KWQRYvBn4g0tuRvEziWZ499Do0Fzxl5q8Eiu zvGg== X-Gm-Message-State: ACgBeo1JVvOzGlyaK92SWFsdc0ikP7IBiOnvfRXasTs078OASK3nmzhG dzGQpVFrkmoxJTjBSvZrjkdq8g== X-Google-Smtp-Source: AA6agR72z7gXpSrSt4MlK0Qii9Fz4lxO9+YCgAXzA44zWKFpX88wGi7wvDKIHf1SjUomkA4m7/Xc+g== X-Received: by 2002:a05:600c:3d8d:b0:3a3:15a8:a8e1 with SMTP id bi13-20020a05600c3d8d00b003a315a8a8e1mr5151407wmb.167.1659716945693; Fri, 05 Aug 2022 09:29:05 -0700 (PDT) Received: from henark71.. ([93.107.66.220]) by smtp.gmail.com with ESMTPSA id b10-20020a056000054a00b00220633d96f2sm5210086wrf.72.2022.08.05.09.29.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Aug 2022 09:29:05 -0700 (PDT) From: Conor Dooley To: Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Palmer Dabbelt , Paul Walmsley , Albert Ou Cc: Daniel Lezcano , Anup Patel , Conor Dooley , Guo Ren , Sagar Kadam , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, qemu-riscv@nongnu.org, Rob Herring Subject: [PATCH 2/3] dt-bindings: interrupt-controller: sifive,plic: add legacy riscv compatible Date: Fri, 5 Aug 2022 17:28:44 +0100 Message-Id: <20220805162844.1554247-3-mail@conchuod.ie> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220805162844.1554247-1-mail@conchuod.ie> References: <20220805162844.1554247-1-mail@conchuod.ie> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Conor Dooley While "real" hardware might not use the compatible string "riscv,plic0" it is present in the driver & QEMU uses it for automatically generated virt machine dtbs. To avoid dt-validate problems with QEMU produced dtbs, such as the following, add it to the binding. riscv-virt.dtb: plic@c000000: compatible: 'oneOf' conditional failed, one m= ust be fixed: 'sifive,plic-1.0.0' is not one of ['sifive,fu540-c000-plic', 'starf= ive,jh7100-plic', 'canaan,k210-plic'] 'sifive,plic-1.0.0' is not one of ['allwinner,sun20i-d1-plic'] 'sifive,plic-1.0.0' was expected 'thead,c900-plic' was expected riscv-virt.dtb: plic@c000000: '#address-cells' is a required property Reported-by: Rob Herring Link: https://lore.kernel.org/linux-riscv/20220803170552.GA2250266-robh@ker= nel.org/ Signed-off-by: Conor Dooley --- .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,= plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/si= five,plic-1.0.0.yaml index 92e0f8c3eff2..eb07c4f1a201 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.= 0.0.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.= 0.0.yaml @@ -66,6 +66,11 @@ properties: - enum: - allwinner,sun20i-d1-plic - const: thead,c900-plic + - items: + - const: sifive,plic-1.0.0 + - const: riscv,plic0 + deprecated: true + description: For legacy systems & the qemu virt machine only =20 reg: maxItems: 1 --=20 2.37.1 From nobody Sat Apr 11 21:03:41 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E7A87C25B08 for ; Fri, 5 Aug 2022 16:29:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241289AbiHEQ3Y (ORCPT ); Fri, 5 Aug 2022 12:29:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58872 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241115AbiHEQ3J (ORCPT ); Fri, 5 Aug 2022 12:29:09 -0400 Received: from mail-wr1-x435.google.com (mail-wr1-x435.google.com [IPv6:2a00:1450:4864:20::435]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5AFD91704F for ; Fri, 5 Aug 2022 09:29:08 -0700 (PDT) Received: by mail-wr1-x435.google.com with SMTP id l22so3808115wrz.7 for ; Fri, 05 Aug 2022 09:29:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=conchuod.ie; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=Bx9G8JNLiLJhDs2y+OulTQ6Arh93SHt8PJNhnkzS76A=; b=G8MjgRH1Dn5QHvCiGLUoHF1aRHWwuzqsY8+wvXJca/a+ZTHD0d/fJq9ByzAG71C4Gm brpuYzE4q5EjV6KvPCrpP4q8RpKDe6BQP38FTgiaz7FvOaWB6HnBXC7Y+QemmGTQ6XFG Lql/qMKUyGD9o89w4PxplbuWHyocXiBfg11Ydjl3fzyMGp0iFa5haHQaEJ6LYLEGv/VD VoFzWhQ3mh9Itj2HrYNPxF09k6/cIDE9Bhv/zErgH0H7Z96OQE0yeeQlrN1EThLHsKpH JEYKHdu+rxrhXp70NsNm7i69uxBxb+6KjfurAgrsGgo0faWi1e/J/E9qFugnQXv6KItI NW8g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=Bx9G8JNLiLJhDs2y+OulTQ6Arh93SHt8PJNhnkzS76A=; b=enH77B53FJJeWvyv50Atapmq7Cn5K5Q5YV447atdYzaeXBiYYmINUA0AnSXXZnKLfS UxGnD7SU2VNBDatB4Wy+VT8jpUVooAMQ35BQSxoyM6c+MBAMFsIQTmnkQMwkC5/cz1qT OuwhjrF02dICB6BMReYvpo46oiAdhQo+mzYNMzYyVDJQKmHZVf6pOal5UVUu7FrlKHeT vw1E981eW2canVT5RMGBaLdJ6beyS1vjJBJT6D2WqggMUK1utbVx15km+5oE3lmFANA0 fT58UThqyNW9ho0yLqkOuXidFFoGIRqSONCJSRisCmGKBD/MRMeTIEe4Uv1UYKOCPi2b L7zg== X-Gm-Message-State: ACgBeo1Ju3iERhUK8aG8gElaS/qk6yHm1eEldeFUvj/OXpoMDcVm5zRf C770/CG98uYBcoZIR07vKP3d1w== X-Google-Smtp-Source: AA6agR4qNHuK519Im+LmKC2Dyrt7fi+TNPv6Ialp08tZQks0jZtMsiBr2xk+CxzRIiLrK+LeQ/NxSg== X-Received: by 2002:adf:fbc6:0:b0:21d:3fc3:99e with SMTP id d6-20020adffbc6000000b0021d3fc3099emr4737953wrs.550.1659716946942; Fri, 05 Aug 2022 09:29:06 -0700 (PDT) Received: from henark71.. ([93.107.66.220]) by smtp.gmail.com with ESMTPSA id b10-20020a056000054a00b00220633d96f2sm5210086wrf.72.2022.08.05.09.29.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Aug 2022 09:29:06 -0700 (PDT) From: Conor Dooley To: Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Palmer Dabbelt , Paul Walmsley , Albert Ou Cc: Daniel Lezcano , Anup Patel , Conor Dooley , Guo Ren , Sagar Kadam , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, qemu-riscv@nongnu.org, Rob Herring Subject: [PATCH 3/3] dt-bindings: riscv: add new riscv,isa strings for emulators Date: Fri, 5 Aug 2022 17:28:45 +0100 Message-Id: <20220805162844.1554247-4-mail@conchuod.ie> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220805162844.1554247-1-mail@conchuod.ie> References: <20220805162844.1554247-1-mail@conchuod.ie> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Conor Dooley The QEMU virt and spike machines currently export a riscv,isa string of "rv64imafdcsuh", but this obviously has illegal extensions in it. The presense of "su" is a QEMU bug, so add an entry for the valid portion of the isa string. Reported-by: Rob Herring Link: https://lore.kernel.org/linux-riscv/20220803170552.GA2250266-robh@ker= nel.org/ Signed-off-by: Conor Dooley --- Although the commit message says "a" string, I have added more than one isa string. My patched version of QEMU emits the full string with the multi letter extensions and I am not sure what the policy is for including them in the binding. Obviously I am more than willing to change the patch text if needed. --- Documentation/devicetree/bindings/riscv/cpus.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentat= ion/devicetree/bindings/riscv/cpus.yaml index d632ac76532e..59b942c5b9aa 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -77,6 +77,8 @@ properties: enum: - rv64imac - rv64imafdc + - rv64imafdch + - rv64imafdch_zicsr_zifencei_zba_zbb_zbc_zbs =20 # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here timebase-frequency: false --=20 2.37.1