From nobody Sat Apr 11 20:58:56 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3D0DDC3F6B0 for ; Fri, 5 Aug 2022 12:19:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240701AbiHEMTN (ORCPT ); Fri, 5 Aug 2022 08:19:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55848 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240658AbiHEMTI (ORCPT ); Fri, 5 Aug 2022 08:19:08 -0400 Received: from mail-ed1-x533.google.com (mail-ed1-x533.google.com [IPv6:2a00:1450:4864:20::533]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F3C3E7823A for ; Fri, 5 Aug 2022 05:19:06 -0700 (PDT) Received: by mail-ed1-x533.google.com with SMTP id b16so3162151edd.4 for ; Fri, 05 Aug 2022 05:19:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc; bh=unDWnF6HPmVWReddvgna+5d9gjeuo0raSvPQa0BEduo=; b=L2Iw0f6QqFnxvHpQZx1RKYQRMJIcN2uSxqz2ZFl1nMmvB5wRe7FhqOwWh4SrABpWx1 twFImOeI4yxodTkB/FR4sw6CP3SF/G69ha39oIeIdhzYkEyaf264aeRVckc8bHaZMERB 0EQaHo5zwSI7RKSG/K+UFJFBAhHNG6zlPCeILj85q3TbTonCMNzfpnwFXsBSBrPi+Fnt 8oJw68tBYSRtaYSdtDIUmcniMavAtFJql/xamLg9+gvFphlY90emFf8VjdExWshct95j kHWai7ihKf+bAKdbQGgadmoqV03DylXfROrVPxZXXAVJuQ1AuhiPxS/PcVlSh+b1H3TI woaQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc; bh=unDWnF6HPmVWReddvgna+5d9gjeuo0raSvPQa0BEduo=; b=psnFiu9bUp7CkGiN/IpBiP8W/2M8+ecw5KRr19W8j4iX6tIQPY44ecySTdKAty4fc3 1amv/WCvthLcy4tuxU5XQHqKZ/2ScdyZrQLHd+H2wzpYblGp4p0YKxplghjH7oeOax7W TQoagAfhjj3aery2XcgKSsxW9OVYbOMMoNr0eWP5x/11lPX8w6YD0A1HQ7FOZqb8PAAe Gvy9Y4dPqcGM0K5A9HpmaYQVehiJgMUrG7PBbLaoRKUSviKzogAysDuAlxBTdYKWUeiG laQg92lG9z8HOI9YUGNSe0ms19khNngVkQsF9cM7s/vpmRcf+vc+OhLX/6ocef6BRh5C 3UJQ== X-Gm-Message-State: ACgBeo2YTph4ZaiLC94z3kn4k3nYuFVL6XLgGvnHqvPbGu9XXBsB64R2 uBT/okrBkA73DHY+0JQGFffmag== X-Google-Smtp-Source: AA6agR6I8Ts90gv0xcLO6i3FVR8tZU2PU9eEjeiG437F7M3n5uMeDxVxWBhahrKXMGwxebZcUC120g== X-Received: by 2002:a05:6402:292:b0:43c:ee5e:a5da with SMTP id l18-20020a056402029200b0043cee5ea5damr6428365edv.181.1659701945406; Fri, 05 Aug 2022 05:19:05 -0700 (PDT) Received: from localhost.localdomain (2a02-8440-5241-be09-b892-f882-607f-7a79.rev.sfr.net. [2a02:8440:5241:be09:b892:f882:607f:7a79]) by smtp.gmail.com with ESMTPSA id kx13-20020a170907774d00b0072b3464c043sm1506111ejc.116.2022.08.05.05.19.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Aug 2022 05:19:04 -0700 (PDT) From: Jerome Neanne To: lgirdwood@gmail.com, broonie@kernel.org, robh+dt@kernel.org, nm@ti.com, kristo@kernel.org, dmitry.torokhov@gmail.com Cc: khilman@baylibre.com, narmstrong@baylibre.com, msp@baylibre.com, j-keerthy@ti.com, lee.jones@linaro.org, jneanne@baylibre.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-input@vger.kernel.org Subject: [PATCH v3 01/10] DONOTMERGE: arm64: dts: ti: Add TI TPS65219 PMIC support for AM642 SK board. Date: Fri, 5 Aug 2022 14:18:43 +0200 Message-Id: <20220805121852.21254-2-jneanne@baylibre.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220805121852.21254-1-jneanne@baylibre.com> References: <20220805121852.21254-1-jneanne@baylibre.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add support fot the TI Power Management IC TPS65219 on the AM642 SKEVM board. Needed for driver testing but official board support pending. TI commitment is required before board upstream kick-off. Signed-off-by: Jerome Neanne --- arch/arm64/boot/dts/ti/k3-am642-sk.dts | 104 +++++++++++++++++++++++++ 1 file changed, 104 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/t= i/k3-am642-sk.dts index 2620469a7517..565b50810579 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts @@ -150,6 +150,20 @@ vin-supply =3D <&com8_ls_en>; gpio =3D <&main_gpio0 48 GPIO_ACTIVE_HIGH>; }; + + vsel_sd_nddr: gpio-regulator { + compatible =3D "regulator-gpio"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&vsel_sd_nddr_pins_default>; + regulator-name =3D "tps65219-LDO1-SEL-SD"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + vin-supply =3D <&ldo1_reg>; + gpios =3D <&main_gpio0 45 GPIO_ACTIVE_HIGH>; + states =3D <1800000 0x0>, + <3300000 0x1>; + }; }; =20 &main_pmx0 { @@ -181,6 +195,13 @@ >; }; =20 + main_i2c0_pins_default: main-i2c0-pins-default { + pinctrl-single,pins =3D < + AM64X_IOPAD(0x0260, PIN_INPUT_PULLUP, 0) /* (A18) I2C0_SCL */ + AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0) /* (B18) I2C0_SDA */ + >; + }; + main_i2c1_pins_default: main-i2c1-pins-default { pinctrl-single,pins =3D < AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */ @@ -267,6 +288,12 @@ AM64X_IOPAD(0x00bc, PIN_INPUT, 7) /* (U8) GPIO0_46 */ >; }; + + vsel_sd_nddr_pins_default: vsel-sd-nddr-pins-default { + pinctrl-single,pins =3D < + AM64X_IOPAD(0x00b8, PIN_INPUT, 7) /* (Y7) PRG1_PRU0_GPO0.GPIO0_45 */ + >; + }; }; =20 &mcu_uart0 { @@ -315,6 +342,83 @@ status =3D "disabled"; }; =20 +&main_i2c0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_i2c0_pins_default>; + clock-frequency =3D <400000>; + status =3D "okay"; + + tps65219: pmic@30 { + compatible =3D "ti,tps65219"; + reg =3D <0x30>; + system-power-controller; + + buck1-supply =3D <&vcc_3v3_sys>; + buck2-supply =3D <&vcc_3v3_sys>; + buck3-supply =3D <&vcc_3v3_sys>; + ldo1-supply =3D <&vcc_3v3_sys>; + ldo2-supply =3D <&buck2_reg>; + ldo3-supply =3D <&vcc_3v3_sys>; + ldo4-supply =3D <&vcc_3v3_sys>; + + regulators { + buck1_reg: buck1 { + regulator-name =3D "VDD_CORE"; + regulator-min-microvolt =3D <750000>; + regulator-max-microvolt =3D <1000000>; + regulator-boot-on; + regulator-always-on; + }; + + buck2_reg: buck2 { + regulator-name =3D "VCC1V8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + buck3_reg: buck3 { + regulator-name =3D "VDD_LPDDR4"; + regulator-min-microvolt =3D <1100000>; + regulator-max-microvolt =3D <1100000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: ldo1 { + regulator-name =3D "VDDSHV_SD_IO_PMIC"; + regulator-min-microvolt =3D <1000000>; + regulator-max-microvolt =3D <3300000>; + regulator-allow-bypass; + }; + + ldo2_reg: ldo2 { + regulator-name =3D "VDDAR_CORE"; + regulator-min-microvolt =3D <850000>; + regulator-max-microvolt =3D <850000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3_reg: ldo3 { + regulator-name =3D "VDDA_1V8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4_reg: ldo4 { + regulator-name =3D "VDD_PHY_2V5"; + regulator-min-microvolt =3D <2500000>; + regulator-max-microvolt =3D <2500000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; &main_i2c1 { pinctrl-names =3D "default"; pinctrl-0 =3D <&main_i2c1_pins_default>; --=20 2.17.1 From nobody Sat Apr 11 20:58:56 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 22CECC00140 for ; Fri, 5 Aug 2022 12:19:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240733AbiHEMTQ (ORCPT ); Fri, 5 Aug 2022 08:19:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55974 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240723AbiHEMTM (ORCPT ); Fri, 5 Aug 2022 08:19:12 -0400 Received: from mail-ed1-x52e.google.com (mail-ed1-x52e.google.com [IPv6:2a00:1450:4864:20::52e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A65127858B for ; Fri, 5 Aug 2022 05:19:09 -0700 (PDT) Received: by mail-ed1-x52e.google.com with SMTP id t5so3114075edc.11 for ; Fri, 05 Aug 2022 05:19:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc; bh=MAf7g1yH66QfElwkollldhEjdf2FGegN5lxrXOLWjy0=; b=q53Kv+UgtLvMRTdzxh7yngF2st+EZQIAQtMXeXYFgUN80qdO1a5yYwmUS7OwbjzNh/ TdghSQa8ufvvm0/kCWPmT01tq8rASXhI2s0DIPASdUfhD4g4xsh5rb6daUv+Rknl4tTM 0XIo8FTW2bzLaZF5pBjfIJbt/i/mMktQ/fxJ6J33QE/wNROxAV1OhVJRi8x6er8VUyD+ cz8+s6fTZ0hBw6zGQNcjoKTtO+bM88BYp2zn5+RCZVgTe5Y7NR8NQ4e7SToZQ3pxwGVW 5AH+2DW1LTcJpsSfvL782ZAj32oP7FXQ714N5fTz8gpgu2V2BGt/LCyIa3jBME5ZLlrL 4MBw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc; bh=MAf7g1yH66QfElwkollldhEjdf2FGegN5lxrXOLWjy0=; b=dSJAti/QdoMDiwVYm1AffE06fwg0I2tXK+5q10aakQbr1u54368UhNllOIctY5zkAb 9ALMqqUNwbvL8meukFcg0kNlcpJqoOG9WoiSJMePYbSjqtELVl0avfXR0PAn+fQJuuEM asOgq5dTHNTAzrdd+wnOrf7CWduu9qWl5iNVTVoqewqrAvBTiX9DkHOrO3kiy1qWQGRV uprl8y+N4lo77fnFxn912d4epg+ipdE4qa9Y+ouYDufdIG7EtvmFvZIXrlM1LRVAeHXA 2p04cb1TXhBo+hIKMOhSkcyP/uDJJuliWZvKgjMLu0f92jSwZV0BApMvjfLLV3AOt7oA JgQw== X-Gm-Message-State: ACgBeo0EvSBop4LTgErTVSytvTyoszj9Fs7d62Sf4PoKoSYJtTEh5Ro6 bmqI8H0oMq62H/WxQbv4BOZjmg== X-Google-Smtp-Source: AA6agR7RIEEwPz8yN/vPznJuUdG7h5rxeImCRN2lvUK0/EQKUts6mozrxr0q7hOnmN7p3Svvhff7Sw== X-Received: by 2002:a05:6402:611:b0:43c:cb2d:76c0 with SMTP id n17-20020a056402061100b0043ccb2d76c0mr6436094edv.425.1659701948521; Fri, 05 Aug 2022 05:19:08 -0700 (PDT) Received: from localhost.localdomain (2a02-8440-5241-be09-b892-f882-607f-7a79.rev.sfr.net. [2a02:8440:5241:be09:b892:f882:607f:7a79]) by smtp.gmail.com with ESMTPSA id kx13-20020a170907774d00b0072b3464c043sm1506111ejc.116.2022.08.05.05.19.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Aug 2022 05:19:08 -0700 (PDT) From: Jerome Neanne To: lgirdwood@gmail.com, broonie@kernel.org, robh+dt@kernel.org, nm@ti.com, kristo@kernel.org, dmitry.torokhov@gmail.com Cc: khilman@baylibre.com, narmstrong@baylibre.com, msp@baylibre.com, j-keerthy@ti.com, lee.jones@linaro.org, jneanne@baylibre.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-input@vger.kernel.org Subject: [PATCH v3 02/10] DONOTMERGE: arm64: dts: ti: Add pinmux and irq mapping for TPS65219 external interrupts Date: Fri, 5 Aug 2022 14:18:44 +0200 Message-Id: <20220805121852.21254-3-jneanne@baylibre.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220805121852.21254-1-jneanne@baylibre.com> References: <20220805121852.21254-1-jneanne@baylibre.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Interrupt occurring on PMIC TPS65219 is propagated to SOC through EXTINTn pin connected to gic500 interrupt controller Needed for driver testing but official board support pending. TI commitment is required before board upstream kick-off. Signed-off-by: Jerome Neanne --- arch/arm64/boot/dts/ti/k3-am642-sk.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/t= i/k3-am642-sk.dts index 565b50810579..1f7ce60ecb57 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts @@ -294,6 +294,12 @@ AM64X_IOPAD(0x00b8, PIN_INPUT, 7) /* (Y7) PRG1_PRU0_GPO0.GPIO0_45 */ >; }; + + pmic_irq_pins_default: pmic-irq-pins-default { + pinctrl-single,pins =3D < + AM64X_IOPAD(0x0278, PIN_INPUT, 0) /* (C19) EXTINTn */ + >; + }; }; =20 &mcu_uart0 { @@ -352,6 +358,10 @@ compatible =3D "ti,tps65219"; reg =3D <0x30>; system-power-controller; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pmic_irq_pins_default>; + interrupt-parent =3D <&gic500>; + interrupts =3D ; =20 buck1-supply =3D <&vcc_3v3_sys>; buck2-supply =3D <&vcc_3v3_sys>; --=20 2.17.1 From nobody Sat Apr 11 20:58:56 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EC08FC00140 for ; Fri, 5 Aug 2022 12:19:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237809AbiHEMTV (ORCPT ); Fri, 5 Aug 2022 08:19:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55978 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240728AbiHEMTM (ORCPT ); Fri, 5 Aug 2022 08:19:12 -0400 Received: from mail-ej1-x62e.google.com (mail-ej1-x62e.google.com [IPv6:2a00:1450:4864:20::62e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DA81B78212 for ; Fri, 5 Aug 2022 05:19:11 -0700 (PDT) Received: by mail-ej1-x62e.google.com with SMTP id a7so4755458ejp.2 for ; Fri, 05 Aug 2022 05:19:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc; bh=TEgAz8TyTEUxFcTpNCv4lGZ7t5+w4UkFWYn6r6UPn6c=; b=GdlW2vrkR8Va0X99n1iERUM39qc5sgEPSCjAR8k9yixoELLFcDdtyx0CpxG3GJ/HmJ ZahKVF7vjOa8jNj8pFFIBkkgsZeMpGsiqgY01rXRrPOk3y4Qobwdgo/9aFYVl7ZsBkBU EXWm6C+okDN1w0VIjgK1RumilBXQ2pXnNn7cEGmoLaKgnhsYElerxmLHjVQcV46raskC 4zr4XKYJxFrs1Crin8TlBdOoECDvh6BggXxn9UBDHp7vNC07tl5bqXttcZi4afbFu4CB mAN67OOXeVo9bNsr68oIJuJpvy8sjguUX52+Hrtz1vHEswlPu7iuwCX0me8LzZXQ+Xs5 rvBg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc; bh=TEgAz8TyTEUxFcTpNCv4lGZ7t5+w4UkFWYn6r6UPn6c=; b=HZsnJTBr2WrOm84cVUgLf2sXScFIdNJpLlmIh+y+iPPxAJTRJKfwp8rCWV1l1tmqeO MUtc/kegxBLohaLEB7XGB4ihPl5/K/ZMOwCn2CPJpHuO12n3HMlf/C9K51casE621MQV Gug76nme1sfYCWd0ORGf+759nyINKIN3w3kK6TBt/J1LJPW3XUXBRD6fv17enHmBZQxt bj1rAOOfN3K0EoH7dZN6hviL+7GS9kkV5lwIOmkhqBkN6VlwNHeulFr+6N3qaz/obiC7 NAxZLcDwFJuhv5jGVOx22WsWqbvO2qAs9rUiloSmjWI4+9qPV5GgFYLUBIb3TmMUrNgX LK8Q== X-Gm-Message-State: ACgBeo0MPYDF4BGNu3DxKlTYyTh3QbNGo+D56lz0zerJKlSqnZv5Gig5 YzssHWi1HSMAE8yY5zX65j9gLQ== X-Google-Smtp-Source: AA6agR7U9bW7l6YeondNI0IKqukUvOZaPzQy8h7T/tdMPVGZDBOXIp3O3HkM71h2OzKTbTAKiNwOYQ== X-Received: by 2002:a17:906:93f7:b0:730:da74:3454 with SMTP id yl23-20020a17090693f700b00730da743454mr4197777ejb.331.1659701951491; Fri, 05 Aug 2022 05:19:11 -0700 (PDT) Received: from localhost.localdomain (2a02-8440-5241-be09-b892-f882-607f-7a79.rev.sfr.net. [2a02:8440:5241:be09:b892:f882:607f:7a79]) by smtp.gmail.com with ESMTPSA id kx13-20020a170907774d00b0072b3464c043sm1506111ejc.116.2022.08.05.05.19.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Aug 2022 05:19:11 -0700 (PDT) From: Jerome Neanne To: lgirdwood@gmail.com, broonie@kernel.org, robh+dt@kernel.org, nm@ti.com, kristo@kernel.org, dmitry.torokhov@gmail.com Cc: khilman@baylibre.com, narmstrong@baylibre.com, msp@baylibre.com, j-keerthy@ti.com, lee.jones@linaro.org, jneanne@baylibre.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-input@vger.kernel.org Subject: [PATCH v3 03/10] DONOTMERGE: arm64: dts: ti: k3-am642-sk: Enable tps65219 power-button Date: Fri, 5 Aug 2022 14:18:45 +0200 Message-Id: <20220805121852.21254-4-jneanne@baylibre.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220805121852.21254-1-jneanne@baylibre.com> References: <20220805121852.21254-1-jneanne@baylibre.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This board uses the pin as a power-button, enable it. Needed for driver testing but official board support pending. TI commitment is required before board upstream kick-off. Signed-off-by: Markus Schneider-Pargmann Signed-off-by: Jerome Neanne --- arch/arm64/boot/dts/ti/k3-am642-sk.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/t= i/k3-am642-sk.dts index 1f7ce60ecb57..238798ea6a79 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts @@ -362,6 +362,7 @@ pinctrl-0 =3D <&pmic_irq_pins_default>; interrupt-parent =3D <&gic500>; interrupts =3D ; + ti,power-button; =20 buck1-supply =3D <&vcc_3v3_sys>; buck2-supply =3D <&vcc_3v3_sys>; --=20 2.17.1 From nobody Sat Apr 11 20:58:56 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EF7C8C00140 for ; Fri, 5 Aug 2022 12:19:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240772AbiHEMTc (ORCPT ); Fri, 5 Aug 2022 08:19:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56632 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240746AbiHEMT2 (ORCPT ); Fri, 5 Aug 2022 08:19:28 -0400 Received: from mail-ed1-x530.google.com (mail-ed1-x530.google.com [IPv6:2a00:1450:4864:20::530]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5751379692 for ; Fri, 5 Aug 2022 05:19:15 -0700 (PDT) Received: by mail-ed1-x530.google.com with SMTP id e13so3109912edj.12 for ; Fri, 05 Aug 2022 05:19:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc; bh=ZBrNwp1gHFl2Xae1KzJGBgqN04yJKsQPmkG6lAXyXkY=; b=7DatlSWT+HmPu8MMLiYslByU/UARQySrMTQMYq440e9VxeucyNDW+kWVXbUBWotSoD HgQng3XVWyf3yI2E8Ks+lnep8ra6P3P3xDCjR24m/ogrN9fv+0ywIcy7pcLf8prD7xEK r7L3MyeUw0k1CsbqI3rui93VMVocVbz4MN9oOybZ/gGK4ivAc6BCwVR6cZ5IViiAfomr Flg8htISrnwlWjX5u8MwYpGmdKz2Y1rJ+J8RjWighMXLKpTqlnOZM6tXaKsfZbIM3vPt o6L6NH9e0KhwCO2IzF2lS8V8Tfa7sYCWSpny7S32hpoJGLxFf2G4hq/J4Jj8WNDBej6R J3Hw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc; bh=ZBrNwp1gHFl2Xae1KzJGBgqN04yJKsQPmkG6lAXyXkY=; b=AQW8/e8p81tqX8UgbiU7wn9j2+c7FrQRT8nfVtFG3kDewIkMSzojTc957iryBSm5fU pb7sn6gDVc/GLSa68Qac6Xk8ITN1FJ3NTTGTzh2uukEXvJ8i0rmsCwqDaYFVri67tdQB zudFIm0ZRoRvBwyMF8XGsoyExwGoC27uDYa+hAQJu9obnUkzJu34yxB7jGxz0ZnWJ/Vb W+/yigbsFq8vf86XW57keFGGacA7hpj83q0Cj8vmNuLE8Qgnk9J5x370IMO3uaB2TASu Z5D2lMbctOx0H+Vt+Lc/Us71sqds2+Oy9N/TK1/y/VTFHAZQUGK53/x27LrQfhwnm7Fn XhZw== X-Gm-Message-State: ACgBeo1JCnBw+2gT6SOuZhdXVNrsHONfRsNmNo5QpJu/HdEo+vRTiI+/ ppkY+40hdhD3Rsjaq0nquxI5OQ== X-Google-Smtp-Source: AA6agR7Sb1gOaYyoNGw0c+ZBGHTMvLfFZfSSPLavuwmyGPimjQmVaWCcBi0sWNaqTcOwTNlJSnyc5A== X-Received: by 2002:a05:6402:240a:b0:437:d2b6:3dde with SMTP id t10-20020a056402240a00b00437d2b63ddemr6371256eda.62.1659701954806; Fri, 05 Aug 2022 05:19:14 -0700 (PDT) Received: from localhost.localdomain (2a02-8440-5241-be09-b892-f882-607f-7a79.rev.sfr.net. [2a02:8440:5241:be09:b892:f882:607f:7a79]) by smtp.gmail.com with ESMTPSA id kx13-20020a170907774d00b0072b3464c043sm1506111ejc.116.2022.08.05.05.19.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Aug 2022 05:19:14 -0700 (PDT) From: Jerome Neanne To: lgirdwood@gmail.com, broonie@kernel.org, robh+dt@kernel.org, nm@ti.com, kristo@kernel.org, dmitry.torokhov@gmail.com Cc: khilman@baylibre.com, narmstrong@baylibre.com, msp@baylibre.com, j-keerthy@ti.com, lee.jones@linaro.org, jneanne@baylibre.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-input@vger.kernel.org Subject: [PATCH v3 04/10] regulator: dt-bindings: Add TI TPS65219 PMIC bindings Date: Fri, 5 Aug 2022 14:18:46 +0200 Message-Id: <20220805121852.21254-5-jneanne@baylibre.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220805121852.21254-1-jneanne@baylibre.com> References: <20220805121852.21254-1-jneanne@baylibre.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add TPS65219 PMIC bindings using json-schema. Describe required properties and regname-supply. regname-supply is required when bypass mode is used for a regulator. Describes regulator topology. Interrupts support. Add a power-button property to configure the EN/PB/VSENSE pin as a powerbutton: TPS65219 has a multipurpose pin called EN/PB/VSENSE that can be either: - EN in which case it functions as an enable pin. - VSENSE which compares the voltages and triggers an automatic on/off request. - PB in which case it can be configured to trigger an interrupt to the SoC. ti,power-button reflects the last one of those options where the board has a button wired to the pin and triggers an interrupt on pressing it. Signed-off-by: Markus Schneider-Pargmann Signed-off-by: Jerome Neanne Reviewed-by: Rob Herring --- .../bindings/regulator/ti,tps65219.yaml | 173 ++++++++++++++++++ 1 file changed, 173 insertions(+) create mode 100644 Documentation/devicetree/bindings/regulator/ti,tps65219= .yaml diff --git a/Documentation/devicetree/bindings/regulator/ti,tps65219.yaml b= /Documentation/devicetree/bindings/regulator/ti,tps65219.yaml new file mode 100644 index 000000000000..78be79930fda --- /dev/null +++ b/Documentation/devicetree/bindings/regulator/ti,tps65219.yaml @@ -0,0 +1,173 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regulator/ti,tps65219.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI tps65219 Power Management Integrated Circuit regulators + +maintainers: + - Jerome Neanne + +description: | + Regulator nodes should be named to buck and ldo. + +properties: + compatible: + enum: + - ti,tps65219 + + reg: + maxItems: 1 + + system-power-controller: + type: boolean + description: Optional property that indicates that this device is + controlling system power. + + interrupts: + description: Short-circuit, over-current, under-voltage for regulators= , PB interrupts. + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + description: Specifies the PIN numbers and Flags, as defined in + include/dt-bindings/interrupt-controller/irq.h + const: 1 + + ti,power-button: + type: boolean + description: | + Optional property that sets the EN/PB/VSENSE pin to be a + power-button. + TPS65219 has a multipurpose pin called EN/PB/VSENSE that can be eith= er + 1. EN in which case it functions as an enable pin. + 2. VSENSE which compares the voltages and triggers an automatic + on/off request. + 3. PB in which case it can be configured to trigger an interrupt + to the SoC. + ti,power-button reflects the last one of those options + where the board has a button wired to the pin and triggers + an interrupt on pressing it. + +patternProperties: + "^buck[1-3]-supply$": + description: Input supply phandle of one regulator. + + "^ldo[1-4]-supply$": + description: Input supply phandle of one regulator. + + regulators: + type: object + description: | + list of regulators provided by this controller + + patternProperties: + "^ldo[1-4]$": + type: object + $ref: regulator.yaml# + description: + Properties for single LDO regulator. + + unevaluatedProperties: false + + "^buck[1-3]$": + type: object + $ref: regulator.yaml# + description: + Properties for single BUCK regulator. + + unevaluatedProperties: false + + additionalProperties: false + +required: + - compatible + - reg + - interrupts + - regulators + +additionalProperties: false + +examples: + - | + #include + i2c { + #address-cells =3D <1>; + #size-cells =3D <0>; + + tps65219: pmic@30 { + compatible =3D "ti,tps65219"; + reg =3D <0x30>; + buck1-supply =3D <&vcc_3v3_sys>; + buck2-supply =3D <&vcc_3v3_sys>; + buck3-supply =3D <&vcc_3v3_sys>; + ldo1-supply =3D <&vcc_3v3_sys>; + ldo2-supply =3D <&buck2_reg>; + ldo3-supply =3D <&vcc_3v3_sys>; + ldo4-supply =3D <&vcc_3v3_sys>; + + pinctrl-0 =3D <&pmic_irq_pins_default>; + + interrupt-parent =3D <&gic500>; + interrupts =3D ; + ti,power-button; + + regulators { + buck1_reg: buck1 { + regulator-name =3D "VDD_CORE"; + regulator-min-microvolt =3D <750000>; + regulator-max-microvolt =3D <750000>; + regulator-boot-on; + regulator-always-on; + }; + + buck2_reg: buck2 { + regulator-name =3D "VCC1V8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + buck3_reg: buck3 { + regulator-name =3D "VDD_LPDDR4"; + regulator-min-microvolt =3D <1100000>; + regulator-max-microvolt =3D <1100000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: ldo1 { + regulator-name =3D "VDDSHV_SD_IO_PMIC"; + regulator-min-microvolt =3D <33000000>; + regulator-max-microvolt =3D <33000000>; + }; + + ldo2_reg: ldo2 { + regulator-name =3D "VDDAR_CORE"; + regulator-min-microvolt =3D <850000>; + regulator-max-microvolt =3D <850000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3_reg: ldo3 { + regulator-name =3D "VDDA_1V8"; + regulator-min-microvolt =3D <18000000>; + regulator-max-microvolt =3D <18000000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4_reg: ldo4 { + regulator-name =3D "VDD_PHY_2V5"; + regulator-min-microvolt =3D <25000000>; + regulator-max-microvolt =3D <25000000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + }; --=20 2.17.1 From nobody Sat Apr 11 20:58:56 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1096EC00140 for ; Fri, 5 Aug 2022 12:19:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240567AbiHEMTh (ORCPT ); Fri, 5 Aug 2022 08:19:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56612 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240742AbiHEMTa (ORCPT ); Fri, 5 Aug 2022 08:19:30 -0400 Received: from mail-ej1-x630.google.com (mail-ej1-x630.google.com [IPv6:2a00:1450:4864:20::630]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2A274785BB for ; Fri, 5 Aug 2022 05:19:18 -0700 (PDT) Received: by mail-ej1-x630.google.com with SMTP id m4so4743236ejr.3 for ; Fri, 05 Aug 2022 05:19:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc; bh=VSxre6cBwjNqPPecgPAEhm/+TXo/mwZa3w41YBkjY/A=; b=f2jemr3iMPp3HJ3mxIStrf4ScIvA9+09jzfW/BAMvjBo2C7auyWSNjQdL9VlmiUvUh ZUp2AT4yqdDQ/u0d7fi3lMi2+7IF41ePf7umOeQrpHKLQwSBDn/xoCY7XQunPuwgCNtr e+d3ajYnkxC2JpZgJPyDl2DOgrQOXTIwtc6SB7HcNNiEa4TKCfy1eA9yW/q4XiWgYAl8 f1sfZ25YAW5yTC0UnEHeHEuYS+lwBNb8wTCFB6XJi6+lCqg3TnOihllrbzb7vm60CAEf ZeqnC0yQVHx+3FnrzQCNzvJMaJQwc3nWpGElEndBR3VTMt7A0x2JIuMbOEXLEZb0wQ4l zzxQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc; bh=VSxre6cBwjNqPPecgPAEhm/+TXo/mwZa3w41YBkjY/A=; b=ZwFMrWOvmFdwvxnYFRflg6uDxa2S/+DpN7lRF6L/KOraYsTJeixQsgFXTrOXJB2yx0 5B8VFxyp5tm2FapHO5Px4V0jHQNCeNtD2iu3lNLTA1GVv3PwdDX1TEjyAA1q+53cL+Dc uVG9mRSUISxgZtNQyohzUoPsryW08ci7c5zUEG2XYHFv59PofOuZOD01TRdDDco0zrQr 6oA6H5I6LKmzSXS60D1KIReMHr8kYZXols7I2wwnGveVN7Vc5rgp28UH60fFAbIYb0u9 wHfQAFQAGixH0nA/SWrfWb6VW9kFXMtp0RZENQ0R5mwaugOIz5dWiRbqJhWcyleLp1fO 2MSA== X-Gm-Message-State: ACgBeo2Kx2SqJ/rLnrzm1dlKO9EPQE6xY/AWXo1hnhTvFW0lcITJjfii PIaPFMhzrv6Bnx90bh4Z56fPbg== X-Google-Smtp-Source: AA6agR63U4PVs5yAIypIGzvAaYbphEFTkkEjAsR4FjBvFt2US08Ww66SH7QNXT9482CLVqnuQm1bPA== X-Received: by 2002:a17:906:216:b0:711:f623:8bb0 with SMTP id 22-20020a170906021600b00711f6238bb0mr5229558ejd.174.1659701957550; Fri, 05 Aug 2022 05:19:17 -0700 (PDT) Received: from localhost.localdomain (2a02-8440-5241-be09-b892-f882-607f-7a79.rev.sfr.net. [2a02:8440:5241:be09:b892:f882:607f:7a79]) by smtp.gmail.com with ESMTPSA id kx13-20020a170907774d00b0072b3464c043sm1506111ejc.116.2022.08.05.05.19.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Aug 2022 05:19:17 -0700 (PDT) From: Jerome Neanne To: lgirdwood@gmail.com, broonie@kernel.org, robh+dt@kernel.org, nm@ti.com, kristo@kernel.org, dmitry.torokhov@gmail.com Cc: khilman@baylibre.com, narmstrong@baylibre.com, msp@baylibre.com, j-keerthy@ti.com, lee.jones@linaro.org, jneanne@baylibre.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-input@vger.kernel.org Subject: [PATCH v3 05/10] mfd: drivers: Add TI TPS65219 PMIC support Date: Fri, 5 Aug 2022 14:18:47 +0200 Message-Id: <20220805121852.21254-6-jneanne@baylibre.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220805121852.21254-1-jneanne@baylibre.com> References: <20220805121852.21254-1-jneanne@baylibre.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The TPS65219 is a power management IC PMIC designed to supply a wide range of SoCs in both portable and stationary applications. Any SoC can control TPS65219 over a standard I2C interface. It contains the following components: - Regulators. - Over Temperature warning and Shut down. - GPIOs - Multi Function Pins (MFP) This patch adds support for tps65219 mfd device. At this time only the functionalities listed below are made available: - Regulators probe and functionalities - warm and cold reset support - SW shutdown support Signed-off-by: Jerome Neanne --- MAINTAINERS | 1 + drivers/mfd/Kconfig | 15 +++ drivers/mfd/Makefile | 1 + drivers/mfd/tps65219.c | 214 +++++++++++++++++++++++++++++ include/linux/mfd/tps65219.h | 251 +++++++++++++++++++++++++++++++++++ 5 files changed, 482 insertions(+) create mode 100644 drivers/mfd/tps65219.c create mode 100644 include/linux/mfd/tps65219.h diff --git a/MAINTAINERS b/MAINTAINERS index fee3ecc2d6ca..ffd533b8debc 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14840,6 +14840,7 @@ F: drivers/mfd/menelaus.c F: drivers/mfd/palmas.c F: drivers/mfd/tps65217.c F: drivers/mfd/tps65218.c +F: drivers/mfd/tps65219.c F: drivers/mfd/tps65910.c F: drivers/mfd/twl-core.[ch] F: drivers/mfd/twl4030*.c diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index 3b59456f5545..c66e56374a9a 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -1574,6 +1574,21 @@ config MFD_TPS65218 This driver can also be built as a module. If so, the module will be called tps65218. =20 +config MFD_TPS65219 + tristate "TI TPS65219 Power Management chips" + depends on I2C && OF + select MFD_CORE + select REGMAP_I2C + select REGMAP_IRQ + help + If you say yes here you get support for the TPS65219 series of + Power Management chips. + These include voltage regulators, gpio and other features + that are often used in portable devices. + + This driver can also be built as a module. If so, the module + will be called tps65219. + config MFD_TPS6586X bool "TI TPS6586x Power Management chips" depends on I2C=3Dy diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile index 858cacf659d6..a8ff3d6ea3ab 100644 --- a/drivers/mfd/Makefile +++ b/drivers/mfd/Makefile @@ -101,6 +101,7 @@ obj-$(CONFIG_TPS6507X) +=3D tps6507x.o obj-$(CONFIG_MFD_TPS65086) +=3D tps65086.o obj-$(CONFIG_MFD_TPS65217) +=3D tps65217.o obj-$(CONFIG_MFD_TPS65218) +=3D tps65218.o +obj-$(CONFIG_MFD_TPS65219) +=3D tps65219.o obj-$(CONFIG_MFD_TPS65910) +=3D tps65910.o obj-$(CONFIG_MFD_TPS65912) +=3D tps65912-core.o obj-$(CONFIG_MFD_TPS65912_I2C) +=3D tps65912-i2c.o diff --git a/drivers/mfd/tps65219.c b/drivers/mfd/tps65219.c new file mode 100644 index 000000000000..c3bf975ea6c7 --- /dev/null +++ b/drivers/mfd/tps65219.c @@ -0,0 +1,214 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Driver for TPS65219 Integrated power management chipsets +// +// Copyright (C) 2022 BayLibre Incorporated - https://www.baylibre.com/ +// +// This implementation derived from tps65218 authored by +// "J Keerthy " +// + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +static struct i2c_client *tps65219_i2c_client; + +/** + * tps65219_warm_reset: issue warm reset to SOC. + * + * @tps: Device to write to. + */ +static int tps65219_warm_reset(struct tps65219 *tps) +{ + dev_dbg(tps->dev, "warm reset"); + pr_flush(1000, true); + return regmap_update_bits(tps->regmap, TPS65219_REG_MFP_CTRL, + TPS65219_MFP_WARM_RESET_I2C_CTRL_MASK, + TPS65219_MFP_WARM_RESET_I2C_CTRL_MASK); +} + +/** + * tps65219_cold_reset: issue cold reset to SOC. + * + * @tps: Device to write to. + */ +static int tps65219_cold_reset(struct tps65219 *tps) +{ + dev_dbg(tps->dev, "cold reset"); + pr_flush(1000, true); + return regmap_update_bits(tps->regmap, TPS65219_REG_MFP_CTRL, + TPS65219_MFP_COLD_RESET_I2C_CTRL_MASK, + TPS65219_MFP_COLD_RESET_I2C_CTRL_MASK); +} + +/** + * tps65219_soft_shutdown: issue cold reset to SOC. + * + * @tps: Device to write to. + */ +static int tps65219_soft_shutdown(struct tps65219 *tps) +{ + dev_dbg(tps->dev, "software shutdown"); + pr_flush(1000, true); + return regmap_update_bits(tps->regmap, TPS65219_REG_MFP_CTRL, + TPS65219_MFP_I2C_OFF_REQ_MASK, + TPS65219_MFP_I2C_OFF_REQ_MASK); +} + +/** + * pmic_rst_restart: trig tps65219 reset to SOC. + * + * Trigged via notifier + */ +static int pmic_rst_restart(struct notifier_block *this, + unsigned long reboot_mode, void *cmd) +{ + struct tps65219 *tps; + + tps =3D container_of(this, struct tps65219, nb); + if (!tps) { + pr_err("%s: pointer to tps65219 is invalid\n", __func__); + return -ENODEV; + } + if (reboot_mode =3D=3D REBOOT_WARM) + tps65219_warm_reset(tps); + else + tps65219_cold_reset(tps); + return NOTIFY_DONE; +} + +static struct notifier_block pmic_rst_restart_nb =3D { + .notifier_call =3D pmic_rst_restart, + .priority =3D 200, +}; + +/** + * pmic_do_poweroff: trig tps65219 regulators power OFF sequence. + */ +static void pmic_do_poweroff(void) +{ + struct tps65219 *tps; + + tps =3D dev_get_drvdata(&tps65219_i2c_client->dev); + tps65219_soft_shutdown(tps); +} + +static const struct mfd_cell tps65219_cells[] =3D { + { .name =3D "tps65219-regulator", }, +}; + +static const struct regmap_config tps65219_regmap_config =3D { + .reg_bits =3D 8, + .val_bits =3D 8, + .max_register =3D TPS65219_REG_FACTORY_CONFIG_2, +}; + +static const struct of_device_id of_tps65219_match_table[] =3D { + { .compatible =3D "ti,tps65219", }, + {} +}; +MODULE_DEVICE_TABLE(of, of_tps65219_match_table); + +static int tps65219_probe(struct i2c_client *client, + const struct i2c_device_id *ids) +{ + struct tps65219 *tps; + int ret; + unsigned int chipid; + bool sys_pwr; + + tps =3D devm_kzalloc(&client->dev, sizeof(*tps), GFP_KERNEL); + if (!tps) + return -ENOMEM; + + i2c_set_clientdata(client, tps); + tps->dev =3D &client->dev; + tps->regmap =3D devm_regmap_init_i2c(client, &tps65219_regmap_config); + if (IS_ERR(tps->regmap)) { + ret =3D PTR_ERR(tps->regmap); + dev_err(tps->dev, "Failed to allocate register map: %d\n", + ret); + return ret; + } + + ret =3D regmap_read(tps->regmap, TPS65219_REG_TI_DEV_ID, &chipid); + if (ret) { + dev_err(tps->dev, "Failed to read device ID: %d\n", ret); + return ret; + } + + ret =3D devm_mfd_add_devices(tps->dev, PLATFORM_DEVID_AUTO, tps65219_cell= s, + ARRAY_SIZE(tps65219_cells), NULL, 0, + NULL); + if (ret) { + dev_err(tps->dev, "mfd_add_devices failed: %d\n", ret); + return ret; + } + + tps->nb =3D pmic_rst_restart_nb; + ret =3D register_restart_handler(&tps->nb); + if (ret) { + dev_err(tps->dev, "%s: cannot register restart handler, %d\n", + __func__, ret); + return -ENODEV; + } + + sys_pwr =3D of_property_read_bool(tps->dev->of_node, + "system-power-controller"); + + if (sys_pwr) { + if (pm_power_off) + dev_warn(tps->dev, "Setup as system-power-controller but pm_power_off f= unction already registered, overwriting\n"); + tps65219_i2c_client =3D client; + pm_power_off =3D &pmic_do_poweroff; + } + return ret; +} + +static int tps65219_remove(struct i2c_client *client) +{ + struct tps65219 *tps =3D i2c_get_clientdata(client); + + if (tps65219_i2c_client =3D=3D client) { + pm_power_off =3D NULL; + tps65219_i2c_client =3D NULL; + } + + return unregister_restart_handler(&tps->nb); +} + +static const struct i2c_device_id tps65219_id_table[] =3D { + { "tps65219", TPS65219 }, + { }, +}; +MODULE_DEVICE_TABLE(i2c, tps65219_id_table); + +static struct i2c_driver tps65219_driver =3D { + .driver =3D { + .name =3D "tps65219", + .of_match_table =3D of_tps65219_match_table, + }, + .probe =3D tps65219_probe, + .id_table =3D tps65219_id_table, + .remove =3D tps65219_remove, +}; + +module_i2c_driver(tps65219_driver); + +MODULE_AUTHOR("Jerome Neanne "); +MODULE_DESCRIPTION("TPS65219 chip family multi-function driver"); +MODULE_LICENSE("GPL"); diff --git a/include/linux/mfd/tps65219.h b/include/linux/mfd/tps65219.h new file mode 100644 index 000000000000..e9197ab8bc75 --- /dev/null +++ b/include/linux/mfd/tps65219.h @@ -0,0 +1,251 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * linux/mfd/tps65219.h + * + * Functions to access TPS65219 power management chip. + * + * Copyright (C) 2022 BayLibre Incorporated - https://www.baylibre.com/ + */ + +#ifndef __LINUX_MFD_TPS65219_H +#define __LINUX_MFD_TPS65219_H + +#include +#include +#include +#include +#include + +#define TPS65219_1V35 1350000 +#define TPS65219_1V8 1800000 + +/* TPS chip id list */ +#define TPS65219 0xF0 + +/* I2C ID for TPS65219 part */ +#define TPS65219_I2C_ID 0x24 + +/* All register addresses */ +#define TPS65219_REG_TI_DEV_ID 0x00 +#define TPS65219_REG_NVM_ID 0x01 +#define TPS65219_REG_ENABLE_CTRL 0x02 +#define TPS65219_REG_BUCKS_CONFIG 0x03 +#define TPS65219_REG_LDO4_VOUT 0x04 +#define TPS65219_REG_LDO3_VOUT 0x05 +#define TPS65219_REG_LDO2_VOUT 0x06 +#define TPS65219_REG_LDO1_VOUT 0x07 +#define TPS65219_REG_BUCK3_VOUT 0x8 +#define TPS65219_REG_BUCK2_VOUT 0x9 +#define TPS65219_REG_BUCK1_VOUT 0xA +#define TPS65219_REG_LDO4_SEQUENCE_SLOT 0xB +#define TPS65219_REG_LDO3_SEQUENCE_SLOT 0xC +#define TPS65219_REG_LDO2_SEQUENCE_SLOT 0xD +#define TPS65219_REG_LDO1_SEQUENCE_SLOT 0xE +#define TPS65219_REG_BUCK3_SEQUENCE_SLOT 0xF +#define TPS65219_REG_BUCK2_SEQUENCE_SLOT 0x10 +#define TPS65219_REG_BUCK1_SEQUENCE_SLOT 0x11 +#define TPS65219_REG_nRST_SEQUENCE_SLOT 0x12 +#define TPS65219_REG_GPIO_SEQUENCE_SLOT 0x13 +#define TPS65219_REG_GPO2_SEQUENCE_SLOT 0x14 +#define TPS65219_REG_GPO1_SEQUENCE_SLOT 0x15 +#define TPS65219_REG_POWER_UP_SLOT_DURATION_1 0x16 +#define TPS65219_REG_POWER_UP_SLOT_DURATION_2 0x17 +#define TPS65219_REG_POWER_UP_SLOT_DURATION_3 0x18 +#define TPS65219_REG_POWER_UP_SLOT_DURATION_4 0x19 +#define TPS65219_REG_POWER_DOWN_SLOT_DURATION_1 0x1A +#define TPS65219_REG_POWER_DOWN_SLOT_DURATION_2 0x1B +#define TPS65219_REG_POWER_DOWN_SLOT_DURATION_3 0x1C +#define TPS65219_REG_POWER_DOWN_SLOT_DURATION_4 0x1D +#define TPS65219_REG_GENERAL_CONFIG 0x1E +#define TPS65219_REG_MFP_1_CONFIG 0x1F +#define TPS65219_REG_MFP_2_CONFIG 0x20 +#define TPS65219_REG_STBY_1_CONFIG 0x21 +#define TPS65219_REG_STBY_2_CONFIG 0x22 +#define TPS65219_REG_OC_DEGL_CONFIG 0x23 +/* 'sub irq' MASK registers */ +#define TPS65219_REG_INT_MASK_UV 0x24 +#define TPS65219_REG_MASK_CONFIG 0x25 + +#define TPS65219_REG_I2C_ADDRESS_REG 0x26 +#define TPS65219_REG_USER_GENERAL_NVM_STORAGE 0x27 +#define TPS65219_REG_MANUFACTURING_VER 0x28 +#define TPS65219_REG_MFP_CTRL 0x29 +#define TPS65219_REG_DISCHARGE_CONFIG 0x2A +/* main irq registers */ +#define TPS65219_REG_INT_SOURCE 0x2B +/* 'sub irq' registers */ +#define TPS65219_REG_INT_LDO_3_4 0x2C +#define TPS65219_REG_INT_LDO_1_2 0x2D +#define TPS65219_REG_INT_BUCK_3 0x2E +#define TPS65219_REG_INT_BUCK_1_2 0x2F +#define TPS65219_REG_INT_SYSTEM 0x30 +#define TPS65219_REG_INT_RV 0x31 +#define TPS65219_REG_INT_TIMEOUT_RV_SD 0x32 +#define TPS65219_REG_INT_PB 0x33 + +#define TPS65219_REG_USER_NVM_CMD 0x34 +#define TPS65219_REG_POWER_UP_STATUS 0x35 +#define TPS65219_REG_SPARE_2 0x36 +#define TPS65219_REG_SPARE_3 0x37 +#define TPS65219_REG_FACTORY_CONFIG_2 0x41 + +/* Register field definitions */ +#define TPS65219_DEVID_REV_MASK GENMASK(7, 0) +#define TPS65219_BUCKS_LDOS_VOUT_VSET_MASK GENMASK(5, 0) +#define TPS65219_BUCKS_UV_THR_SEL_MASK BIT(6) +#define TPS65219_BUCKS_BW_SEL_MASK BIT(7) +#define LDO_BYP_SHIFT 6 +#define TPS65219_LDOS_BYP_CONFIG_MASK BIT(LDO_BYP_SHIFT) +#define TPS65219_LDOS_LSW_CONFIG_MASK BIT(7) +/* Regulators enable control */ +#define TPS65219_ENABLE_BUCK1_EN_MASK BIT(0) +#define TPS65219_ENABLE_BUCK2_EN_MASK BIT(1) +#define TPS65219_ENABLE_BUCK3_EN_MASK BIT(2) +#define TPS65219_ENABLE_LDO1_EN_MASK BIT(3) +#define TPS65219_ENABLE_LDO2_EN_MASK BIT(4) +#define TPS65219_ENABLE_LDO3_EN_MASK BIT(5) +#define TPS65219_ENABLE_LDO4_EN_MASK BIT(6) +/* power ON-OFF sequence slot */ +#define TPS65219_BUCKS_LDOS_SEQUENCE_OFF_SLOT_MASK GENMASK(3, 0) +#define TPS65219_BUCKS_LDOS_SEQUENCE_ON_SLOT_MASK GENMASK(7, 4) +/* TODO: Not needed, same mapping as TPS65219_ENABLE_REGNAME_EN, factorize= */ +#define TPS65219_STBY1_BUCK1_STBY_EN_MASK BIT(0) +#define TPS65219_STBY1_BUCK2_STBY_EN_MASK BIT(1) +#define TPS65219_STBY1_BUCK3_STBY_EN_MASK BIT(2) +#define TPS65219_STBY1_LDO1_STBY_EN_MASK BIT(3) +#define TPS65219_STBY1_LDO2_STBY_EN_MASK BIT(4) +#define TPS65219_STBY1_LDO3_STBY_EN_MASK BIT(5) +#define TPS65219_STBY1_LDO4_STBY_EN_MASK BIT(6) +/* STBY_2 config */ +#define TPS65219_STBY2_GPO1_STBY_EN_MASK BIT(0) +#define TPS65219_STBY2_GPO2_STBY_EN_MASK BIT(1) +#define TPS65219_STBY2_GPIO_STBY_EN_MASK BIT(2) +/* MFP Control */ +#define TPS65219_MFP_I2C_OFF_REQ_MASK BIT(0) +#define TPS65219_MFP_STBY_I2C_CTRL_MASK BIT(1) +#define TPS65219_MFP_COLD_RESET_I2C_CTRL_MASK BIT(2) +#define TPS65219_MFP_WARM_RESET_I2C_CTRL_MASK BIT(3) +#define TPS65219_MFP_GPIO_STATUS_MASK BIT(4) +/* MFP_1 Config */ +#define TPS65219_MFP_1_VSEL_DDR_SEL_MASK BIT(0) +#define TPS65219_MFP_1_VSEL_SD_POL_MASK BIT(1) +#define TPS65219_MFP_1_VSEL_RAIL_MASK BIT(2) +/* MFP_2 Config */ +#define TPS65219_MFP_2_MODE_STBY_MASK GENMASK(1, 0) +#define TPS65219_MFP_2_MODE_RESET_MASK BIT(2) +#define TPS65219_MFP_2_EN_PB_VSENSE_DEGL_MASK BIT(3) +#define TPS65219_MFP_2_EN_PB_VSENSE_MASK GENMASK(5, 4) +#define TPS65219_MFP_2_WARM_COLD_RESET_MASK BIT(6) +#define TPS65219_MFP_2_PU_ON_FSD_MASK BIT(7) +#define TPS65219_MFP_2_EN 0 +#define TPS65219_MFP_2_PB BIT(4) +#define TPS65219_MFP_2_VSENSE BIT(5) +/* MASK_UV Config */ +#define TPS65219_REG_MASK_UV_LDO1_UV_MASK BIT(0) +#define TPS65219_REG_MASK_UV_LDO2_UV_MASK BIT(1) +#define TPS65219_REG_MASK_UV_LDO3_UV_MASK BIT(2) +#define TPS65219_REG_MASK_UV_LDO4_UV_MASK BIT(3) +#define TPS65219_REG_MASK_UV_BUCK1_UV_MASK BIT(4) +#define TPS65219_REG_MASK_UV_BUCK2_UV_MASK BIT(5) +#define TPS65219_REG_MASK_UV_BUCK3_UV_MASK BIT(6) +#define TPS65219_REG_MASK_UV_RETRY_MASK BIT(7) +/* MASK Config */ +// SENSOR_N_WARM_MASK already defined in Thermal +#define TPS65219_REG_MASK_INT_FOR_RV_MASK BIT(4) +#define TPS65219_REG_MASK_EFFECT_MASK GENMASK(2, 1) +#define TPS65219_REG_MASK_INT_FOR_PB_MASK BIT(7) +/* UnderVoltage - Short to GND - OverCurrent*/ +/* LDO3-4 */ +#define TPS65219_INT_LDO3_SCG_MASK BIT(0) +#define TPS65219_INT_LDO3_OC_MASK BIT(1) +#define TPS65219_INT_LDO3_UV_MASK BIT(2) +#define TPS65219_INT_LDO4_SCG_MASK BIT(3) +#define TPS65219_INT_LDO4_OC_MASK BIT(4) +#define TPS65219_INT_LDO4_UV_MASK BIT(5) +/* LDO1-2 */ +#define TPS65219_INT_LDO1_SCG_MASK BIT(0) +#define TPS65219_INT_LDO1_OC_MASK BIT(1) +#define TPS65219_INT_LDO1_UV_MASK BIT(2) +#define TPS65219_INT_LDO2_SCG_MASK BIT(3) +#define TPS65219_INT_LDO2_OC_MASK BIT(4) +#define TPS65219_INT_LDO2_UV_MASK BIT(5) +/* BUCK3 */ +#define TPS65219_INT_BUCK3_SCG_MASK BIT(0) +#define TPS65219_INT_BUCK3_OC_MASK BIT(1) +#define TPS65219_INT_BUCK3_NEG_OC_MASK BIT(2) +#define TPS65219_INT_BUCK3_UV_MASK BIT(3) +/* BUCK1-2 */ +#define TPS65219_INT_BUCK1_SCG_MASK BIT(0) +#define TPS65219_INT_BUCK1_OC_MASK BIT(1) +#define TPS65219_INT_BUCK1_NEG_OC_MASK BIT(2) +#define TPS65219_INT_BUCK1_UV_MASK BIT(3) +#define TPS65219_INT_BUCK2_SCG_MASK BIT(4) +#define TPS65219_INT_BUCK2_OC_MASK BIT(5) +#define TPS65219_INT_BUCK2_NEG_OC_MASK BIT(6) +#define TPS65219_INT_BUCK2_UV_MASK BIT(7) +/* Thermal Sensor */ +#define TPS65219_INT_SENSOR_3_WARM_MASK BIT(0) +#define TPS65219_INT_SENSOR_2_WARM_MASK BIT(1) +#define TPS65219_INT_SENSOR_1_WARM_MASK BIT(2) +#define TPS65219_INT_SENSOR_0_WARM_MASK BIT(3) +#define TPS65219_INT_SENSOR_3_HOT_MASK BIT(4) +#define TPS65219_INT_SENSOR_2_HOT_MASK BIT(5) +#define TPS65219_INT_SENSOR_1_HOT_MASK BIT(6) +#define TPS65219_INT_SENSOR_0_HOT_MASK BIT(7) +/* Residual Voltage */ +#define TPS65219_INT_BUCK1_RV_MASK BIT(0) +#define TPS65219_INT_BUCK2_RV_MASK BIT(1) +#define TPS65219_INT_BUCK3_RV_MASK BIT(2) +#define TPS65219_INT_LDO1_RV_MASK BIT(3) +#define TPS65219_INT_LDO2_RV_MASK BIT(4) +#define TPS65219_INT_LDO3_RV_MASK BIT(5) +#define TPS65219_INT_LDO4_RV_MASK BIT(6) +/* Residual Voltage ShutDown */ +#define TPS65219_INT_BUCK1_RV_SD_MASK BIT(0) +#define TPS65219_INT_BUCK2_RV_SD_MASK BIT(1) +#define TPS65219_INT_BUCK3_RV_SD_MASK BIT(2) +#define TPS65219_INT_LDO1_RV_SD_MASK BIT(3) +#define TPS65219_INT_LDO2_RV_SD_MASK BIT(4) +#define TPS65219_INT_LDO3_RV_SD_MASK BIT(5) +#define TPS65219_INT_LDO4_RV_SD_MASK BIT(6) +#define TPS65219_INT_TIMEOUT_MASK BIT(7) +/* Power Button */ +#define TPS65219_INT_PB_FALLING_EDGE_DET_MASK BIT(0) +#define TPS65219_INT_PB_RISING_EDGE_DET_MASK BIT(1) +#define TPS65219_INT_PB_REAL_TIME_STATUS_MASK BIT(2) + +enum tps65219_regulator_id { + /* DCDC's */ + TPS65219_BUCK_1, + TPS65219_BUCK_2, + TPS65219_BUCK_3, + /* LDOs */ + TPS65219_LDO_1, + TPS65219_LDO_2, + TPS65219_LDO_3, + TPS65219_LDO_4, +}; + +#define TPS65219_MAX_REG_ID TPS65219_LDO_4 + +/* Number of step-down converters available */ +#define TPS65219_NUM_DCDC 3 +/* Number of LDO voltage regulators available */ +#define TPS65219_NUM_LDO 4 +/* Number of total regulators available */ +#define TPS65219_NUM_REGULATOR (TPS65219_NUM_DCDC + TPS65219_NUM_LDO) + +/** + * struct tps65219 - tps65219 sub-driver chip access routines + * + * Device data may be used to access the TPS65219 chip + */ +struct tps65219 { + struct device *dev; + unsigned int id; + struct regulator_desc desc[TPS65219_NUM_REGULATOR]; + struct regmap *regmap; + struct notifier_block nb; +}; + +#endif /* __LINUX_MFD_TPS65219_H */ --=20 2.17.1 From nobody Sat Apr 11 20:58:56 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AF415C25B08 for ; Fri, 5 Aug 2022 12:19:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240835AbiHEMTw (ORCPT ); Fri, 5 Aug 2022 08:19:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56530 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240778AbiHEMTc (ORCPT ); Fri, 5 Aug 2022 08:19:32 -0400 Received: from mail-ed1-x52c.google.com (mail-ed1-x52c.google.com [IPv6:2a00:1450:4864:20::52c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A3AC779EC7 for ; Fri, 5 Aug 2022 05:19:21 -0700 (PDT) Received: by mail-ed1-x52c.google.com with SMTP id w3so3190187edc.2 for ; Fri, 05 Aug 2022 05:19:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc; bh=olXIWZ2Y25qhRcMeiaJUKmc3CzNTJ/CvhLDT0bUM6Tk=; b=BSwVus0dWm79U9A5roivwBm7QiaRYCmWizX0le5B0Sd1KVGQCblHwjnHS/PeGg9Yjm DQlS4NKxMhad/UIwkLW1Tz2XKcl3IU0fzPasln5IjyzTLdOMtpE0LI0dfbM972Ira4D/ Sjfn8fG/GMNrVVOuoCfCkk8Y2rRrlgQpMfOENZC0SSI8i6ltv1uY9+5+f14VVwI/bA2z zTCKauca6I2ganN6blfF63T7hRJig3sKMS1i23OiCTLpsfg+pCbbnsIM8xeNGygYe3gn krd4MOU1ecNwRt+qKANnuq7z8zuao2XoGxEm4HkWFU/DlEqt4FPafx7hfVfEiuspTjfj OFtg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc; bh=olXIWZ2Y25qhRcMeiaJUKmc3CzNTJ/CvhLDT0bUM6Tk=; b=f83Q7RO61bf8u5ZuPufQHZkSrXmITQ4sjYwmV219i+4VwfV71MBW4Q4P0Ck4M0RRxP 8dGxu0DUb5rkdkVHao+gdJcS0xxsYishurSRh0gJ9Jl2IRJnewZQuwWTRm3O5iK4EnvJ Ev3+UQO0s2gW5npTm18mdNCSvTJa34kgqaW6bjX+wIKXKhklg0n2BLuhZNwb9X9JapyD n2OPDzrfhFX6dfKn6q2DCD7kur4SpS7EMcsZjpsICbUI85LDkS5XT3+xrEAT9eLXYb1C slKzxj+ECgTppWZ6glJUgaZ3oLJeydAfDtr+SPTz7HrlcLXbg/poIYsWIjcFZRqPIVpl LSoQ== X-Gm-Message-State: ACgBeo3PU39PYOrN/r6JaBNo6mfEUxb90eIegCqIStt7iOLEaunRJVnU saBuyyEmReDg8YQv8ixYRVVllA== X-Google-Smtp-Source: AA6agR64VAXOnRyarX3ip4fifFQN8qOEDBxTDaMFRjkCdxoQjyjAiKcEznFJAGXeanbu1t3U9pWKYg== X-Received: by 2002:a05:6402:280f:b0:43d:f946:a895 with SMTP id h15-20020a056402280f00b0043df946a895mr6511722ede.229.1659701960946; Fri, 05 Aug 2022 05:19:20 -0700 (PDT) Received: from localhost.localdomain (2a02-8440-5241-be09-b892-f882-607f-7a79.rev.sfr.net. [2a02:8440:5241:be09:b892:f882:607f:7a79]) by smtp.gmail.com with ESMTPSA id kx13-20020a170907774d00b0072b3464c043sm1506111ejc.116.2022.08.05.05.19.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Aug 2022 05:19:20 -0700 (PDT) From: Jerome Neanne To: lgirdwood@gmail.com, broonie@kernel.org, robh+dt@kernel.org, nm@ti.com, kristo@kernel.org, dmitry.torokhov@gmail.com Cc: khilman@baylibre.com, narmstrong@baylibre.com, msp@baylibre.com, j-keerthy@ti.com, lee.jones@linaro.org, jneanne@baylibre.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-input@vger.kernel.org Subject: [PATCH v3 06/10] mfd: drivers: Add interrupts support to TI TPS65219 PMIC Date: Fri, 5 Aug 2022 14:18:48 +0200 Message-Id: <20220805121852.21254-7-jneanne@baylibre.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220805121852.21254-1-jneanne@baylibre.com> References: <20220805121852.21254-1-jneanne@baylibre.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add TPS65219 support for interrupts through regmap_irq_chip Signed-off-by: Jerome Neanne --- drivers/mfd/tps65219.c | 217 ++++++++++++++++++++++++++++++++++- include/linux/mfd/tps65219.h | 113 ++++++++++++++++++ 2 files changed, 328 insertions(+), 2 deletions(-) diff --git a/drivers/mfd/tps65219.c b/drivers/mfd/tps65219.c index c3bf975ea6c7..7366f251c21d 100644 --- a/drivers/mfd/tps65219.c +++ b/drivers/mfd/tps65219.c @@ -107,8 +107,73 @@ static void pmic_do_poweroff(void) tps65219_soft_shutdown(tps); } =20 -static const struct mfd_cell tps65219_cells[] =3D { - { .name =3D "tps65219-regulator", }, +static const struct resource tps65219_pwrbutton_resources[] =3D { + DEFINE_RES_IRQ_NAMED(TPS65219_INT_PB_FALLING_EDGE_DETECT, "falling"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_PB_RISING_EDGE_DETECT, "rising"), +}; + +static const struct resource tps65219_regulator_resources[] =3D { + DEFINE_RES_IRQ_NAMED(TPS65219_INT_LDO3_SCG, "LDO3_SCG"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_LDO3_OC, "LDO3_OC"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_LDO3_UV, "LDO3_UV"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_LDO4_SCG, "LDO4_SCG"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_LDO4_OC, "LDO4_OC"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_LDO4_UV, "LDO4_UV"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_LDO1_SCG, "LDO1_SCG"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_LDO1_OC, "LDO1_OC"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_LDO1_UV, "LDO1_UV"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_LDO2_SCG, "LDO2_SCG"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_LDO2_OC, "LDO2_OC"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_LDO2_UV, "LDO2_UV"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK3_SCG, "BUCK3_SCG"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK3_OC, "BUCK3_OC"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK3_NEG_OC, "BUCK3_NEG_OC"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK3_UV, "BUCK3_UV"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK1_SCG, "BUCK1_SCG"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK1_OC, "BUCK1_OC"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK1_NEG_OC, "BUCK1_NEG_OC"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK1_UV, "BUCK1_UV"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK2_SCG, "BUCK2_SCG"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK2_OC, "BUCK2_OC"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK2_NEG_OC, "BUCK2_NEG_OC"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK2_UV, "BUCK2_UV"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK1_RV, "BUCK1_RV"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK2_RV, "BUCK2_RV"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK3_RV, "BUCK3_RV"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_LDO1_RV, "LDO1_RV"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_LDO2_RV, "LDO2_RV"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_LDO3_RV, "LDO3_RV"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_LDO4_RV, "LDO4_RV"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK1_RV_SD, "BUCK1_RV_SD"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK2_RV_SD, "BUCK2_RV_SD"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK3_RV_SD, "BUCK3_RV_SD"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_LDO1_RV_SD, "LDO1_RV_SD"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_LDO2_RV_SD, "LDO2_RV_SD"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_LDO3_RV_SD, "LDO3_RV_SD"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_LDO4_RV_SD, "LDO4_RV_SD"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_TIMEOUT, "TIMEOUT"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_SENSOR_3_WARM, "SENSOR_3_WARM"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_SENSOR_2_WARM, "SENSOR_2_WARM"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_SENSOR_1_WARM, "SENSOR_1_WARM"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_SENSOR_0_WARM, "SENSOR_0_WARM"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_SENSOR_3_HOT, "SENSOR_3_HOT"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_SENSOR_2_HOT, "SENSOR_2_HOT"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_SENSOR_1_HOT, "SENSOR_1_HOT"), + DEFINE_RES_IRQ_NAMED(TPS65219_INT_SENSOR_0_HOT, "SENSOR_0_HOT"), +}; + +#define TPS65219_MAX_CELLS 2 + +static const struct mfd_cell tps65219_regulator_cell =3D { + .name =3D "tps65219-regulator", + .resources =3D tps65219_regulator_resources, + .num_resources =3D ARRAY_SIZE(tps65219_regulator_resources), +}; + +static const struct mfd_cell tps65219_pwrbutton_cell =3D { + .name =3D "tps65219-pwrbutton", + .resources =3D tps65219_pwrbutton_resources, + .num_resources =3D ARRAY_SIZE(tps65219_pwrbutton_resources), }; =20 static const struct regmap_config tps65219_regmap_config =3D { @@ -117,6 +182,147 @@ static const struct regmap_config tps65219_regmap_con= fig =3D { .max_register =3D TPS65219_REG_FACTORY_CONFIG_2, }; =20 +/* + * Mapping of main IRQ register bits to sub-IRQ register offsets so that w= e can + * access corect sub-IRQ registers based on bits that are set in main IRQ + * register. + */ +/* Timeout Residual Voltage Shutdown */ +static unsigned int bit0_offsets[] =3D {TPS65219_TO_RV_POS}; +static unsigned int bit1_offsets[] =3D {TPS65219_RV_POS}; /* Residual Volt= age */ +static unsigned int bit2_offsets[] =3D {TPS65219_SYS_POS}; /* System */ +static unsigned int bit3_offsets[] =3D {TPS65219_BUCK_1_2_POS}; /* Buck 1-= 2 */ +static unsigned int bit4_offsets[] =3D {TPS65219_BUCK_3_POS}; /* Buck 3 */ +static unsigned int bit5_offsets[] =3D {TPS65219_LDO_1_2_POS}; /* LDO 1-2 = */ +static unsigned int bit6_offsets[] =3D {TPS65219_LDO_3_4_POS}; /* LDO 3-4 = */ +static unsigned int bit7_offsets[] =3D {TPS65219_PB_POS}; /* Power Button = */ + +static struct regmap_irq_sub_irq_map tps65219_sub_irq_offsets[] =3D { + REGMAP_IRQ_MAIN_REG_OFFSET(bit0_offsets), + REGMAP_IRQ_MAIN_REG_OFFSET(bit1_offsets), + REGMAP_IRQ_MAIN_REG_OFFSET(bit2_offsets), + REGMAP_IRQ_MAIN_REG_OFFSET(bit3_offsets), + REGMAP_IRQ_MAIN_REG_OFFSET(bit4_offsets), + REGMAP_IRQ_MAIN_REG_OFFSET(bit5_offsets), + REGMAP_IRQ_MAIN_REG_OFFSET(bit6_offsets), + REGMAP_IRQ_MAIN_REG_OFFSET(bit7_offsets), +}; + +static struct regmap_irq tps65219_irqs[] =3D { + REGMAP_IRQ_REG(TPS65219_INT_LDO3_SCG, TPS65219_LDO_3_4_POS, + TPS65219_INT_LDO3_SCG_MASK), + REGMAP_IRQ_REG(TPS65219_INT_LDO3_OC, + TPS65219_LDO_3_4_POS, TPS65219_INT_LDO3_OC_MASK), + REGMAP_IRQ_REG(TPS65219_INT_LDO3_UV, TPS65219_LDO_3_4_POS, + TPS65219_INT_LDO3_UV_MASK), + REGMAP_IRQ_REG(TPS65219_INT_LDO4_SCG, TPS65219_LDO_3_4_POS, + TPS65219_INT_LDO4_SCG_MASK), + REGMAP_IRQ_REG(TPS65219_INT_LDO4_OC, TPS65219_LDO_3_4_POS, + TPS65219_INT_LDO4_OC_MASK), + REGMAP_IRQ_REG(TPS65219_INT_LDO4_UV, TPS65219_LDO_3_4_POS, + TPS65219_INT_LDO4_UV_MASK), + REGMAP_IRQ_REG(TPS65219_INT_LDO1_SCG, + TPS65219_LDO_1_2_POS, TPS65219_INT_LDO1_SCG_MASK), + REGMAP_IRQ_REG(TPS65219_INT_LDO1_OC, TPS65219_LDO_1_2_POS, + TPS65219_INT_LDO1_OC_MASK), + REGMAP_IRQ_REG(TPS65219_INT_LDO1_UV, TPS65219_LDO_1_2_POS, + TPS65219_INT_LDO1_UV_MASK), + REGMAP_IRQ_REG(TPS65219_INT_LDO2_SCG, TPS65219_LDO_1_2_POS, + TPS65219_INT_LDO2_SCG_MASK), + REGMAP_IRQ_REG(TPS65219_INT_LDO2_OC, TPS65219_LDO_1_2_POS, + TPS65219_INT_LDO2_OC_MASK), + REGMAP_IRQ_REG(TPS65219_INT_LDO2_UV, TPS65219_LDO_1_2_POS, + TPS65219_INT_LDO2_UV_MASK), + REGMAP_IRQ_REG(TPS65219_INT_BUCK3_SCG, TPS65219_BUCK_3_POS, + TPS65219_INT_BUCK3_SCG_MASK), + REGMAP_IRQ_REG(TPS65219_INT_BUCK3_OC, TPS65219_BUCK_3_POS, + TPS65219_INT_BUCK3_OC_MASK), + REGMAP_IRQ_REG(TPS65219_INT_BUCK3_NEG_OC, TPS65219_BUCK_3_POS, + TPS65219_INT_BUCK3_NEG_OC_MASK), + REGMAP_IRQ_REG(TPS65219_INT_BUCK3_UV, TPS65219_BUCK_3_POS, + TPS65219_INT_BUCK3_UV_MASK), + REGMAP_IRQ_REG(TPS65219_INT_BUCK2_SCG, TPS65219_BUCK_1_2_POS, + TPS65219_INT_BUCK2_SCG_MASK), + REGMAP_IRQ_REG(TPS65219_INT_BUCK2_OC, TPS65219_BUCK_1_2_POS, + TPS65219_INT_BUCK2_OC_MASK), + REGMAP_IRQ_REG(TPS65219_INT_BUCK2_NEG_OC, TPS65219_BUCK_1_2_POS, + TPS65219_INT_BUCK2_NEG_OC_MASK), + REGMAP_IRQ_REG(TPS65219_INT_BUCK2_UV, TPS65219_BUCK_1_2_POS, + TPS65219_INT_BUCK2_UV_MASK), + REGMAP_IRQ_REG(TPS65219_INT_BUCK1_SCG, TPS65219_BUCK_1_2_POS, + TPS65219_INT_BUCK1_SCG_MASK), + REGMAP_IRQ_REG(TPS65219_INT_BUCK1_OC, TPS65219_BUCK_1_2_POS, + TPS65219_INT_BUCK1_OC_MASK), + REGMAP_IRQ_REG(TPS65219_INT_BUCK1_NEG_OC, TPS65219_BUCK_1_2_POS, + TPS65219_INT_BUCK1_NEG_OC_MASK), + REGMAP_IRQ_REG(TPS65219_INT_BUCK1_UV, TPS65219_BUCK_1_2_POS, + TPS65219_INT_BUCK1_UV_MASK), + REGMAP_IRQ_REG(TPS65219_INT_SENSOR_3_WARM, + TPS65219_SYS_POS, TPS65219_INT_SENSOR_3_WARM_MASK), + REGMAP_IRQ_REG(TPS65219_INT_SENSOR_2_WARM, TPS65219_SYS_POS, + TPS65219_INT_SENSOR_2_WARM_MASK), + REGMAP_IRQ_REG(TPS65219_INT_SENSOR_1_WARM, TPS65219_SYS_POS, + TPS65219_INT_SENSOR_1_WARM_MASK), + REGMAP_IRQ_REG(TPS65219_INT_SENSOR_0_WARM, TPS65219_SYS_POS, + TPS65219_INT_SENSOR_0_WARM_MASK), + REGMAP_IRQ_REG(TPS65219_INT_SENSOR_3_HOT, TPS65219_SYS_POS, + TPS65219_INT_SENSOR_3_HOT_MASK), + REGMAP_IRQ_REG(TPS65219_INT_SENSOR_2_HOT, TPS65219_SYS_POS, + TPS65219_INT_SENSOR_2_HOT_MASK), + REGMAP_IRQ_REG(TPS65219_INT_SENSOR_1_HOT, TPS65219_SYS_POS, + TPS65219_INT_SENSOR_1_HOT_MASK), + REGMAP_IRQ_REG(TPS65219_INT_SENSOR_0_HOT, TPS65219_SYS_POS, + TPS65219_INT_SENSOR_0_HOT_MASK), + REGMAP_IRQ_REG(TPS65219_INT_BUCK1_RV, TPS65219_RV_POS, + TPS65219_INT_BUCK1_RV_MASK), + REGMAP_IRQ_REG(TPS65219_INT_BUCK2_RV, TPS65219_RV_POS, + TPS65219_INT_BUCK2_RV_MASK), + REGMAP_IRQ_REG(TPS65219_INT_BUCK3_RV, TPS65219_RV_POS, + TPS65219_INT_BUCK3_RV_MASK), + REGMAP_IRQ_REG(TPS65219_INT_LDO1_RV, TPS65219_RV_POS, + TPS65219_INT_LDO1_RV_MASK), + REGMAP_IRQ_REG(TPS65219_INT_LDO2_RV, TPS65219_RV_POS, + TPS65219_INT_LDO2_RV_MASK), + REGMAP_IRQ_REG(TPS65219_INT_LDO3_RV, TPS65219_RV_POS, + TPS65219_INT_LDO3_RV_MASK), + REGMAP_IRQ_REG(TPS65219_INT_LDO4_RV, TPS65219_RV_POS, + TPS65219_INT_LDO4_RV_MASK), + REGMAP_IRQ_REG(TPS65219_INT_BUCK1_RV_SD, + TPS65219_TO_RV_POS, TPS65219_INT_BUCK1_RV_SD_MASK), + REGMAP_IRQ_REG(TPS65219_INT_BUCK2_RV_SD, + TPS65219_TO_RV_POS, TPS65219_INT_BUCK2_RV_SD_MASK), + REGMAP_IRQ_REG(TPS65219_INT_BUCK3_RV_SD, TPS65219_TO_RV_POS, + TPS65219_INT_BUCK3_RV_SD_MASK), + REGMAP_IRQ_REG(TPS65219_INT_LDO1_RV_SD, TPS65219_TO_RV_POS, + TPS65219_INT_LDO1_RV_SD_MASK), + REGMAP_IRQ_REG(TPS65219_INT_LDO2_RV_SD, TPS65219_TO_RV_POS, + TPS65219_INT_LDO2_RV_SD_MASK), + REGMAP_IRQ_REG(TPS65219_INT_LDO3_RV_SD, + TPS65219_TO_RV_POS, TPS65219_INT_LDO3_RV_SD_MASK), + REGMAP_IRQ_REG(TPS65219_INT_LDO4_RV_SD, TPS65219_TO_RV_POS, + TPS65219_INT_LDO4_RV_SD_MASK), + REGMAP_IRQ_REG(TPS65219_INT_TIMEOUT, TPS65219_TO_RV_POS, + TPS65219_INT_TIMEOUT_MASK), + REGMAP_IRQ_REG(TPS65219_INT_PB_FALLING_EDGE_DETECT, + TPS65219_PB_POS, TPS65219_INT_PB_FALLING_EDGE_DET_MASK), + REGMAP_IRQ_REG(TPS65219_INT_PB_RISING_EDGE_DETECT, TPS65219_PB_POS, + TPS65219_INT_PB_RISING_EDGE_DET_MASK), +}; + +static struct regmap_irq_chip tps65219_irq_chip =3D { + .name =3D "tps65219_irq", + .main_status =3D TPS65219_REG_INT_SOURCE, + .num_main_regs =3D 1, + .num_main_status_bits =3D 8, + .irqs =3D tps65219_irqs, + .num_irqs =3D ARRAY_SIZE(tps65219_irqs), + .status_base =3D TPS65219_REG_INT_LDO_3_4, + .ack_base =3D TPS65219_REG_INT_LDO_3_4, + .clear_ack =3D 1, + .num_regs =3D 8, + .sub_reg_offsets =3D &tps65219_sub_irq_offsets[0], +}; + static const struct of_device_id of_tps65219_match_table[] =3D { { .compatible =3D "ti,tps65219", }, {} @@ -137,6 +343,7 @@ static int tps65219_probe(struct i2c_client *client, =20 i2c_set_clientdata(client, tps); tps->dev =3D &client->dev; + tps->irq =3D client->irq; tps->regmap =3D devm_regmap_init_i2c(client, &tps65219_regmap_config); if (IS_ERR(tps->regmap)) { ret =3D PTR_ERR(tps->regmap); @@ -145,6 +352,12 @@ static int tps65219_probe(struct i2c_client *client, return ret; } =20 + ret =3D devm_regmap_add_irq_chip(&client->dev, tps->regmap, tps->irq, + IRQF_ONESHOT, 0, &tps65219_irq_chip, + &tps->irq_data); + if (ret) + return ret; + ret =3D regmap_read(tps->regmap, TPS65219_REG_TI_DEV_ID, &chipid); if (ret) { dev_err(tps->dev, "Failed to read device ID: %d\n", ret); diff --git a/include/linux/mfd/tps65219.h b/include/linux/mfd/tps65219.h index e9197ab8bc75..8cecaf9bc682 100644 --- a/include/linux/mfd/tps65219.h +++ b/include/linux/mfd/tps65219.h @@ -214,6 +214,104 @@ #define TPS65219_INT_PB_RISING_EDGE_DET_MASK BIT(1) #define TPS65219_INT_PB_REAL_TIME_STATUS_MASK BIT(2) =20 +/* Masks for main IRQ register bits */ +enum { + TPS65219_INT_TIMEOUT_RV_SD, +#define TPS65219_INT_TIMEOUT_RV_SD_MASK BIT(TPS65219_INT_TIMEOUT_RV_SD) + TPS65219_INT_RV, +#define TPS65219_INT_RV_MASK BIT(TPS65219_INT_RV) + TPS65219_INT_SYSTEM, +#define TPS65219_INT_SYSTEM_MASK BIT(TPS65219_INT_SYSTEM) + TPS65219_INT_BUCK_1_2, +#define TPS65219_INT_BUCK_1_2_MASK BIT(TPS65219_INT_BUCK_1_2) + TPS65219_INT_BUCK_3, +#define TPS65219_INT_BUCK_3_MASK BIT(TPS65219_INT_BUCK_3) + TPS65219_INT_LDO_1_2, +#define TPS65219_INT_LDO_1_2_MASK BIT(TPS65219_INT_LDO_1_2) + TPS65219_INT_LDO_3_4, +#define TPS65219_INT_LDO_3_4_MASK BIT(TPS65219_LDO_3_4) + TPS65219_INT_PB, +#define TPS65219_INT_PB_MASK BIT(TPS65219_INT_PB) +}; + +/* Timeout Residual Voltage Shutdown */ +#define TPS65219_TO_RV_POS 6 +/* Residual Voltage */ +#define TPS65219_RV_POS 5 +/* System */ +#define TPS65219_SYS_POS 4 +/* Buck 1-2 */ +#define TPS65219_BUCK_1_2_POS 3 +/* Buck 3 */ +#define TPS65219_BUCK_3_POS 2 +/* LDO 1-2 */ +#define TPS65219_LDO_1_2_POS 1 +/* LDO 3-4 */ +#define TPS65219_LDO_3_4_POS 0 +/* Power Button */ +#define TPS65219_PB_POS 7 + +/* IRQs */ +enum { + /* LDO3-4 register IRQs */ + TPS65219_INT_LDO3_SCG, + TPS65219_INT_LDO3_OC, + TPS65219_INT_LDO3_UV, + TPS65219_INT_LDO4_SCG, + TPS65219_INT_LDO4_OC, + TPS65219_INT_LDO4_UV, + /* LDO1-2 */ + TPS65219_INT_LDO1_SCG, + TPS65219_INT_LDO1_OC, + TPS65219_INT_LDO1_UV, + TPS65219_INT_LDO2_SCG, + TPS65219_INT_LDO2_OC, + TPS65219_INT_LDO2_UV, + /* BUCK3 */ + TPS65219_INT_BUCK3_SCG, + TPS65219_INT_BUCK3_OC, + TPS65219_INT_BUCK3_NEG_OC, + TPS65219_INT_BUCK3_UV, + /* BUCK1-2 */ + TPS65219_INT_BUCK1_SCG, + TPS65219_INT_BUCK1_OC, + TPS65219_INT_BUCK1_NEG_OC, + TPS65219_INT_BUCK1_UV, + TPS65219_INT_BUCK2_SCG, + TPS65219_INT_BUCK2_OC, + TPS65219_INT_BUCK2_NEG_OC, + TPS65219_INT_BUCK2_UV, + /* Thermal Sensor */ + TPS65219_INT_SENSOR_3_WARM, + TPS65219_INT_SENSOR_2_WARM, + TPS65219_INT_SENSOR_1_WARM, + TPS65219_INT_SENSOR_0_WARM, + TPS65219_INT_SENSOR_3_HOT, + TPS65219_INT_SENSOR_2_HOT, + TPS65219_INT_SENSOR_1_HOT, + TPS65219_INT_SENSOR_0_HOT, + /* Residual Voltage */ + TPS65219_INT_BUCK1_RV, + TPS65219_INT_BUCK2_RV, + TPS65219_INT_BUCK3_RV, + TPS65219_INT_LDO1_RV, + TPS65219_INT_LDO2_RV, + TPS65219_INT_LDO3_RV, + TPS65219_INT_LDO4_RV, + /* Residual Voltage ShutDown */ + TPS65219_INT_BUCK1_RV_SD, + TPS65219_INT_BUCK2_RV_SD, + TPS65219_INT_BUCK3_RV_SD, + TPS65219_INT_LDO1_RV_SD, + TPS65219_INT_LDO2_RV_SD, + TPS65219_INT_LDO3_RV_SD, + TPS65219_INT_LDO4_RV_SD, + TPS65219_INT_TIMEOUT, + /* Power Button */ + TPS65219_INT_PB_FALLING_EDGE_DETECT, + TPS65219_INT_PB_RISING_EDGE_DETECT, +}; + enum tps65219_regulator_id { /* DCDC's */ TPS65219_BUCK_1, @@ -235,6 +333,19 @@ enum tps65219_regulator_id { /* Number of total regulators available */ #define TPS65219_NUM_REGULATOR (TPS65219_NUM_DCDC + TPS65219_NUM_LDO) =20 +/* Define the TPS65219 IRQ numbers */ +enum tps65219_irqs { + /* INT source registers */ + TPS65219_TO_RV_SD_SET_IRQ, + TPS65219_RV_SET_IRQ, + TPS65219_SYS_SET_IRQ, + TPS65219_BUCK_1_2_SET_IRQ, + TPS65219_BUCK_3_SET_IRQ, + TPS65219_LDO_1_2_SET_IRQ, + TPS65219_LDO_3_4_SET_IRQ, + TPS65219_PB_SET_IRQ, +}; + /** * struct tps65219 - tps65219 sub-driver chip access routines * @@ -243,6 +354,8 @@ enum tps65219_regulator_id { struct tps65219 { struct device *dev; unsigned int id; + int irq; + struct regmap_irq_chip_data *irq_data; struct regulator_desc desc[TPS65219_NUM_REGULATOR]; struct regmap *regmap; struct notifier_block nb; --=20 2.17.1 From nobody Sat Apr 11 20:58:56 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AD64CC25B06 for ; Fri, 5 Aug 2022 12:20:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240847AbiHEMUE (ORCPT ); Fri, 5 Aug 2022 08:20:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56802 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240769AbiHEMTr (ORCPT ); Fri, 5 Aug 2022 08:19:47 -0400 Received: from mail-ej1-x629.google.com (mail-ej1-x629.google.com [IPv6:2a00:1450:4864:20::629]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F038B79EC2 for ; Fri, 5 Aug 2022 05:19:26 -0700 (PDT) Received: by mail-ej1-x629.google.com with SMTP id w19so4712301ejc.7 for ; Fri, 05 Aug 2022 05:19:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc; bh=GNrNSsuONOTD44Y0Q9blvBNHRmEVk0mvY3do2mRmKgc=; b=a/uwkzGq+yuyHz2sS/aR9ewxi1sK5Wl/RrWwOe2SHCSDZDeHIUVIigGwsT5fxHtfsM c6suea9o/UsFOv0zshyrM0VPNdTEDFMlz20l5jPAn3kfhRH7yK0DHopw80D2qXf7FjXu krVOdFjUMKtT7KlqDvdQANEeio6Zik0jH/Tex6/7Nkc4jfrgN9wxUKX2PGckbqNcnddP 2Pi3Wp5NhmjvlzFlQbbQVLhzHOhePnWd9CLKHxDwacL2VHm2TSY+M67L7gARkNA+zTRb ERbzLbUv6Tmn6eawW5f8Z3LV1Sznd/r9n02OKZSDCiTn6ItsbRlnRcILVo1sbSM5Z3aW kGZw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc; bh=GNrNSsuONOTD44Y0Q9blvBNHRmEVk0mvY3do2mRmKgc=; b=IL1iNvvj4gijE8WQS1EjoVvjsG0j+OUa4P1OVEmmhvBpjDkGiPx74c8GZeBVic9RT8 oOHt+mEFEQOed3vZBj4s0LHL3/2V5p03yM3hytSlklNqLyfnk+k3YwEnvd92Fnu8QP2h mQJdrtxoUCmvv2gWbwHMzJtZUf78EWpZ+kjIGNtXuWnhTixZolO9BB0a7ovx4+lsOM+j 7BURwZMzo3+JZ/Zo5cMJZFEYmOe+4+3QMa1p7bK+ALZOLmW0kNc2GhVl93WNsAqyjwE4 n3ZS03BeIMs1vLSwF60AURvFc9cHzyGxrpkwlNoHLBaqySTV5mm3iip/3p3+1rTMkpnh NbRA== X-Gm-Message-State: ACgBeo328VyPbvjUcHu18jcaXBXw17JxPQ9mrGxLdGfRqHoGkpWaQwxP +PhbqZ7CnTHrlWpPI5lZZn2Ut8yFCq0Txw== X-Google-Smtp-Source: AA6agR5FIsO97DLM2JgDp/V+GxyepC/MnM+cAzEQ8k4pSTXMQo1WAiwolVztjtJBjgkOEwXs7rFNKg== X-Received: by 2002:a17:907:9710:b0:72b:3271:c9f with SMTP id jg16-20020a170907971000b0072b32710c9fmr4906092ejc.91.1659701966427; Fri, 05 Aug 2022 05:19:26 -0700 (PDT) Received: from localhost.localdomain (2a02-8440-5241-be09-b892-f882-607f-7a79.rev.sfr.net. [2a02:8440:5241:be09:b892:f882:607f:7a79]) by smtp.gmail.com with ESMTPSA id kx13-20020a170907774d00b0072b3464c043sm1506111ejc.116.2022.08.05.05.19.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Aug 2022 05:19:26 -0700 (PDT) From: Jerome Neanne To: lgirdwood@gmail.com, broonie@kernel.org, robh+dt@kernel.org, nm@ti.com, kristo@kernel.org, dmitry.torokhov@gmail.com Cc: khilman@baylibre.com, narmstrong@baylibre.com, msp@baylibre.com, j-keerthy@ti.com, lee.jones@linaro.org, jneanne@baylibre.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-input@vger.kernel.org Subject: [PATCH v3 07/10] mfd: tps65219: Add power-button support Date: Fri, 5 Aug 2022 14:18:49 +0200 Message-Id: <20220805121852.21254-8-jneanne@baylibre.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220805121852.21254-1-jneanne@baylibre.com> References: <20220805121852.21254-1-jneanne@baylibre.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Markus Schneider-Pargmann Using a power-button on the EN/PB/VSENSE pin of TPS65219 is optional, so this driver adds the mfd cell for tps65219-pwrbutton only if needed. Two interrupts are passed to the driver. Signed-off-by: Markus Schneider-Pargmann Signed-off-by: Jerome Neanne --- drivers/mfd/tps65219.c | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/drivers/mfd/tps65219.c b/drivers/mfd/tps65219.c index 7366f251c21d..c2136662627c 100644 --- a/drivers/mfd/tps65219.c +++ b/drivers/mfd/tps65219.c @@ -335,7 +335,10 @@ static int tps65219_probe(struct i2c_client *client, struct tps65219 *tps; int ret; unsigned int chipid; + bool pwr_button; bool sys_pwr; + struct mfd_cell cells[TPS65219_MAX_CELLS]; + int nr_cells =3D 0; =20 tps =3D devm_kzalloc(&client->dev, sizeof(*tps), GFP_KERNEL); if (!tps) @@ -364,9 +367,16 @@ static int tps65219_probe(struct i2c_client *client, return ret; } =20 - ret =3D devm_mfd_add_devices(tps->dev, PLATFORM_DEVID_AUTO, tps65219_cell= s, - ARRAY_SIZE(tps65219_cells), NULL, 0, - NULL); + memcpy(&cells[nr_cells++], &tps65219_regulator_cell, + sizeof(tps65219_regulator_cell)); + pwr_button =3D of_property_read_bool(tps->dev->of_node, "ti,power-button"= ); + if (pwr_button) + memcpy(&cells[nr_cells++], &tps65219_pwrbutton_cell, + sizeof(tps65219_pwrbutton_cell)); + + ret =3D devm_mfd_add_devices(tps->dev, PLATFORM_DEVID_AUTO, cells, + nr_cells, NULL, 0, + regmap_irq_get_domain(tps->irq_data)); if (ret) { dev_err(tps->dev, "mfd_add_devices failed: %d\n", ret); return ret; --=20 2.17.1 From nobody Sat Apr 11 20:58:56 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5A3C9C00140 for ; Fri, 5 Aug 2022 12:20:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240746AbiHEMUS (ORCPT ); Fri, 5 Aug 2022 08:20:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56878 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240832AbiHEMTw (ORCPT ); Fri, 5 Aug 2022 08:19:52 -0400 Received: from mail-ed1-x52b.google.com (mail-ed1-x52b.google.com [IPv6:2a00:1450:4864:20::52b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0D2867969C for ; Fri, 5 Aug 2022 05:19:33 -0700 (PDT) Received: by mail-ed1-x52b.google.com with SMTP id b96so3249459edf.0 for ; Fri, 05 Aug 2022 05:19:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc; bh=syRgqvLlRIW5BUXBXSYKcB6w+IB0NOavd0Y5qbVcTcE=; b=z3CY2ja5H4IWuYuPSmHcXu2YdiNtBnUnztsQxjyc2c16TuZfZJFWpOyFu5WAoetS76 fnc6kn0rCJxsmI4/KgDQHA9GaN0ndkd1LfXV3hjlSwWEj4dbVBcipjqtAwh9JS9NJb/m jjw6SdkZFg5eI5LzuJwT704txvIpXMX7lx+iCFmeSD5TXyQxnxBklgxa4OJelwiXBZKX fX21VTr6pGLV1jDq2Vn/47295ja9thO8/Mc/CKJzJzVmM6b3GJiBhiZUXiz9uLeXbxqG U+uj4RXPgvAAe5JH/7XysLRWVR0BELSfDpHVZhE9q1Au7yQh9623sxdbNG1QJjijoJX/ W36w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc; bh=syRgqvLlRIW5BUXBXSYKcB6w+IB0NOavd0Y5qbVcTcE=; b=iJr80WispItbdWu/UAO61lU9vQLQMTxpm6SYb/HdnUqVZf0FRKZ6v3O9GmMchTQ9JO 90WDvNIEx11Dxg0wWhZhSijN8UMq+E8t+gJ3ppCUY6LbIeWFR7rvzhB1Xo8AbCWurBQc WbBswHBHyc2mo1E1v/MnP0XL2ZkYsINziRhuIrQZOAP74lt36mVDYgInRts8GhgU4z6e mt0+1ZcIO1wgCTdHzG386P+KGtEGudXl++swPAkc71vwsxRPvO/FizP0HkRzLnrAKefB nBuGzeXO5wzX0TJ/GmxXZBje3Ml8PYhfveapy63fROY/+CU5aZJJdIl/+Dgw4+8a7658 xkfQ== X-Gm-Message-State: ACgBeo3DjB8f0C5Ikw1Spm765eVmqXiMTSuZc+wnGDCjalJPzajRsett HbuNqTKmpyukp6/MT9vVoPCOBg== X-Google-Smtp-Source: AA6agR7VPA/mE/lrNexdRwlmsrXo7oohV5DpHPwWaGlIUV0U5lEiW0rXDw0h6AkCjA+6h1Pdyu0rSw== X-Received: by 2002:aa7:ccc4:0:b0:43d:9e0e:b7ff with SMTP id y4-20020aa7ccc4000000b0043d9e0eb7ffmr6552038edt.14.1659701971445; Fri, 05 Aug 2022 05:19:31 -0700 (PDT) Received: from localhost.localdomain (2a02-8440-5241-be09-b892-f882-607f-7a79.rev.sfr.net. [2a02:8440:5241:be09:b892:f882:607f:7a79]) by smtp.gmail.com with ESMTPSA id kx13-20020a170907774d00b0072b3464c043sm1506111ejc.116.2022.08.05.05.19.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Aug 2022 05:19:30 -0700 (PDT) From: Jerome Neanne To: lgirdwood@gmail.com, broonie@kernel.org, robh+dt@kernel.org, nm@ti.com, kristo@kernel.org, dmitry.torokhov@gmail.com Cc: khilman@baylibre.com, narmstrong@baylibre.com, msp@baylibre.com, j-keerthy@ti.com, lee.jones@linaro.org, jneanne@baylibre.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-input@vger.kernel.org Subject: [PATCH v3 08/10] regulator: drivers: Add TI TPS65219 PMIC regulators support Date: Fri, 5 Aug 2022 14:18:50 +0200 Message-Id: <20220805121852.21254-9-jneanne@baylibre.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220805121852.21254-1-jneanne@baylibre.com> References: <20220805121852.21254-1-jneanne@baylibre.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The regulators set consists of 3 bucks DCDCs and 4 LDOs. The output voltages are configurable and are meant to supply power to the main processor and other components. Validation: Visual check: cat /sys/kernel/debug/regulator/regulator_summary Validation: userspace-consumer and virtual-regulator required to test further Enable/Disable: cat /sys/devices/platform/userspace-consumer-VDDSHV_SD_IO_PMIC/state echo disabled > /sys/devices/platform/ userspace-consumer-VDDSHV_SD_IO_PMIC/state echo enabled > /sys/devices/platform/ userspace-consumer-VDDSHV_SD_IO_PMIC/state Change voltage: cat /sys/devices/platform/regulator-virtual-ldo1/min_microvolts echo 1000000 > /sys/devices/platform/regulator-virtual-ldo1/ min_microvolts echo 3000000 > /sys/devices/platform/regulator-virtual-ldo1/ max_microvolts Signed-off-by: Jerome Neanne --- MAINTAINERS | 1 + drivers/regulator/Kconfig | 9 + drivers/regulator/Makefile | 1 + drivers/regulator/tps65219-regulator.c | 416 +++++++++++++++++++++++++ 4 files changed, 427 insertions(+) create mode 100644 drivers/regulator/tps65219-regulator.c diff --git a/MAINTAINERS b/MAINTAINERS index ffd533b8debc..faa9b2b7851b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14850,6 +14850,7 @@ F: drivers/regulator/palmas-regulator*.c F: drivers/regulator/pbias-regulator.c F: drivers/regulator/tps65217-regulator.c F: drivers/regulator/tps65218-regulator.c +F: drivers/regulator/tps65219-regulator.c F: drivers/regulator/tps65910-regulator.c F: drivers/regulator/twl-regulator.c F: drivers/regulator/twl6030-regulator.c diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig index 23e3e4a35cc9..f9bd683baa38 100644 --- a/drivers/regulator/Kconfig +++ b/drivers/regulator/Kconfig @@ -1384,6 +1384,15 @@ config REGULATOR_TPS65218 voltage regulators. It supports software based voltage control for different voltage domains =20 +config REGULATOR_TPS65219 + tristate "TI TPS65219 Power regulators" + depends on MFD_TPS65219 && OF + help + This driver supports TPS65219 voltage regulator chips. + TPS65219 series of PMICs have 3 single phase BUCKs & 4 LDOs + voltage regulators. It supports software based voltage control + for different voltage domains. + config REGULATOR_TPS6524X tristate "TI TPS6524X Power regulators" depends on SPI diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile index fa49bb6cc544..d7734a8dfbaf 100644 --- a/drivers/regulator/Makefile +++ b/drivers/regulator/Makefile @@ -162,6 +162,7 @@ obj-$(CONFIG_REGULATOR_TPS65086) +=3D tps65086-regulato= r.o obj-$(CONFIG_REGULATOR_TPS65090) +=3D tps65090-regulator.o obj-$(CONFIG_REGULATOR_TPS65217) +=3D tps65217-regulator.o obj-$(CONFIG_REGULATOR_TPS65218) +=3D tps65218-regulator.o +obj-$(CONFIG_REGULATOR_TPS65219) +=3D tps65219-regulator.o obj-$(CONFIG_REGULATOR_TPS6524X) +=3D tps6524x-regulator.o obj-$(CONFIG_REGULATOR_TPS6586X) +=3D tps6586x-regulator.o obj-$(CONFIG_REGULATOR_TPS65910) +=3D tps65910-regulator.o diff --git a/drivers/regulator/tps65219-regulator.c b/drivers/regulator/tps= 65219-regulator.c new file mode 100644 index 000000000000..7ba2594e437c --- /dev/null +++ b/drivers/regulator/tps65219-regulator.c @@ -0,0 +1,416 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// tps65219-regulator.c +// +// Regulator driver for TPS65219 PMIC +// +// Copyright (C) 2022 BayLibre Incorporated - https://www.baylibre.com/ +// +// This implementation derived from tps65218 authored by +// "J Keerthy " +// + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct tps65219_regulator_irq_type { + const char *irq_name; + const char *regulator_name; + const char *event_name; + unsigned long event; +}; + +struct tps65219_regulator_irq_type tps65219_regulator_irq_types[] =3D { + { "LDO3_SCG", "LDO3", "short circuit to ground", REGULATOR_EVENT_REGULATI= ON_OUT }, + { "LDO3_OC", "LDO3", "overcurrent", REGULATOR_EVENT_OVER_CURRENT }, + { "LDO3_UV", "LDO3", "undervoltage", REGULATOR_EVENT_UNDER_VOLTAGE }, + { "LDO4_SCG", "LDO4", "short circuit to ground", REGULATOR_EVENT_REGULATI= ON_OUT }, + { "LDO4_OC", "LDO4", "overcurrent", REGULATOR_EVENT_OVER_CURRENT }, + { "LDO4_UV", "LDO4", "undervoltage", REGULATOR_EVENT_UNDER_VOLTAGE }, + { "LDO1_SCG", "LDO1", "short circuit to ground", REGULATOR_EVENT_REGULATI= ON_OUT }, + { "LDO1_OC", "LDO1", "overcurrent", REGULATOR_EVENT_OVER_CURRENT }, + { "LDO1_UV", "LDO1", "undervoltage", REGULATOR_EVENT_UNDER_VOLTAGE }, + { "LDO2_SCG", "LDO2", "short circuit to ground", REGULATOR_EVENT_REGULATI= ON_OUT }, + { "LDO2_OC", "LDO2", "overcurrent", REGULATOR_EVENT_OVER_CURRENT }, + { "LDO2_UV", "LDO2", "undervoltage", REGULATOR_EVENT_UNDER_VOLTAGE }, + { "BUCK3_SCG", "BUCK3", "short circuit to ground", REGULATOR_EVENT_REGULA= TION_OUT }, + { "BUCK3_OC", "BUCK3", "overcurrent", REGULATOR_EVENT_OVER_CURRENT }, + { "BUCK3_NEG_OC", "BUCK3", "negative overcurrent", REGULATOR_EVENT_OVER_C= URRENT }, + { "BUCK3_UV", "BUCK3", "undervoltage", REGULATOR_EVENT_UNDER_VOLTAGE }, + { "BUCK1_SCG", "BUCK1", "short circuit to ground", REGULATOR_EVENT_REGULA= TION_OUT }, + { "BUCK1_OC", "BUCK1", "overcurrent", REGULATOR_EVENT_OVER_CURRENT }, + { "BUCK1_NEG_OC", "BUCK1", "negative overcurrent", REGULATOR_EVENT_OVER_C= URRENT }, + { "BUCK1_UV", "BUCK1", "undervoltage", REGULATOR_EVENT_UNDER_VOLTAGE }, + { "BUCK2_SCG", "BUCK2", "short circuit to ground", REGULATOR_EVENT_REGULA= TION_OUT }, + { "BUCK2_OC", "BUCK2", "overcurrent", REGULATOR_EVENT_OVER_CURRENT }, + { "BUCK2_NEG_OC", "BUCK2", "negative overcurrent", REGULATOR_EVENT_OVER_C= URRENT }, + { "BUCK2_UV", "BUCK2", "undervoltage", REGULATOR_EVENT_UNDER_VOLTAGE }, + { "BUCK1_RV", "BUCK1", "residual voltage", REGULATOR_EVENT_OVER_VOLTAGE_W= ARN }, + { "BUCK2_RV", "BUCK2", "residual voltage", REGULATOR_EVENT_OVER_VOLTAGE_W= ARN }, + { "BUCK3_RV", "BUCK3", "residual voltage", REGULATOR_EVENT_OVER_VOLTAGE_W= ARN }, + { "LDO1_RV", "LDO1", "residual voltage", REGULATOR_EVENT_OVER_VOLTAGE_WAR= N }, + { "LDO2_RV", "LDO2", "residual voltage", REGULATOR_EVENT_OVER_VOLTAGE_WAR= N }, + { "LDO3_RV", "LDO3", "residual voltage", REGULATOR_EVENT_OVER_VOLTAGE_WAR= N }, + { "LDO4_RV", "LDO4", "residual voltage", REGULATOR_EVENT_OVER_VOLTAGE_WAR= N }, + { "BUCK1_RV_SD", "BUCK1", "residual voltage on shutdown", + REGULATOR_EVENT_OVER_VOLTAGE_WARN }, + { "BUCK2_RV_SD", "BUCK2", "residual voltage on shutdown", + REGULATOR_EVENT_OVER_VOLTAGE_WARN }, + { "BUCK3_RV_SD", "BUCK3", "residual voltage on shutdown", + REGULATOR_EVENT_OVER_VOLTAGE_WARN }, + { "LDO1_RV_SD", "LDO1", "residual voltage on shutdown", REGULATOR_EVENT_O= VER_VOLTAGE_WARN }, + { "LDO2_RV_SD", "LDO2", "residual voltage on shutdown", REGULATOR_EVENT_O= VER_VOLTAGE_WARN }, + { "LDO3_RV_SD", "LDO3", "residual voltage on shutdown", REGULATOR_EVENT_O= VER_VOLTAGE_WARN }, + { "LDO4_RV_SD", "LDO4", "residual voltage on shutdown", REGULATOR_EVENT_O= VER_VOLTAGE_WARN }, + { "SENSOR_3_WARM", "SENSOR3", "warm temperature", REGULATOR_EVENT_OVER_TE= MP_WARN}, + { "SENSOR_2_WARM", "SENSOR2", "warm temperature", REGULATOR_EVENT_OVER_TE= MP_WARN }, + { "SENSOR_1_WARM", "SENSOR1", "warm temperature", REGULATOR_EVENT_OVER_TE= MP_WARN }, + { "SENSOR_0_WARM", "SENSOR0", "warm temperature", REGULATOR_EVENT_OVER_TE= MP_WARN }, + { "SENSOR_3_HOT", "SENSOR3", "hot temperature", REGULATOR_EVENT_OVER_TEMP= }, + { "SENSOR_2_HOT", "SENSOR2", "hot temperature", REGULATOR_EVENT_OVER_TEMP= }, + { "SENSOR_1_HOT", "SENSOR1", "hot temperature", REGULATOR_EVENT_OVER_TEMP= }, + { "SENSOR_0_HOT", "SENSOR0", "hot temperature", REGULATOR_EVENT_OVER_TEMP= }, + { "TIMEOUT", "", "", REGULATOR_EVENT_ABORT_VOLTAGE_CHANGE }, +}; + +struct tps65219_regulator_irq_data { + struct device *dev; + struct tps65219_regulator_irq_type *type; + struct regulator_dev *rdev; +}; + +#define TPS65219_REGULATOR(_name, _of, _id, _type, _ops, _n, _vr, _vm, _er= , \ + _em, _cr, _cm, _lr, _nlr, _delay, _fuv, \ + _ct, _ncl, _bpm) \ + { \ + .name =3D _name, \ + .of_match =3D _of, \ + .regulators_node =3D of_match_ptr("regulators"), \ + .supply_name =3D _of, \ + .id =3D _id, \ + .ops =3D &(_ops), \ + .n_voltages =3D _n, \ + .type =3D _type, \ + .owner =3D THIS_MODULE, \ + .vsel_reg =3D _vr, \ + .vsel_mask =3D _vm, \ + .csel_reg =3D _cr, \ + .csel_mask =3D _cm, \ + .curr_table =3D _ct, \ + .n_current_limits =3D _ncl, \ + .enable_reg =3D _er, \ + .enable_mask =3D _em, \ + .volt_table =3D NULL, \ + .linear_ranges =3D _lr, \ + .n_linear_ranges =3D _nlr, \ + .ramp_delay =3D _delay, \ + .fixed_uV =3D _fuv, \ + .bypass_reg =3D _vr, \ + .bypass_mask =3D _bpm, \ + .bypass_val_on =3D 1, \ + } \ + +static const struct linear_range bucks_ranges[] =3D { + REGULATOR_LINEAR_RANGE(600000, 0x0, 0x1f, 25000), + REGULATOR_LINEAR_RANGE(1400000, 0x20, 0x33, 100000), + REGULATOR_LINEAR_RANGE(3400000, 0x34, 0x3f, 0), +}; + +static const struct linear_range ldos_1_2_ranges[] =3D { + REGULATOR_LINEAR_RANGE(600000, 0x0, 0x37, 50000), + REGULATOR_LINEAR_RANGE(3400000, 0x38, 0x3f, 0), +}; + +static const struct linear_range ldos_3_4_ranges[] =3D { + REGULATOR_LINEAR_RANGE(1200000, 0x0, 0xC, 0), + REGULATOR_LINEAR_RANGE(1250000, 0xD, 0x35, 50000), + REGULATOR_LINEAR_RANGE(3300000, 0x36, 0x3F, 0), +}; + +static int tps65219_set_mode(struct regulator_dev *dev, unsigned int mode) +{ + struct tps65219 *tps =3D rdev_get_drvdata(dev); + + switch (mode) { + case REGULATOR_MODE_NORMAL: + return regmap_set_bits(tps->regmap, TPS65219_REG_STBY_1_CONFIG, + dev->desc->enable_mask); + + case REGULATOR_MODE_STANDBY: + return regmap_clear_bits(tps->regmap, + TPS65219_REG_STBY_1_CONFIG, + dev->desc->enable_mask); + default: + return -EINVAL; + } +} + +static unsigned int tps65219_get_mode(struct regulator_dev *dev) +{ + struct tps65219 *tps =3D rdev_get_drvdata(dev); + unsigned int rid =3D rdev_get_id(dev); + int ret, value =3D 0; + + ret =3D regmap_read(tps->regmap, TPS65219_REG_STBY_1_CONFIG, &value); + if (ret) { + dev_dbg(tps->dev, "%s failed for regulator %s: %d ", + __func__, dev->desc->name, ret); + return ret; + } + value =3D (value & BIT(rid)) >> rid; + if (value) + return REGULATOR_MODE_STANDBY; + else + return REGULATOR_MODE_NORMAL; +} + +/* + * generic regulator_set_bypass_regmap does not fully match requirements + * TPS65219 Requires explicitly that regulator is disabled before switch + */ +static int tps65219_set_bypass(struct regulator_dev *dev, bool enable) +{ + struct tps65219 *tps =3D rdev_get_drvdata(dev); + unsigned int rid =3D rdev_get_id(dev); + int ret =3D 0; + + if (dev->desc->ops->enable) { + dev_err(tps->dev, + "%s LDO%d enabled, must be shut down to set bypass ", + __func__, rid); + return -EBUSY; + } + ret =3D regulator_set_bypass_regmap(dev, enable); + return ret; +} + +/* Operations permitted on BUCK1/2/3 */ +static const struct regulator_ops tps65219_bucks_ops =3D { + .is_enabled =3D regulator_is_enabled_regmap, + .enable =3D regulator_enable_regmap, + .disable =3D regulator_disable_regmap, + .set_mode =3D tps65219_set_mode, + .get_mode =3D tps65219_get_mode, + .get_voltage_sel =3D regulator_get_voltage_sel_regmap, + .set_voltage_sel =3D regulator_set_voltage_sel_regmap, + .list_voltage =3D regulator_list_voltage_linear_range, + .map_voltage =3D regulator_map_voltage_linear_range, + .set_voltage_time_sel =3D regulator_set_voltage_time_sel, + +}; + +/* Operations permitted on LDO1/2 */ +static const struct regulator_ops tps65219_ldos_1_2_ops =3D { + .is_enabled =3D regulator_is_enabled_regmap, + .enable =3D regulator_enable_regmap, + .disable =3D regulator_disable_regmap, + .set_mode =3D tps65219_set_mode, + .get_mode =3D tps65219_get_mode, + .get_voltage_sel =3D regulator_get_voltage_sel_regmap, + .set_voltage_sel =3D regulator_set_voltage_sel_regmap, + .list_voltage =3D regulator_list_voltage_linear_range, + .map_voltage =3D regulator_map_voltage_linear_range, + .set_bypass =3D tps65219_set_bypass, + .get_bypass =3D regulator_get_bypass_regmap, +}; + +/* Operations permitted on LDO3/4 */ +static const struct regulator_ops tps65219_ldos_3_4_ops =3D { + .is_enabled =3D regulator_is_enabled_regmap, + .enable =3D regulator_enable_regmap, + .disable =3D regulator_disable_regmap, + .set_mode =3D tps65219_set_mode, + .get_mode =3D tps65219_get_mode, + .get_voltage_sel =3D regulator_get_voltage_sel_regmap, + .set_voltage_sel =3D regulator_set_voltage_sel_regmap, + .list_voltage =3D regulator_list_voltage_linear_range, + .map_voltage =3D regulator_map_voltage_linear_range, +}; + +static const struct regulator_desc regulators[] =3D { + TPS65219_REGULATOR("BUCK1", "buck1", TPS65219_BUCK_1, + REGULATOR_VOLTAGE, tps65219_bucks_ops, 64, + TPS65219_REG_BUCK1_VOUT, + TPS65219_BUCKS_LDOS_VOUT_VSET_MASK, + TPS65219_REG_ENABLE_CTRL, + TPS65219_ENABLE_BUCK1_EN_MASK, 0, 0, bucks_ranges, + 3, 4000, 0, NULL, 0, 0), + TPS65219_REGULATOR("BUCK2", "buck2", TPS65219_BUCK_2, + REGULATOR_VOLTAGE, tps65219_bucks_ops, 64, + TPS65219_REG_BUCK2_VOUT, + TPS65219_BUCKS_LDOS_VOUT_VSET_MASK, + TPS65219_REG_ENABLE_CTRL, + TPS65219_ENABLE_BUCK2_EN_MASK, 0, 0, bucks_ranges, + 3, 4000, 0, NULL, 0, 0), + TPS65219_REGULATOR("BUCK3", "buck3", TPS65219_BUCK_3, + REGULATOR_VOLTAGE, tps65219_bucks_ops, 64, + TPS65219_REG_BUCK3_VOUT, + TPS65219_BUCKS_LDOS_VOUT_VSET_MASK, + TPS65219_REG_ENABLE_CTRL, + TPS65219_ENABLE_BUCK3_EN_MASK, 0, 0, bucks_ranges, + 3, 0, 0, NULL, 0, 0), + TPS65219_REGULATOR("LDO1", "ldo1", TPS65219_LDO_1, + REGULATOR_VOLTAGE, tps65219_ldos_1_2_ops, 64, + TPS65219_REG_LDO1_VOUT, + TPS65219_BUCKS_LDOS_VOUT_VSET_MASK, + TPS65219_REG_ENABLE_CTRL, + TPS65219_ENABLE_LDO1_EN_MASK, 0, 0, ldos_1_2_ranges, + 2, 0, 0, NULL, 0, TPS65219_LDOS_BYP_CONFIG_MASK), + TPS65219_REGULATOR("LDO2", "ldo2", TPS65219_LDO_2, + REGULATOR_VOLTAGE, tps65219_ldos_1_2_ops, 64, + TPS65219_REG_LDO2_VOUT, + TPS65219_BUCKS_LDOS_VOUT_VSET_MASK, + TPS65219_REG_ENABLE_CTRL, + TPS65219_ENABLE_LDO2_EN_MASK, 0, 0, ldos_1_2_ranges, + 2, 0, 0, NULL, 0, TPS65219_LDOS_BYP_CONFIG_MASK), + TPS65219_REGULATOR("LDO3", "ldo3", TPS65219_LDO_3, + REGULATOR_VOLTAGE, tps65219_ldos_3_4_ops, 64, + TPS65219_REG_LDO3_VOUT, + TPS65219_BUCKS_LDOS_VOUT_VSET_MASK, + TPS65219_REG_ENABLE_CTRL, + TPS65219_ENABLE_LDO3_EN_MASK, 0, 0, ldos_3_4_ranges, + 3, 0, 0, NULL, 0, 0), + TPS65219_REGULATOR("LDO4", "ldo4", TPS65219_LDO_4, + REGULATOR_VOLTAGE, tps65219_ldos_3_4_ops, 64, + TPS65219_REG_LDO4_VOUT, + TPS65219_BUCKS_LDOS_VOUT_VSET_MASK, + TPS65219_REG_ENABLE_CTRL, + TPS65219_ENABLE_LDO4_EN_MASK, 0, 0, ldos_3_4_ranges, + 3, 0, 0, NULL, 0, 0), +}; + +static irqreturn_t tps65219_regulator_irq_handler(int irq, void *data) +{ + struct tps65219_regulator_irq_data *irq_data =3D data; + + if (irq_data->type->event_name[0] =3D=3D '\0') { + /* This is the timeout interrupt no specific regulator */ + dev_err(irq_data->dev, + "System was put in shutdown due to timeout during an active or standby = transition.\n"); + return IRQ_HANDLED; + } + + regulator_notifier_call_chain(irq_data->rdev, + irq_data->type->event, NULL); + + dev_err(irq_data->dev, "Error IRQ trap %s for %s\n", + irq_data->type->event_name, irq_data->type->regulator_name); + return IRQ_HANDLED; +} + +static int tps65219_get_rdev_by_name(const char *regulator_name, + struct regulator_dev *rdevtbl[7], + struct regulator_dev *dev) +{ + int i; + + for (i =3D 0; i < ARRAY_SIZE(regulators); i++) { + if (strcmp(regulator_name, regulators[i].name) =3D=3D 0) { + dev =3D rdevtbl[i]; + return 0; + } + } + return -EINVAL; +} + +static int tps65219_regulator_probe(struct platform_device *pdev) +{ + struct tps65219 *tps =3D dev_get_drvdata(pdev->dev.parent); + struct regulator_dev *rdev; + struct regulator_config config =3D { }; + int i; + int error; + int irq; + struct tps65219_regulator_irq_data *irq_data; + struct tps65219_regulator_irq_type *irq_type; + struct regulator_dev *rdevtbl[7]; + + config.dev =3D tps->dev; + config.driver_data =3D tps; + config.regmap =3D tps->regmap; + + for (i =3D 0; i < ARRAY_SIZE(regulators); i++) { + dev_dbg(tps->dev, "%s regul i=3D %d START", __func__, i); + rdev =3D devm_regulator_register(&pdev->dev, ®ulators[i], + &config); + if (IS_ERR(rdev)) { + dev_err(tps->dev, "failed to register %s regulator\n", + pdev->name); + return PTR_ERR(rdev); + } + rdevtbl[i] =3D rdev; + dev_dbg(tps->dev, "%s regul i=3D %d COMPLETED", __func__, i); + } + + irq_data =3D devm_kmalloc(tps->dev, + ARRAY_SIZE(tps65219_regulator_irq_types) * + sizeof(struct tps65219_regulator_irq_data), + GFP_KERNEL); + if (!irq_data) + return -ENOMEM; + + for (i =3D 0; i < ARRAY_SIZE(tps65219_regulator_irq_types); ++i) { + irq_type =3D &tps65219_regulator_irq_types[i]; + + irq =3D platform_get_irq_byname(pdev, irq_type->irq_name); + if (irq < 0) { + dev_err(tps->dev, "Failed to get IRQ %s: %d\n", + irq_type->irq_name, irq); + return -EINVAL; + } + irq_data[i].dev =3D tps->dev; + irq_data[i].type =3D irq_type; + + tps65219_get_rdev_by_name(irq_type->regulator_name, rdevtbl, rdev); + if (rdev < 0) { + dev_err(tps->dev, "Failed to get rdev for %s\n", + irq_type->regulator_name); + return -EINVAL; + } + irq_data[i].rdev =3D rdev; + + error =3D devm_request_threaded_irq(tps->dev, irq, NULL, + tps65219_regulator_irq_handler, + IRQF_ONESHOT, + irq_type->irq_name, + &irq_data[i]); + if (error) { + dev_err(tps->dev, "failed to request %s IRQ %d: %d\n", + irq_type->irq_name, irq, error); + return error; + } + } + + return 0; +} + +static const struct platform_device_id tps65219_regulator_id_table[] =3D { + { "tps65219-regulator", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(platform, tps65219_regulator_id_table); + +static struct platform_driver tps65219_regulator_driver =3D { + .driver =3D { + .name =3D "tps65219-pmic", + }, + .probe =3D tps65219_regulator_probe, + .id_table =3D tps65219_regulator_id_table, +}; + +module_platform_driver(tps65219_regulator_driver); + +MODULE_AUTHOR("Jerome Neanne "); +MODULE_DESCRIPTION("TPS65219 voltage regulator driver"); +MODULE_ALIAS("platform:tps65219-pmic"); +MODULE_LICENSE("GPL"); --=20 2.17.1 From nobody Sat Apr 11 20:58:56 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A4BDFC25B06 for ; Fri, 5 Aug 2022 12:20:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240650AbiHEMU2 (ORCPT ); Fri, 5 Aug 2022 08:20:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56632 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240789AbiHEMTw (ORCPT ); Fri, 5 Aug 2022 08:19:52 -0400 Received: from mail-ej1-x631.google.com (mail-ej1-x631.google.com [IPv6:2a00:1450:4864:20::631]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5A2C27A50B for ; Fri, 5 Aug 2022 05:19:36 -0700 (PDT) Received: by mail-ej1-x631.google.com with SMTP id y13so4647473ejp.13 for ; Fri, 05 Aug 2022 05:19:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc; bh=XdUXjfksZQ9iMFS15BrD7+WKE/NgfG2aT9cbNg97hXc=; b=Ezz4AA2GG/bTYXwH9nQgJElDJpqXHETdXSbgXflBuyAqkJNO8YkT9QfW/b0LK8pr0g J9VxGh5DGdwfXCCG16vEmACGaz5KIs3WjD4HZ0y/LjYjWgzVlwe8x7SV4o1Oa35WsCKU v2scxaINFByCNRuf3MqeikX+s9+yCJrhJFpy7qyGB+dg9/IKA+/HgaNqK1ihh90nl+KT CgfTxyiCMzHiJOPNhtAYEa8tUdU1wkLc9Go0BLcVUeS1PiTsePh2XhM0RFPqrAFE3u0O mxcdzXOHS0uBAHe8JusyjTdUBHSZjm5lzZosVLerEru5j+7HCmLa9yntM8BEDKCx6EBb WEnA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc; bh=XdUXjfksZQ9iMFS15BrD7+WKE/NgfG2aT9cbNg97hXc=; b=qYM95tV4HHcWT/yXXL8QFfXasjYf1Pw6V3Cz1kSAwYXfvxCHdYHdtAjHK8UAZZD1LA Ei4QYcgRl0CbHYIAMwWWL5d/F0R4nu/m4LgW6j82gAaehoYtfcnUv1VNrU/5UKb1rcs4 puQuIXwvoPzGzWI12YF7vaO6AE8WXXuHsJ4gmv7mRadYerT1y9pCwD4AbhGSE8TOBNRm SgSoH6OGNqAhaXquKgFmh12QpONXDnFf9m2HD2E+18tO8Uxze5SltwOTTgvZ4KW/sjAs wMOajAI7SRqyHi07kFU5dpeXKD/JzPVIeRWPCJHZL4PQe7dSoC4ndnNYI65Vr3sP7iEc BK0A== X-Gm-Message-State: ACgBeo3tLwRjWhkexjJ35fDzW2+lO7BdB50wVOz+qVO80RC3xNyJnQy1 erwKmSyTP9nw1rIEBI2pF3kM6g== X-Google-Smtp-Source: AA6agR7EviyVJOK5VZ5j9yWj0XCUdikn3E8Fkqvp0peiRtd7if9pv8c/5biu5a+AByiefOsuhjDuig== X-Received: by 2002:a17:907:2889:b0:730:b35c:d91f with SMTP id em9-20020a170907288900b00730b35cd91fmr4986318ejc.57.1659701974642; Fri, 05 Aug 2022 05:19:34 -0700 (PDT) Received: from localhost.localdomain (2a02-8440-5241-be09-b892-f882-607f-7a79.rev.sfr.net. [2a02:8440:5241:be09:b892:f882:607f:7a79]) by smtp.gmail.com with ESMTPSA id kx13-20020a170907774d00b0072b3464c043sm1506111ejc.116.2022.08.05.05.19.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Aug 2022 05:19:34 -0700 (PDT) From: Jerome Neanne To: lgirdwood@gmail.com, broonie@kernel.org, robh+dt@kernel.org, nm@ti.com, kristo@kernel.org, dmitry.torokhov@gmail.com Cc: khilman@baylibre.com, narmstrong@baylibre.com, msp@baylibre.com, j-keerthy@ti.com, lee.jones@linaro.org, jneanne@baylibre.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-input@vger.kernel.org Subject: [PATCH v3 09/10] Input: Add tps65219 interrupt driven powerbutton Date: Fri, 5 Aug 2022 14:18:51 +0200 Message-Id: <20220805121852.21254-10-jneanne@baylibre.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220805121852.21254-1-jneanne@baylibre.com> References: <20220805121852.21254-1-jneanne@baylibre.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" TPS65219 has different interrupts compared to other TPS6521* chips. TPS65219 defines two interrupts for the powerbutton one for push and one for release. This driver is very simple in that it maps the push interrupt to a key input and the release interrupt to a key release. Signed-off-by: Markus Schneider-Pargmann Signed-off-by: Jerome Neanne --- drivers/input/misc/Kconfig | 10 ++ drivers/input/misc/Makefile | 1 + drivers/input/misc/tps65219-pwrbutton.c | 150 ++++++++++++++++++++++++ 3 files changed, 161 insertions(+) create mode 100644 drivers/input/misc/tps65219-pwrbutton.c diff --git a/drivers/input/misc/Kconfig b/drivers/input/misc/Kconfig index a18ab7358d8f..18d4a321e7ff 100644 --- a/drivers/input/misc/Kconfig +++ b/drivers/input/misc/Kconfig @@ -468,6 +468,16 @@ config INPUT_TPS65218_PWRBUTTON To compile this driver as a module, choose M here. The module will be called tps65218-pwrbutton. =20 +config INPUT_TPS65219_PWRBUTTON + tristate "TPS65219 Power button driver" + depends on MFD_TPS65219 + help + Say Y here if you want to enable power button reporting for + TPS65219 Power Management IC devices. + + To compile this driver as a module, choose M here. The module will + be called tps65219-pwrbutton. + config INPUT_AXP20X_PEK tristate "X-Powers AXP20X power button driver" depends on MFD_AXP20X diff --git a/drivers/input/misc/Makefile b/drivers/input/misc/Makefile index 28dfc444f0a9..fe8f47402d12 100644 --- a/drivers/input/misc/Makefile +++ b/drivers/input/misc/Makefile @@ -78,6 +78,7 @@ obj-$(CONFIG_INPUT_SOC_BUTTON_ARRAY) +=3D soc_button_arra= y.o obj-$(CONFIG_INPUT_SPARCSPKR) +=3D sparcspkr.o obj-$(CONFIG_INPUT_STPMIC1_ONKEY) +=3D stpmic1_onkey.o obj-$(CONFIG_INPUT_TPS65218_PWRBUTTON) +=3D tps65218-pwrbutton.o +obj-$(CONFIG_INPUT_TPS65219_PWRBUTTON) +=3D tps65219-pwrbutton.o obj-$(CONFIG_INPUT_TWL4030_PWRBUTTON) +=3D twl4030-pwrbutton.o obj-$(CONFIG_INPUT_TWL4030_VIBRA) +=3D twl4030-vibra.o obj-$(CONFIG_INPUT_TWL6040_VIBRA) +=3D twl6040-vibra.o diff --git a/drivers/input/misc/tps65219-pwrbutton.c b/drivers/input/misc/t= ps65219-pwrbutton.c new file mode 100644 index 000000000000..48ced7b63ec3 --- /dev/null +++ b/drivers/input/misc/tps65219-pwrbutton.c @@ -0,0 +1,150 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Driver for TPS65219 Push Button +// +// Copyright (C) 2022 BayLibre Incorporated - https://www.baylibre.com/ +// + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct tps65219_pwrbutton { + struct device *dev; + struct input_dev *idev; + char phys[32]; +}; + +static irqreturn_t tps65219_pb_push_irq(int irq, void *_pwr) +{ + struct tps65219_pwrbutton *pwr =3D _pwr; + + input_report_key(pwr->idev, KEY_POWER, 1); + pm_wakeup_event(pwr->dev, 0); + input_sync(pwr->idev); + + return IRQ_HANDLED; +} + +static irqreturn_t tps65219_pb_release_irq(int irq, void *_pwr) +{ + struct tps65219_pwrbutton *pwr =3D _pwr; + + input_report_key(pwr->idev, KEY_POWER, 0); + input_sync(pwr->idev); + + return IRQ_HANDLED; +} + +static int tps65219_pb_probe(struct platform_device *pdev) +{ + struct tps65219 *tps =3D dev_get_drvdata(pdev->dev.parent); + struct device *dev =3D &pdev->dev; + struct tps65219_pwrbutton *pwr; + struct input_dev *idev; + int error; + int push_irq; + int release_irq; + + pwr =3D devm_kzalloc(dev, sizeof(*pwr), GFP_KERNEL); + if (!pwr) + return -ENOMEM; + + idev =3D devm_input_allocate_device(dev); + if (!idev) + return -ENOMEM; + + idev->name =3D pdev->name; + snprintf(pwr->phys, sizeof(pwr->phys), "%s/input0", + pdev->name); + idev->phys =3D pwr->phys; + idev->dev.parent =3D dev; + idev->id.bustype =3D BUS_I2C; + + input_set_capability(idev, EV_KEY, KEY_POWER); + + pwr->dev =3D dev; + pwr->idev =3D idev; + device_init_wakeup(dev, true); + + push_irq =3D platform_get_irq(pdev, 0); + if (push_irq < 0) + return -EINVAL; + + release_irq =3D platform_get_irq(pdev, 1); + if (release_irq < 0) + return -EINVAL; + + error =3D devm_request_threaded_irq(dev, push_irq, NULL, + tps65219_pb_push_irq, + IRQF_ONESHOT, + dev->init_name, pwr); + if (error) { + dev_err(dev, "failed to request push IRQ #%d: %d\n", push_irq, + error); + return error; + } + + error =3D devm_request_threaded_irq(dev, release_irq, NULL, + tps65219_pb_release_irq, + IRQF_ONESHOT, + dev->init_name, pwr); + if (error) { + dev_err(dev, "failed to request release IRQ #%d: %d\n", + release_irq, error); + return error; + } + + error =3D input_register_device(idev); + if (error) { + dev_err(dev, "Can't register power button: %d\n", error); + return error; + } + + /* Enable interrupts for the pushbutton */ + regmap_clear_bits(tps->regmap, TPS65219_REG_MASK_CONFIG, + TPS65219_REG_MASK_INT_FOR_PB_MASK); + + /* Set PB/EN/VSENSE pin to be a pushbutton */ + regmap_update_bits(tps->regmap, TPS65219_REG_MFP_2_CONFIG, + TPS65219_MFP_2_EN_PB_VSENSE_MASK, TPS65219_MFP_2_PB); + + return 0; +} + +static int tps65219_pb_remove(struct platform_device *pdev) +{ + struct tps65219 *tps =3D dev_get_drvdata(pdev->dev.parent); + + /* Disable interrupt for the pushbutton */ + return regmap_update_bits(tps->regmap, TPS65219_REG_MASK_CONFIG, + TPS65219_REG_MASK_INT_FOR_PB_MASK, + TPS65219_REG_MASK_INT_FOR_PB_MASK); +} + +static const struct platform_device_id tps65219_pwrbtn_id_table[] =3D { + { "tps65219-pwrbutton", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(platform, tps65219_pwrbtn_id_table); + +static struct platform_driver tps65219_pb_driver =3D { + .probe =3D tps65219_pb_probe, + .remove =3D tps65219_pb_remove, + .driver =3D { + .name =3D "tps65219_pwrbutton", + }, + .id_table =3D tps65219_pwrbtn_id_table, +}; +module_platform_driver(tps65219_pb_driver); + +MODULE_DESCRIPTION("TPS65219 Power Button"); +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Markus Schneider-Pargmann X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 55687C00140 for ; Fri, 5 Aug 2022 12:20:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240777AbiHEMUp (ORCPT ); Fri, 5 Aug 2022 08:20:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56824 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240811AbiHEMUF (ORCPT ); Fri, 5 Aug 2022 08:20:05 -0400 Received: from mail-ej1-x62f.google.com (mail-ej1-x62f.google.com [IPv6:2a00:1450:4864:20::62f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 50D447A506 for ; Fri, 5 Aug 2022 05:19:46 -0700 (PDT) Received: by mail-ej1-x62f.google.com with SMTP id tl27so4760370ejc.1 for ; Fri, 05 Aug 2022 05:19:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc; bh=Sb8YvNB59ODw1an6ha6Ie3iag8hDt0GZw+CZTxlCMRc=; b=MWt382uJO5dILVUI3JyjixhKUvoKabVNq8ZEzM+v+aAiBNJDdOddUayN5fXs4JXN8C m7vMNueJ5wj/9mdXiYdCQpzXo8ty1BfkK/8+3ZpS8HuvkeeMqC33iNFeCD7nS37+qJR9 dXRuDA48OC2aC5WF+bPRqKE+OXD4TCNDbOiDaPVJrX9qlMIqZ3YHFHaYl5VM18cAxUly d+DjxRaTzF5H9CXGJdcTtL/Srmz9pmabQWXJBf19r0+8PSHkhyxfZ4niw1espmCLa2TS f2S8ZPT+aEFEDXvnPF2lPACNsHDuzAlCmrzuvVpYkJ4XVLGahm9o19VUJZifYJh3N3cs gFyA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc; bh=Sb8YvNB59ODw1an6ha6Ie3iag8hDt0GZw+CZTxlCMRc=; b=7rn7K2GDN7bDIgQoS1p3M1wpH1EC8gWfxvkf53fLXQFeIVHLKF6JeNbYwQN3TmOBLQ vLs4Cv+nYPvkYe9xmOZT/tqFLxtpEvHJPGCMNjvap1vipyflvL3cdl7Wvusk6lnPMqGF mp6TC5DQTvoC5BqQy2wxYvSmgJhcSwLcJ34fxC2epCm2sLjyMn6mqPrkKvmXHRuXUUIs iWjv8MPbqDPLNyoZDeC8+mk9KAQcg/T3yU/5PSuZUNPVpseOvdb0MN5U6LzpQkvFWjiZ TMlnch5YNsHdHIyuDn3te2sYRHBM/0InlOXi4VVWtrbcL76uEHL3wShkRKO+lczWneK8 v5EA== X-Gm-Message-State: ACgBeo1BJgQMiUJF3fdKg1Ozlqb6BPH/uS6Ih1TU+gabuhyGJAKlZ+c+ iyMaOLwjVzfr6036FYRGS0KnAg== X-Google-Smtp-Source: AA6agR4jbzi6qTGaK1l/Q47nB7mzGrUQT8Ocd6+d8ebwjA/2eV+ceRVHwhYbHsLTYRZ6CgV6LafJRw== X-Received: by 2002:a17:907:a06a:b0:730:d10e:fff3 with SMTP id ia10-20020a170907a06a00b00730d10efff3mr5314861ejc.109.1659701980966; Fri, 05 Aug 2022 05:19:40 -0700 (PDT) Received: from localhost.localdomain (2a02-8440-5241-be09-b892-f882-607f-7a79.rev.sfr.net. [2a02:8440:5241:be09:b892:f882:607f:7a79]) by smtp.gmail.com with ESMTPSA id kx13-20020a170907774d00b0072b3464c043sm1506111ejc.116.2022.08.05.05.19.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Aug 2022 05:19:40 -0700 (PDT) From: Jerome Neanne To: lgirdwood@gmail.com, broonie@kernel.org, robh+dt@kernel.org, nm@ti.com, kristo@kernel.org, dmitry.torokhov@gmail.com Cc: khilman@baylibre.com, narmstrong@baylibre.com, msp@baylibre.com, j-keerthy@ti.com, lee.jones@linaro.org, jneanne@baylibre.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-input@vger.kernel.org Subject: [PATCH v3 10/10] arm64: defconfig: Add tps65219 as modules Date: Fri, 5 Aug 2022 14:18:52 +0200 Message-Id: <20220805121852.21254-11-jneanne@baylibre.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220805121852.21254-1-jneanne@baylibre.com> References: <20220805121852.21254-1-jneanne@baylibre.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This adds defconfig option to support TPS65219 PMIC, MFD, Regulators and power-button. Signed-off-by: Jerome Neanne --- arch/arm64/configs/defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index d5b2d2dd4904..d64e00355fcd 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -406,6 +406,7 @@ CONFIG_TOUCHSCREEN_GOODIX=3Dm CONFIG_TOUCHSCREEN_EDT_FT5X06=3Dm CONFIG_INPUT_MISC=3Dy CONFIG_INPUT_PM8941_PWRKEY=3Dy +CONFIG_INPUT_TPS65219_PWRBUTTON=3Dm CONFIG_INPUT_PM8XXX_VIBRATOR=3Dm CONFIG_INPUT_PWM_BEEPER=3Dm CONFIG_INPUT_PWM_VIBRA=3Dm @@ -639,6 +640,7 @@ CONFIG_MFD_SPMI_PMIC=3Dy CONFIG_MFD_RK808=3Dy CONFIG_MFD_SEC_CORE=3Dy CONFIG_MFD_SL28CPLD=3Dy +CONFIG_MFD_TPS65219=3Dm CONFIG_MFD_ROHM_BD718XX=3Dy CONFIG_MFD_WCD934X=3Dm CONFIG_REGULATOR_FIXED_VOLTAGE=3Dy @@ -666,6 +668,7 @@ CONFIG_REGULATOR_QCOM_SPMI=3Dy CONFIG_REGULATOR_RK808=3Dy CONFIG_REGULATOR_S2MPS11=3Dy CONFIG_REGULATOR_TPS65132=3Dm +CONFIG_REGULATOR_TPS65219=3Dm CONFIG_REGULATOR_VCTRL=3Dm CONFIG_RC_CORE=3Dm CONFIG_RC_DECODERS=3Dy --=20 2.17.1