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[81.185.163.235]) by smtp.gmail.com with ESMTPSA id o15-20020adfcf0f000000b0021d6a520ce9sm1156817wrj.47.2022.08.04.06.09.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Aug 2022 06:10:00 -0700 (PDT) From: bchihi@baylibre.com To: rafael@kernel.org, rui.zhang@intel.com, daniel.lezcano@linaro.org, amitk@kernel.org Cc: linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, khilman@baylibre.com, mka@chromium.org, robh+dt@kernel.org, krzk+dt@kernel.org, matthias.bgg@gmail.com, p.zabel@pengutronix.de, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, james.lo@mediatek.com, fan.chen@mediatek.com, louis.yu@mediatek.com, rex-bc.chen@mediatek.com, abailon@baylibre.com Subject: [PATCH v8.1, 3/7] arm64: dts: mt8192: Add thermal zone Date: Thu, 4 Aug 2022 15:09:08 +0200 Message-Id: <20220804130912.676043-4-bchihi@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220804130912.676043-1-bchihi@baylibre.com> References: <20220804130912.676043-1-bchihi@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Balsam CHIHI This adds the thermal zone for the mt8192. Signed-off-by: Balsam CHIHI --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 113 ++++++++++++++++++++++- 1 file changed, 112 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts= /mediatek/mt8192.dtsi index cbae5a5ee4a0..3320b5c14ee3 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0 OR MIT) /* - * Copyright (C) 2020 MediaTek Inc. + * Copyright (C) 2022 MediaTek Inc. * Author: Seiya Wang */ =20 @@ -12,6 +12,7 @@ #include #include #include +#include =20 / { compatible =3D "mediatek,mt8192"; @@ -599,6 +600,28 @@ spi0: spi@1100a000 { status =3D "disabled"; }; =20 + lvts_ap: thermal-sensor@1100b000 { + compatible =3D "mediatek,mt8192-lvts-ap"; + #thermal-sensor-cells =3D <1>; + reg =3D <0 0x1100b000 0 0x1000>; + interrupts =3D ; + clocks =3D <&infracfg CLK_INFRA_THERM>; + resets =3D <&infracfg MT8192_INFRA_RST0_THERM_CTRL_SWRST>; + nvmem-cells =3D <&lvts_e_data1>; + nvmem-cell-names =3D "lvts_calib_data1"; + }; + + lvts_mcu: thermal-sensor@11278000 { + compatible =3D "mediatek,mt8192-lvts-mcu"; + #thermal-sensor-cells =3D <1>; + reg =3D <0 0x11278000 0 0x1000>; + interrupts =3D ; + clocks =3D <&infracfg CLK_INFRA_THERM>; + resets =3D <&infracfg MT8192_INFRA_RST4_THERM_CTRL_MCU_SWRST>; + nvmem-cells =3D <&lvts_e_data1>; + nvmem-cell-names =3D "lvts_calib_data1"; + }; + spi1: spi@11010000 { compatible =3D "mediatek,mt8192-spi", "mediatek,mt6765-spi"; @@ -1457,4 +1480,92 @@ larb2: larb@1f002000 { power-domains =3D <&spm MT8192_POWER_DOMAIN_MDP>; }; }; + + thermal_zones: thermal-zones { + cpu-big1-thermal { + polling-delay =3D <0>; + polling-delay-passive =3D <0>; + thermal-sensors =3D <&lvts_mcu 0>; + }; + cpu-big2-thermal { + polling-delay =3D <0>; + polling-delay-passive =3D <0>; + thermal-sensors =3D <&lvts_mcu 1>; + }; + cpu-big3-thermal { + polling-delay =3D <0>; + polling-delay-passive =3D <0>; + thermal-sensors =3D <&lvts_mcu 2>; + }; + cpu-big4-thermal { + polling-delay =3D <0>; + polling-delay-passive =3D <0>; + thermal-sensors =3D <&lvts_mcu 3>; + }; + cpu-little1-thermal { + polling-delay =3D <0>; + polling-delay-passive =3D <0>; + thermal-sensors =3D <&lvts_mcu 4>; + }; + cpu-little2-thermal { + polling-delay =3D <0>; + polling-delay-passive =3D <0>; + thermal-sensors =3D <&lvts_mcu 5>; + }; + cpu-little3-thermal { + polling-delay =3D <0>; + polling-delay-passive =3D <0>; + thermal-sensors =3D <&lvts_mcu 6>; + }; + cpu-little4-thermal { + polling-delay =3D <0>; + polling-delay-passive =3D <0>; + thermal-sensors =3D <&lvts_mcu 7>; + }; + vpu1-thermal { + polling-delay =3D <0>; + polling-delay-passive =3D <0>; + thermal-sensors =3D <&lvts_ap 0>; + }; + vpu2-thermal { + polling-delay =3D <0>; + polling-delay-passive =3D <0>; + thermal-sensors =3D <&lvts_ap 1>; + }; + gpu1-thermal { + polling-delay =3D <0>; + polling-delay-passive =3D <0>; + thermal-sensors =3D <&lvts_ap 2>; + }; + gpu2-thermal { + polling-delay =3D <0>; + polling-delay-passive =3D <0>; + thermal-sensors =3D <&lvts_ap 3>; + }; + vdec-thermal { + polling-delay =3D <0>; + polling-delay-passive =3D <0>; + thermal-sensors =3D <&lvts_ap 4>; + }; + img-thermal { + polling-delay =3D <0>; + polling-delay-passive =3D <0>; + thermal-sensors =3D <&lvts_ap 5>; + }; + infra-thermal { + polling-delay =3D <0>; + polling-delay-passive =3D <0>; + thermal-sensors =3D <&lvts_ap 6>; + }; + cam1-thermal { + polling-delay =3D <0>; + polling-delay-passive =3D <0>; + thermal-sensors =3D <&lvts_ap 7>; + }; + cam2-thermal { + polling-delay =3D <0>; + polling-delay-passive =3D <0>; + thermal-sensors =3D <&lvts_ap 8>; + }; + }; }; --=20 2.34.1