From nobody Sat Sep 21 23:07:55 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 81030C19F29 for ; Thu, 4 Aug 2022 02:17:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239355AbiHDCRL (ORCPT ); Wed, 3 Aug 2022 22:17:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45766 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238939AbiHDCQI (ORCPT ); Wed, 3 Aug 2022 22:16:08 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6CBAF5FAD8; Wed, 3 Aug 2022 19:16:06 -0700 (PDT) X-UUID: 6298e7916e3c4859a079db8cd19272e2-20220804 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=JACpGrS9uLsceVJJOi8hr5prYUoeV/OIr2JtZki3qlY=; b=DJxKbvC7RIsgndrqFV+/lwZQ7BK0nKV5wvOpk3VSwivsvtfUBFhplGDvW8c8A6e/5w0jkTk0PXLDtmavx11pkIy0Zmhri8rlI+ArFwhosJ/FptsigC6itb8gTyasq7ENSL6o21pY9m8BiVL4VCVskZSJN1m1GpEO9vqm5IbtfRY=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.8,REQID:57eea159-b20f-4ab5-b1ee-78e10979511c,OB:0,LO B:30,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,RULE:Release_Ham,AC TION:release,TS:95 X-CID-INFO: VERSION:1.1.8,REQID:57eea159-b20f-4ab5-b1ee-78e10979511c,OB:0,LOB: 30,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,RULE:Spam_GS981B3D,AC TION:quarantine,TS:95 X-CID-META: VersionHash:0f94e32,CLOUDID:79c03bd0-a6cf-4fb6-be1b-c60094821ca2,C OID:09443d6b6e07,Recheck:0,SF:28|17|19|48,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,QS:nil,BEC:nil,COL:0 X-UUID: 6298e7916e3c4859a079db8cd19272e2-20220804 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 786767242; Thu, 04 Aug 2022 10:15:58 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Thu, 4 Aug 2022 10:15:56 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 4 Aug 2022 10:15:56 +0800 From: Tinghan Shen To: Yong Wu , Joerg Roedel , Will Deacon , Robin Murphy , Rob Herring , Krzysztof Kozlowski , Lee Jones , Matthias Brugger , AngeloGioacchino Del Regno , Tinghan Shen , MandyJH Liu CC: , , , , , Subject: [PATCH v5 11/20] arm64: dts: mt8195: Add vdosys and vppsys clock nodes Date: Thu, 4 Aug 2022 10:15:44 +0800 Message-ID: <20220804021553.14867-12-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220804021553.14867-1-tinghan.shen@mediatek.com> References: <20220804021553.14867-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add display clock nodes. Signed-off-by: Tinghan Shen Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 900aaa16f862f..8d59a7da32714 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -983,6 +983,12 @@ #clock-cells =3D <1>; }; =20 + vppsys0: clock-controller@14000000 { + compatible =3D "mediatek,mt8195-vppsys0"; + reg =3D <0 0x14000000 0 0x1000>; + #clock-cells =3D <1>; + }; + wpesys: clock-controller@14e00000 { compatible =3D "mediatek,mt8195-wpesys"; reg =3D <0 0x14e00000 0 0x1000>; @@ -1001,6 +1007,12 @@ #clock-cells =3D <1>; }; =20 + vppsys1: clock-controller@14f00000 { + compatible =3D "mediatek,mt8195-vppsys1"; + reg =3D <0 0x14f00000 0 0x1000>; + #clock-cells =3D <1>; + }; + imgsys: clock-controller@15000000 { compatible =3D "mediatek,mt8195-imgsys"; reg =3D <0 0x15000000 0 0x1000>; @@ -1108,5 +1120,17 @@ reg =3D <0 0x1b000000 0 0x1000>; #clock-cells =3D <1>; }; + + vdosys0: syscon@1c01a000 { + compatible =3D "mediatek,mt8195-mmsys", "syscon"; + reg =3D <0 0x1c01a000 0 0x1000>; + #clock-cells =3D <1>; + }; + + vdosys1: syscon@1c100000 { + compatible =3D "mediatek,mt8195-mmsys", "syscon"; + reg =3D <0 0x1c100000 0 0x1000>; + #clock-cells =3D <1>; + }; }; }; --=20 2.18.0