From nobody Sun Apr 12 00:54:30 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6A7EBC19F2B for ; Wed, 3 Aug 2022 22:50:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238600AbiHCWuR (ORCPT ); Wed, 3 Aug 2022 18:50:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37184 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238388AbiHCWuJ (ORCPT ); Wed, 3 Aug 2022 18:50:09 -0400 Received: from mail-yw1-x114a.google.com (mail-yw1-x114a.google.com [IPv6:2607:f8b0:4864:20::114a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4483A481F0 for ; Wed, 3 Aug 2022 15:50:08 -0700 (PDT) Received: by mail-yw1-x114a.google.com with SMTP id 00721157ae682-3238ce833beso137893357b3.11 for ; Wed, 03 Aug 2022 15:50:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:reply-to:from:to:cc; bh=SPa2O+7Mze0bsq8ap8FmcbiFuFSXZGJKxHFkzvC7sT8=; b=mDV2yaRQ40EVKU/eNX/FCSCMbrm3jI3NTGk+xe5bhVD9DzGKwvGcHuXotUJbowBoaE cjVjtTKgs+CH4nn/bvEP5KVZaboce2sBNMMbfqK5N22Xgtj95BsewTqXyj4tixPlQBbJ l3adCyQl/4S9dz7hR29gXjSqueoATUfHAqSZEJPnLhsA3taMs/cB89DrBOigZpQjNgqp A9NALz2pEEzsY/k8KKqZ2eld7+xe8ZT32e4cDLzMxXjPhEDbyrIB4WACv4XOGoNX8mlK Rak3qAyp2O3eDEn9wVvJq8MXcgd95xZKoXMARo54eAS1dPnbfMTY8jfp1AGf8mI69jRP hofQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:reply-to:x-gm-message-state:from:to:cc; bh=SPa2O+7Mze0bsq8ap8FmcbiFuFSXZGJKxHFkzvC7sT8=; b=SHBq8Dd7KFLQWJ5FqqnkeW95POL/B85JCKHzQ/omMNDkQuk6/f7IUpE2ayRZ7frdzk S6Y3OwL4GUqT7bTTlbUrrv0h+mRZexX340qcE84f2peP6/6nPeqluAc57KDRxgj87Usn 7YvU5m5vfAwboQaCJXDWhNlGLQ52jwD8dBr27LPxYJ8q5K97o9WZrTY/Vk6o0D1psL9Z HpULBgpaZthBAYsmQVtY6WG6miXuc3TzQk9bOUszw4+Lrf0AiW4DO7+r+jMlyKKL/Yyr X7u6mGlu+/ECUl4AWqcxGxR3cT0KhCUTGR3sO1HyIqTAt7mPaRNAN/W4RSHOE/XMn4yu CA6Q== X-Gm-Message-State: ACgBeo0+u812B0ybCpxpsqaigvIA5ddwkJWaAvh64YZyDmcRqJJJ0RfQ vLnyAUMNwcU3mhupQSCnAY5c2X+da3s= X-Google-Smtp-Source: AA6agR4vvYuZchZorwqNL4ADWM2SVsdXLpazfIk0/fo45JEQlQw8DGJMrYjsMUzBSUry6w5MQIFt772ped0= X-Received: from zagreus.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:5c37]) (user=seanjc job=sendgmr) by 2002:a25:7a82:0:b0:671:6802:fb8d with SMTP id v124-20020a257a82000000b006716802fb8dmr20992881ybc.224.1659567007526; Wed, 03 Aug 2022 15:50:07 -0700 (PDT) Reply-To: Sean Christopherson Date: Wed, 3 Aug 2022 22:49:57 +0000 In-Reply-To: <20220803224957.1285926-1-seanjc@google.com> Message-Id: <20220803224957.1285926-4-seanjc@google.com> Mime-Version: 1.0 References: <20220803224957.1285926-1-seanjc@google.com> X-Mailer: git-send-email 2.37.1.559.g78731f0fdb-goog Subject: [PATCH v2 3/3] KVM: SVM: Disable SEV-ES support if MMIO caching is disable From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Kai Huang , Michael Roth , Tom Lendacky Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Disable SEV-ES if MMIO caching is disabled as SEV-ES relies on MMIO SPTEs generating #NPF(RSVD), which are reflected by the CPU into the guest as a #VC. With SEV-ES, the untrusted host, a.k.a. KVM, doesn't have access to the guest instruction stream or register state and so can't directly emulate in response to a #NPF on an emulated MMIO GPA. Disabling MMIO caching means guest accesses to emulated MMIO ranges cause #NPF(!PRESENT), and those flavors of #NPF cause automatic VM-Exits, not #VC. Adjust KVM's MMIO masks to account for the C-bit location prior to doing SEV(-ES) setup, and document that dependency between adjusting the MMIO SPTE mask and SEV(-ES) setup. Fixes: b09763da4dd8 ("KVM: x86/mmu: Add module param to disable MMIO cachin= g (for testing)") Reported-by: Michael Roth Tested-by: Michael Roth Cc: Tom Lendacky Cc: stable@vger.kernel.org Signed-off-by: Sean Christopherson --- arch/x86/kvm/mmu.h | 2 ++ arch/x86/kvm/mmu/spte.c | 1 + arch/x86/kvm/mmu/spte.h | 2 -- arch/x86/kvm/svm/sev.c | 10 ++++++++++ arch/x86/kvm/svm/svm.c | 9 ++++++--- 5 files changed, 19 insertions(+), 5 deletions(-) diff --git a/arch/x86/kvm/mmu.h b/arch/x86/kvm/mmu.h index a99acec925eb..6bdaacb6faa0 100644 --- a/arch/x86/kvm/mmu.h +++ b/arch/x86/kvm/mmu.h @@ -6,6 +6,8 @@ #include "kvm_cache_regs.h" #include "cpuid.h" =20 +extern bool __read_mostly enable_mmio_caching; + #define PT_WRITABLE_SHIFT 1 #define PT_USER_SHIFT 2 =20 diff --git a/arch/x86/kvm/mmu/spte.c b/arch/x86/kvm/mmu/spte.c index 66f76f5a15bd..03ca740bf721 100644 --- a/arch/x86/kvm/mmu/spte.c +++ b/arch/x86/kvm/mmu/spte.c @@ -22,6 +22,7 @@ bool __read_mostly enable_mmio_caching =3D true; static bool __ro_after_init allow_mmio_caching; module_param_named(mmio_caching, enable_mmio_caching, bool, 0444); +EXPORT_SYMBOL_GPL(enable_mmio_caching); =20 u64 __read_mostly shadow_host_writable_mask; u64 __read_mostly shadow_mmu_writable_mask; diff --git a/arch/x86/kvm/mmu/spte.h b/arch/x86/kvm/mmu/spte.h index 26b144ffd146..9a9414b8d1d6 100644 --- a/arch/x86/kvm/mmu/spte.h +++ b/arch/x86/kvm/mmu/spte.h @@ -5,8 +5,6 @@ =20 #include "mmu_internal.h" =20 -extern bool __read_mostly enable_mmio_caching; - /* * A MMU present SPTE is backed by actual memory and may or may not be pre= sent * in hardware. E.g. MMIO SPTEs are not considered present. Use bit 11, = as it diff --git a/arch/x86/kvm/svm/sev.c b/arch/x86/kvm/svm/sev.c index b0e793e7d85c..28064060413a 100644 --- a/arch/x86/kvm/svm/sev.c +++ b/arch/x86/kvm/svm/sev.c @@ -22,6 +22,7 @@ #include #include =20 +#include "mmu.h" #include "x86.h" #include "svm.h" #include "svm_ops.h" @@ -2221,6 +2222,15 @@ void __init sev_hardware_setup(void) if (!sev_es_enabled) goto out; =20 + /* + * SEV-ES requires MMIO caching as KVM doesn't have access to the guest + * instruction stream, i.e. can't emulate in response to a #NPF and + * instead relies on #NPF(RSVD) being reflected into the guest as #VC + * (the guest can then do a #VMGEXIT to request MMIO emulation). + */ + if (!enable_mmio_caching) + goto out; + /* Does the CPU support SEV-ES? */ if (!boot_cpu_has(X86_FEATURE_SEV_ES)) goto out; diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index 38f873cb6f2c..f3813dbacb9f 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -5034,13 +5034,16 @@ static __init int svm_hardware_setup(void) /* Setup shadow_me_value and shadow_me_mask */ kvm_mmu_set_me_spte_mask(sme_me_mask, sme_me_mask); =20 - /* Note, SEV setup consumes npt_enabled. */ + svm_adjust_mmio_mask(); + + /* + * Note, SEV setup consumes npt_enabled and enable_mmio_caching (which + * may be modified by svm_adjust_mmio_mask()). + */ sev_hardware_setup(); =20 svm_hv_hardware_setup(); =20 - svm_adjust_mmio_mask(); - for_each_possible_cpu(cpu) { r =3D svm_cpu_init(cpu); if (r) --=20 2.37.1.559.g78731f0fdb-goog