From nobody Sun Apr 12 04:21:18 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 53A8DC19F28 for ; Wed, 3 Aug 2022 10:27:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237685AbiHCK1u (ORCPT ); Wed, 3 Aug 2022 06:27:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34984 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237923AbiHCK11 (ORCPT ); Wed, 3 Aug 2022 06:27:27 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B29D13F31A; Wed, 3 Aug 2022 03:27:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1659522428; x=1691058428; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=9cakn4tlvPI+qogjOzCeScbPuMLwF4m8+0rQKisSsCQ=; b=BDdyRGsgLqjfnUNOW8An+dGeBVUeYtjF04G0cm+4PReowcvmDA3ZGIKq bvkNVC9JnHPIpSp1kkiTW3FCIxRmBblRO//Rf13rt1nftguziPuju6gvG SUX1umrJJVZlsSvwlvWAiEtNsna5ewgjri4ggVTmuex76CwbIWo/g5uqE 3JUvNDGt3WnqR3dVJbdTP+4s8KFXVJ9McWXtFaOts0RpU6m2TXoFQKLxi JM7WMF2fmpcCtpzG4I9ZoSzJQwP7v+ET95jKEBk0cwoQe6Swi4pBNKMj8 LlkkU6KOiA1A+WxxR/tb8BeYVej4LqMSb9j2QlYUcLZFjS0Dm93LCp4i6 A==; X-IronPort-AV: E=Sophos;i="5.93,214,1654585200"; d="scan'208";a="107364746" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 03 Aug 2022 03:27:07 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Wed, 3 Aug 2022 03:27:06 -0700 Received: from localhost.localdomain (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2375.28 via Frontend Transport; Wed, 3 Aug 2022 03:27:03 -0700 From: Claudiu Beznea To: , , , , , , CC: , , , , Claudiu Beznea Subject: [PATCH v3 09/19] iio: adc: at91-sama5d2_adc: add .read_avail() chan_info ops Date: Wed, 3 Aug 2022 13:28:45 +0300 Message-ID: <20220803102855.2191070-10-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220803102855.2191070-1-claudiu.beznea@microchip.com> References: <20220803102855.2191070-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add .read_avail() to chan_info ops which will retrieve the available oversampling ratio. Suggested-by: Jonathan Cameron Signed-off-by: Claudiu Beznea --- drivers/iio/adc/at91-sama5d2_adc.c | 50 +++++++++++++++++++++--------- 1 file changed, 35 insertions(+), 15 deletions(-) diff --git a/drivers/iio/adc/at91-sama5d2_adc.c b/drivers/iio/adc/at91-sama= 5d2_adc.c index fe4bec03bea9..47caaf271fae 100644 --- a/drivers/iio/adc/at91-sama5d2_adc.c +++ b/drivers/iio/adc/at91-sama5d2_adc.c @@ -319,6 +319,8 @@ static const struct at91_adc_reg_layout sama7g5_layout = =3D { .info_mask_shared_by_type =3D BIT(IIO_CHAN_INFO_SCALE), \ .info_mask_shared_by_all =3D BIT(IIO_CHAN_INFO_SAMP_FREQ)|\ BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ + .info_mask_shared_by_all_available =3D \ + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ .datasheet_name =3D "CH"#num, \ .indexed =3D 1, \ } @@ -340,6 +342,8 @@ static const struct at91_adc_reg_layout sama7g5_layout = =3D { .info_mask_shared_by_type =3D BIT(IIO_CHAN_INFO_SCALE), \ .info_mask_shared_by_all =3D BIT(IIO_CHAN_INFO_SAMP_FREQ)|\ BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ + .info_mask_shared_by_all_available =3D \ + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ .datasheet_name =3D "CH"#num"-CH"#num2, \ .indexed =3D 1, \ } @@ -359,6 +363,8 @@ static const struct at91_adc_reg_layout sama7g5_layout = =3D { .info_mask_separate =3D BIT(IIO_CHAN_INFO_RAW), \ .info_mask_shared_by_all =3D BIT(IIO_CHAN_INFO_SAMP_FREQ)|\ BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ + .info_mask_shared_by_all_available =3D \ + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ .datasheet_name =3D name, \ } #define AT91_SAMA5D2_CHAN_PRESSURE(num, name) \ @@ -374,6 +380,8 @@ static const struct at91_adc_reg_layout sama7g5_layout = =3D { .info_mask_separate =3D BIT(IIO_CHAN_INFO_RAW), \ .info_mask_shared_by_all =3D BIT(IIO_CHAN_INFO_SAMP_FREQ)|\ BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ + .info_mask_shared_by_all_available =3D \ + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ .datasheet_name =3D name, \ } =20 @@ -398,6 +406,8 @@ static const struct at91_adc_reg_layout sama7g5_layout = =3D { * than the total channel number) * @hw_trig_cnt: number of possible hardware triggers * @osr_mask: oversampling ratio bitmask on EMR register + * @oversampling_avail: available oversampling values + * @oversampling_avail_no: number of available oversampling values */ struct at91_adc_platform { const struct at91_adc_reg_layout *layout; @@ -410,6 +420,8 @@ struct at91_adc_platform { unsigned int max_index; unsigned int hw_trig_cnt; unsigned int osr_mask; + unsigned int oversampling_avail[3]; + unsigned int oversampling_avail_no; }; =20 /** @@ -609,6 +621,8 @@ static const struct at91_adc_platform sama5d2_platform = =3D { #define AT91_SAMA5D2_HW_TRIG_CNT 3 .hw_trig_cnt =3D AT91_SAMA5D2_HW_TRIG_CNT, .osr_mask =3D GENMASK(17, 16), + .oversampling_avail =3D { 1, 4, 16, }, + .oversampling_avail_no =3D 3, }; =20 static const struct at91_adc_platform sama7g5_platform =3D { @@ -625,6 +639,8 @@ static const struct at91_adc_platform sama7g5_platform = =3D { #define AT91_SAMA7G5_HW_TRIG_CNT 3 .hw_trig_cnt =3D AT91_SAMA7G5_HW_TRIG_CNT, .osr_mask =3D GENMASK(18, 16), + .oversampling_avail =3D { 1, 4, 16, }, + .oversampling_avail_no =3D 3, }; =20 static int at91_adc_chan_xlate(struct iio_dev *indio_dev, int chan) @@ -1682,6 +1698,24 @@ static int at91_adc_write_raw(struct iio_dev *indio_= dev, } } =20 +static int at91_adc_read_avail(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + const int **vals, int *type, int *length, + long mask) +{ + struct at91_adc_state *st =3D iio_priv(indio_dev); + + switch (mask) { + case IIO_CHAN_INFO_OVERSAMPLING_RATIO: + *vals =3D (int *)st->soc_info.platform->oversampling_avail; + *type =3D IIO_VAL_INT; + *length =3D st->soc_info.platform->oversampling_avail_no; + return IIO_AVAIL_LIST; + default: + return -EINVAL; + } +} + static void at91_adc_dma_init(struct at91_adc_state *st) { struct device *dev =3D &st->indio_dev->dev; @@ -1869,20 +1903,6 @@ static IIO_DEVICE_ATTR(hwfifo_watermark, 0444, static IIO_CONST_ATTR(hwfifo_watermark_min, "2"); static IIO_CONST_ATTR(hwfifo_watermark_max, AT91_HWFIFO_MAX_SIZE_STR); =20 -static IIO_CONST_ATTR(oversampling_ratio_available, - __stringify(1) " " - __stringify(4) " " - __stringify(16)); - -static struct attribute *at91_adc_attributes[] =3D { - &iio_const_attr_oversampling_ratio_available.dev_attr.attr, - NULL, -}; - -static const struct attribute_group at91_adc_attribute_group =3D { - .attrs =3D at91_adc_attributes, -}; - static const struct attribute *at91_adc_fifo_attributes[] =3D { &iio_const_attr_hwfifo_watermark_min.dev_attr.attr, &iio_const_attr_hwfifo_watermark_max.dev_attr.attr, @@ -1892,7 +1912,7 @@ static const struct attribute *at91_adc_fifo_attribut= es[] =3D { }; =20 static const struct iio_info at91_adc_info =3D { - .attrs =3D &at91_adc_attribute_group, + .read_avail =3D &at91_adc_read_avail, .read_raw =3D &at91_adc_read_raw, .write_raw =3D &at91_adc_write_raw, .update_scan_mode =3D &at91_adc_update_scan_mode, --=20 2.34.1