From nobody Sun Apr 12 02:46:49 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 247BDC00144 for ; Mon, 1 Aug 2022 13:16:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231745AbiHANQL (ORCPT ); Mon, 1 Aug 2022 09:16:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47766 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230202AbiHANQH (ORCPT ); Mon, 1 Aug 2022 09:16:07 -0400 Received: from mail.fris.de (mail.fris.de [116.203.77.234]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8E6512B265; Mon, 1 Aug 2022 06:16:05 -0700 (PDT) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 7AE05C01B2; Mon, 1 Aug 2022 15:16:01 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fris.de; s=dkim; t=1659359763; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=EvDIWgGGFv0dTGHx3tYvYz7xpwXiwSm00vavKsPFV3Y=; b=obDUdM6Vkpe6QoBH6/m6GEV5mMxg0lGFjtT07gSiov3zBVNDhpdws4E5hSXXeXbC1e+AND BQzau/fcSKuvZpsk1DvZOreD0aFQgpDlRRvyO3SedmX98xMrAV1Ru4+bfMqAKWNrsNKWBd AaF3dOyxFVzDiKtMe6E93BMqXI295awqmyu9G9KpH9NOpZOvknBE0qxtOuN49+kX0B5eyU w1En35OKRXnlRMb0OT3YNmTjY15H5kK8mThx0hsIhuNDAqgyqBt3jYC8VHuF/GjNUtyjE5 2CjkKKrp72e63W+V0Q+ONcStiImD1xEVby5pNiueZLbjNkV0ozej6QYQav4hbg== From: Frieder Schrempf To: devicetree@vger.kernel.org, Krzysztof Kozlowski , linux-kernel@vger.kernel.org, Li Yang , Rob Herring , Shawn Guo Cc: Fabio Estevam , linux-arm-kernel@lists.infradead.org, Frieder Schrempf , Krzysztof Kozlowski , Alexander Stein , "Ariel D'Alessandro" , Denys Drozdov , Fabio Estevam , Marcel Ziswiler , Marek Vasut , Matthias Schiffer , Max Krummenacher , Rob Herring , Tim Harvey Subject: [PATCH v2 1/8] dt-bindings: arm: fsl: Add Kontron BL i.MX8MM OSM-S board Date: Mon, 1 Aug 2022 15:15:45 +0200 Message-Id: <20220801131554.116795-2-frieder@fris.de> In-Reply-To: <20220801131554.116795-1-frieder@fris.de> References: <20220801131554.116795-1-frieder@fris.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Frieder Schrempf Add bindings for the Kontron BL i.MX8MM OSM-S board. Signed-off-by: Frieder Schrempf Acked-by: Krzysztof Kozlowski --- Changes in v2: * add A-b tag from Krzysztof (Thanks!) --- Documentation/devicetree/bindings/arm/fsl.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation= /devicetree/bindings/arm/fsl.yaml index ef524378d449..ef99d948e908 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -847,6 +847,12 @@ properties: - const: kontron,imx8mm-n801x-som - const: fsl,imx8mm =20 + - description: Kontron BL i.MX8MM OSM-S (N802X S) Board + items: + - const: kontron,imx8mm-n802x-s + - const: kontron,imx8mm-n802x-som + - const: fsl,imx8mm + - description: Toradex Boards with Verdin iMX8M Mini Modules items: - enum: --=20 2.37.1 From nobody Sun Apr 12 02:46:49 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8D410C00144 for ; Mon, 1 Aug 2022 13:16:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231926AbiHANQO (ORCPT ); Mon, 1 Aug 2022 09:16:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47776 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230203AbiHANQI (ORCPT ); Mon, 1 Aug 2022 09:16:08 -0400 Received: from mail.fris.de (mail.fris.de [IPv6:2a01:4f8:c2c:390b::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5FBAA2B267; Mon, 1 Aug 2022 06:16:06 -0700 (PDT) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 79084C01B3; Mon, 1 Aug 2022 15:16:04 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fris.de; s=dkim; t=1659359765; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=dDXHjR+rY6x+7wr/ZTif7aTyQ06P/cqOLoN75cSeQSE=; b=X9iZc0Z4Au8xcwh5BGUVPUeW3PFbUuPS4d/S5zwhSWxhWC5VKweWWKXGBzI7A65c6IRDgy 6TQ0cf/rOvjHbEN77cEfasgFG01SYcqEKtu+/gR57QoPPFejxE9vauR5Sm5b5RiqW8ZDaT /2LMfY2ThnJP92ws7h7vl01KtjARfxejAigX+2bTAxTbPxtZZnEaTBBw75/R2CPw2C+K9Z CV9SO0ofCusjMwa7wEf359uxwD/s5DUJUrauAbYSL47KJN7Hp0JgQSzYQ+cITi9XntYZDi F7/FV/hTKL1EwCa0yCU4s2lvQeXXzYTJvbNjo+egk621ozMcefkHdwaqfPvv1g== From: Frieder Schrempf To: devicetree@vger.kernel.org, Krzysztof Kozlowski , Liam Girdwood , linux-kernel@vger.kernel.org, Mark Brown , Rob Herring , Robin Gong Cc: Fabio Estevam , linux-arm-kernel@lists.infradead.org, Frieder Schrempf , Per-Daniel Olsson , Rickard x Andersson Subject: [PATCH v2 2/8] dt-bindings: regulator: pca9450: Allow arbitrary regulator names Date: Mon, 1 Aug 2022 15:15:46 +0200 Message-Id: <20220801131554.116795-3-frieder@fris.de> In-Reply-To: <20220801131554.116795-1-frieder@fris.de> References: <20220801131554.116795-1-frieder@fris.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Frieder Schrempf Instead of restricting regulator-name to non-descriptive names, allow to use arbitrary strings. This enables us to use the name of the voltage rail that is powered by the regulator as some board DTs already do. Signed-off-by: Frieder Schrempf --- Changes in v2: * new patch --- .../bindings/regulator/nxp,pca9450-regulator.yaml | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/regulator/nxp,pca9450-regula= tor.yaml b/Documentation/devicetree/bindings/regulator/nxp,pca9450-regulato= r.yaml index b539781e39aa..b1e4fd09928b 100644 --- a/Documentation/devicetree/bindings/regulator/nxp,pca9450-regulator.yaml +++ b/Documentation/devicetree/bindings/regulator/nxp,pca9450-regulator.yaml @@ -49,9 +49,9 @@ properties: =20 properties: regulator-name: - pattern: "^LDO[1-5]$" description: - should be "LDO1", ..., "LDO5" + Should be "LDO1", ..., "LDO5" or whatever the name of the bo= ards + voltage rail powered by this regulator is. =20 unevaluatedProperties: false =20 @@ -63,9 +63,9 @@ properties: =20 properties: regulator-name: - pattern: "^BUCK[1-6]$" description: - should be "BUCK1", ..., "BUCK6" + Should be "BUCK1", ..., "BUCK6" or whatever the name of the = boards + voltage rail powered by this regulator is. =20 nxp,dvs-run-voltage: $ref: "/schemas/types.yaml#/definitions/uint32" --=20 2.37.1 From nobody Sun Apr 12 02:46:49 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0E521C19F29 for ; Mon, 1 Aug 2022 13:16:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231815AbiHANQU (ORCPT ); Mon, 1 Aug 2022 09:16:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47866 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231814AbiHANQL (ORCPT ); Mon, 1 Aug 2022 09:16:11 -0400 Received: from mail.fris.de (mail.fris.de [IPv6:2a01:4f8:c2c:390b::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 395062B26E; Mon, 1 Aug 2022 06:16:09 -0700 (PDT) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id A38D4C01B5; Mon, 1 Aug 2022 15:16:06 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fris.de; s=dkim; t=1659359767; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=ibTdyKFj8P0BuRvMeMNwN6K/pbZ2SGY2V9Kqxo+bbC0=; b=uX2pZnU3cjvu8YT6x3oPKmDewPet1ZJ2cDt7lizZ7Sw+HNPP3WzVoFUJ42Ndml/m2PCE// hrgR9tCz8rtjh/OFDIdYr1jMZ4I9xVMP3ckjhy+5UutgsjxpTNyt1pn6SnmBlMQhht7RUN YU2GysQ/jzE4PWQT3Sp0jUZ6l8uKeifjOpojPB68QW+QtIrVD12sHoR7ss/OsY5KK6gjk6 quA5qWe1A5H9QlKHpR7IKC+wIzdmHY016al8tbJN0Ps2f9Ft0ukD6nwD38x3eqCqHPPKk1 ZNjt7uY0U22fS4F9pqoTO8B41m0MuT7Wz+FHR97Y9KUPaXZ4/kb7aBgbCA+lOg== From: Frieder Schrempf To: devicetree@vger.kernel.org, Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rob Herring , Sascha Hauer , Shawn Guo Cc: Fabio Estevam , Frieder Schrempf , Heiko Thiery , Krzysztof Kozlowski , NXP Linux Team , Oleksij Rempel , Pengutronix Kernel Team Subject: [PATCH v2 3/8] arm64: dts: imx8mm-kontron: Adjust board and SoM model strings Date: Mon, 1 Aug 2022 15:15:47 +0200 Message-Id: <20220801131554.116795-4-frieder@fris.de> In-Reply-To: <20220801131554.116795-1-frieder@fris.de> References: <20220801131554.116795-1-frieder@fris.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Frieder Schrempf The official naming includes "SL" (SoM-Line) or "BL" (Board-Line). The legacy identifiers are kept in brackets and are still used in file names and compatible strings. Signed-off-by: Frieder Schrempf --- Changes in v2: * none --- arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-s.dts | 2 +- arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-s.dts b/arc= h/arm64/boot/dts/freescale/imx8mm-kontron-n801x-s.dts index 23be1ec538ba..cb8102bb8db5 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-s.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-s.dts @@ -8,7 +8,7 @@ #include "imx8mm-kontron-n801x-som.dtsi" =20 / { - model =3D "Kontron i.MX8MM N801X S"; + model =3D "Kontron BL i.MX8MM (N801X)"; compatible =3D "kontron,imx8mm-n801x-s", "kontron,imx8mm-n801x-som", "fsl= ,imx8mm"; =20 aliases { diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi b/= arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi index 8f90eb02550d..b6d90d646a5f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi @@ -6,7 +6,7 @@ #include "imx8mm.dtsi" =20 / { - model =3D "Kontron i.MX8MM N801X SoM"; + model =3D "Kontron SL i.MX8MM (N801X)"; compatible =3D "kontron,imx8mm-n801x-som", "fsl,imx8mm"; =20 memory@40000000 { --=20 2.37.1 From nobody Sun Apr 12 02:46:49 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 587CFC19F29 for ; Mon, 1 Aug 2022 13:16:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232123AbiHANQY (ORCPT ); Mon, 1 Aug 2022 09:16:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48244 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231509AbiHANQS (ORCPT ); Mon, 1 Aug 2022 09:16:18 -0400 Received: from mail.fris.de (mail.fris.de [IPv6:2a01:4f8:c2c:390b::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ED5322C10E; Mon, 1 Aug 2022 06:16:11 -0700 (PDT) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id DD187C01C1; Mon, 1 Aug 2022 15:16:08 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fris.de; s=dkim; t=1659359769; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=uEhwV847uQ4J0YX9XnJNc7BuGq20ipcYeJhXwV8hGfQ=; b=rJIHRllQZmD6WLYndAzI53c6VELbAIE/0yYoV4fKu9yLcpXeWhHgFSuvnR+aGNx46Sxo/W VgEIknyFuEFzO+djnNedHDYTyvZxejWR6LmU7FI/1ITc6ux98BLb9xp8DWzslYSQ6bR4cM 2laySzagDfl6um3sqLSS8oG9N0mwB0gUCKqOixFxRLQvbLCiwatTs58A6f1o2g/q+zb7CD lAmOGM+vuL9GHGjWZiQA+ryruO6RFsntB7YjoPysg5/i3phGPYb42/gKjdYvaj47ToDoB/ 666vZL4yk1ENZUBadWm83M1yqBvj64ugUEY2Z8c0VasSFbNL7v5Q3Xdcixo4UQ== From: Frieder Schrempf To: devicetree@vger.kernel.org, Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rob Herring , Sascha Hauer , Shawn Guo Cc: Fabio Estevam , Frieder Schrempf , Heiko Thiery , Krzysztof Kozlowski , NXP Linux Team , Oleksij Rempel , Pengutronix Kernel Team Subject: [PATCH v2 4/8] arm64: dts: imx8mm-kontron: Use the VSELECT signal to switch SD card IO voltage Date: Mon, 1 Aug 2022 15:15:48 +0200 Message-Id: <20220801131554.116795-5-frieder@fris.de> In-Reply-To: <20220801131554.116795-1-frieder@fris.de> References: <20220801131554.116795-1-frieder@fris.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Frieder Schrempf It turns out that it is not necessary to declare the VSELECT signal as GPIO and let the PMIC driver set it to a fixed high level. This switches the voltage between 3.3V and 1.8V by setting the PMIC register for LDO5 accordingly. Instead we can do it like other boards already do and simply mux the VSELECT signal of the USDHC interface to the pin. This makes sure that the correct voltage is selected by setting the PMIC's SD_VSEL input to high or low accordingly. Reported-by: Heiko Thiery Signed-off-by: Frieder Schrempf Reviewed-by: Heiko Thiery --- Changes in v2: * Add Heiko's R-b tag (Thanks!) --- arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-s.dts | 3 +++ arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi | 2 -- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-s.dts b/arc= h/arm64/boot/dts/freescale/imx8mm-kontron-n801x-s.dts index cb8102bb8db5..bc46426ad8f6 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-s.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-s.dts @@ -321,6 +321,7 @@ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 >; }; =20 @@ -333,6 +334,7 @@ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 >; }; =20 @@ -345,6 +347,7 @@ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 >; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi b/= arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi index b6d90d646a5f..77c074b491a6 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi @@ -86,7 +86,6 @@ pca9450: pmic@25 { pinctrl-0 =3D <&pinctrl_pmic>; interrupt-parent =3D <&gpio1>; interrupts =3D <0 IRQ_TYPE_LEVEL_LOW>; - sd-vsel-gpios =3D <&gpio1 4 GPIO_ACTIVE_HIGH>; =20 regulators { reg_vdd_soc: BUCK1 { @@ -229,7 +228,6 @@ MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 pinctrl_pmic: pmicgrp { fsl,pins =3D < MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x141 - MX8MM_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x141 >; }; =20 --=20 2.37.1 From nobody Sun Apr 12 02:46:49 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C7562C00144 for ; Mon, 1 Aug 2022 13:16:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232549AbiHANQ1 (ORCPT ); Mon, 1 Aug 2022 09:16:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48272 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232010AbiHANQT (ORCPT ); Mon, 1 Aug 2022 09:16:19 -0400 Received: from mail.fris.de (mail.fris.de [116.203.77.234]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EA5B02CC8B; Mon, 1 Aug 2022 06:16:12 -0700 (PDT) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 7FEB4C01C2; Mon, 1 Aug 2022 15:16:10 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fris.de; s=dkim; t=1659359771; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=1Vq+dWeAn9HBzxJo1vPF2gxJMteCwjIli7Ab5hcGzkE=; b=T5yYgTmwz6ia7FHp8jnxg6j4aHaDhIshr6oTHEAg3+1gigsnTkcxVH+fhGzUKUO7NdzWhI 6dtULpYHtjnFdfxzP4cdIeqR3Pzruq4ZbqzH1J64J30jj1gzIRLDjuHd6bBpBr/3uDbg8B 2JeUlUaDg2sw/jjA6VauOhJkjR7DsSZbbXc8a92mDK2zEyw2V2M6f2Zxa1n2xZS1ck/l+D YEDtadJSw7pddiQ+AOFc9tMiX+xb2fOip29EKlsK6DZ729qwk+P5Xc0a+RhybOqoNstSpq E9LZkblqphXIio8INDplrqpmS6ZGbXlSw7JU4rSG37AVyHvyV+iE3aYF5cfaoA== From: Frieder Schrempf To: devicetree@vger.kernel.org, Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rob Herring , Sascha Hauer , Shawn Guo Cc: Fabio Estevam , Frieder Schrempf , Heiko Thiery , Krzysztof Kozlowski , NXP Linux Team , Pengutronix Kernel Team Subject: [PATCH v2 5/8] arm64: dts: imx8mm-kontron: Remove low DDRC operating point Date: Mon, 1 Aug 2022 15:15:49 +0200 Message-Id: <20220801131554.116795-6-frieder@fris.de> In-Reply-To: <20220801131554.116795-1-frieder@fris.de> References: <20220801131554.116795-1-frieder@fris.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Frieder Schrempf For some reason there is a problem with finding a DDR configuration that works on all operating points and all LPDDR4 types used on the SoM. Therefore the bootloader currently doesn't configure the lowest of the three operating points. Let's also skip this in the kernel devicetree to make sure it isn't used. Signed-off-by: Frieder Schrempf --- Changes in v2: * none --- arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi b/= arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi index 77c074b491a6..2d0661cce89b 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi @@ -46,10 +46,6 @@ &ddrc { ddrc_opp_table: opp-table { compatible =3D "operating-points-v2"; =20 - opp-25M { - opp-hz =3D /bits/ 64 <25000000>; - }; - opp-100M { opp-hz =3D /bits/ 64 <100000000>; }; --=20 2.37.1 From nobody Sun Apr 12 02:46:49 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7C81BC00144 for ; Mon, 1 Aug 2022 13:16:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231867AbiHANQc (ORCPT ); Mon, 1 Aug 2022 09:16:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48328 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232225AbiHANQU (ORCPT ); Mon, 1 Aug 2022 09:16:20 -0400 Received: from mail.fris.de (mail.fris.de [116.203.77.234]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 99E0A2DAA2; Mon, 1 Aug 2022 06:16:14 -0700 (PDT) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 0B547C01C6; Mon, 1 Aug 2022 15:16:12 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fris.de; s=dkim; t=1659359772; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=p5psr6T+2z5S/p8G5n2WFznn5vhijxmnxdmilBVyBek=; b=N+lmgVg0PPlRHSNvdxtcVfnkYHdlEyjEkV4qzB3e+hcpomwxMBM6bRChNGcYFwSceOzTZ1 4CFGAoTD1dbQYUfG3494yrwbrw5Y5VXD9SJ4fu7iC0CVWTunlipkZTzSC3LV3vCe125GIb uJ/hqEViLPfnkvXGzOXTSf6sOdv69OfeFRCxM1+9PIF7D3i6cKFMlhtE7ZxBIM3k94uX7b i55ld2Nq0ny+iLr0nZKRFkOsPYvDqemqqKIwq/hXzvfGKPV2UgnttVDn9Aze21GJukhzPI 04G5Y02geQDh/o00BpdUPW68Utyo6s2WGdU2uRwDl+aUb3baKgpBv2fuDYP9sw== From: Frieder Schrempf To: devicetree@vger.kernel.org, Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rob Herring , Sascha Hauer , Shawn Guo Cc: Fabio Estevam , Frieder Schrempf , Heiko Thiery , Krzysztof Kozlowski , NXP Linux Team , Pengutronix Kernel Team Subject: [PATCH v2 6/8] arm64: dts: imx8mm-kontron: Use voltage rail names from schematic for PMIC regulator-names Date: Mon, 1 Aug 2022 15:15:50 +0200 Message-Id: <20220801131554.116795-7-frieder@fris.de> In-Reply-To: <20220801131554.116795-1-frieder@fris.de> References: <20220801131554.116795-1-frieder@fris.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Frieder Schrempf Improve the naming of the regulators to contain the voltage rail names from the schematic. Suggested-by: Heiko Thiery Signed-off-by: Frieder Schrempf --- Changes in v2: * new patch --- .../freescale/imx8mm-kontron-n801x-som.dtsi | 22 +++++++++---------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi b/= arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi index 2d0661cce89b..c995592981c2 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi @@ -85,7 +85,7 @@ pca9450: pmic@25 { =20 regulators { reg_vdd_soc: BUCK1 { - regulator-name =3D "buck1"; + regulator-name =3D "+0V8_VDD_SOC (BUCK1)"; regulator-min-microvolt =3D <800000>; regulator-max-microvolt =3D <850000>; regulator-boot-on; @@ -96,7 +96,7 @@ reg_vdd_soc: BUCK1 { }; =20 reg_vdd_arm: BUCK2 { - regulator-name =3D "buck2"; + regulator-name =3D "+0V9_VDD_ARM (BUCK2)"; regulator-min-microvolt =3D <850000>; regulator-max-microvolt =3D <950000>; regulator-boot-on; @@ -107,7 +107,7 @@ reg_vdd_arm: BUCK2 { }; =20 reg_vdd_dram: BUCK3 { - regulator-name =3D "buck3"; + regulator-name =3D "+0V9_VDD_DRAM&PU (BUCK3)"; regulator-min-microvolt =3D <850000>; regulator-max-microvolt =3D <950000>; regulator-boot-on; @@ -115,7 +115,7 @@ reg_vdd_dram: BUCK3 { }; =20 reg_vdd_3v3: BUCK4 { - regulator-name =3D "buck4"; + regulator-name =3D "+3V3 (BUCK4)"; regulator-min-microvolt =3D <3300000>; regulator-max-microvolt =3D <3300000>; regulator-boot-on; @@ -123,7 +123,7 @@ reg_vdd_3v3: BUCK4 { }; =20 reg_vdd_1v8: BUCK5 { - regulator-name =3D "buck5"; + regulator-name =3D "+1V8 (BUCK5)"; regulator-min-microvolt =3D <1800000>; regulator-max-microvolt =3D <1800000>; regulator-boot-on; @@ -131,7 +131,7 @@ reg_vdd_1v8: BUCK5 { }; =20 reg_nvcc_dram: BUCK6 { - regulator-name =3D "buck6"; + regulator-name =3D "+1V1_NVCC_DRAM (BUCK6)"; regulator-min-microvolt =3D <1100000>; regulator-max-microvolt =3D <1100000>; regulator-boot-on; @@ -139,7 +139,7 @@ reg_nvcc_dram: BUCK6 { }; =20 reg_nvcc_snvs: LDO1 { - regulator-name =3D "ldo1"; + regulator-name =3D "+1V8_NVCC_SNVS (LDO1)"; regulator-min-microvolt =3D <1800000>; regulator-max-microvolt =3D <1800000>; regulator-boot-on; @@ -147,7 +147,7 @@ reg_nvcc_snvs: LDO1 { }; =20 reg_vdd_snvs: LDO2 { - regulator-name =3D "ldo2"; + regulator-name =3D "+0V8_VDD_SNVS (LDO2)"; regulator-min-microvolt =3D <800000>; regulator-max-microvolt =3D <900000>; regulator-boot-on; @@ -155,7 +155,7 @@ reg_vdd_snvs: LDO2 { }; =20 reg_vdda: LDO3 { - regulator-name =3D "ldo3"; + regulator-name =3D "+1V8_VDDA (LDO3)"; regulator-min-microvolt =3D <1800000>; regulator-max-microvolt =3D <1800000>; regulator-boot-on; @@ -163,7 +163,7 @@ reg_vdda: LDO3 { }; =20 reg_vdd_phy: LDO4 { - regulator-name =3D "ldo4"; + regulator-name =3D "+0V9_VDD_PHY (LDO4)"; regulator-min-microvolt =3D <900000>; regulator-max-microvolt =3D <900000>; regulator-boot-on; @@ -171,7 +171,7 @@ reg_vdd_phy: LDO4 { }; =20 reg_nvcc_sd: LDO5 { - regulator-name =3D "ldo5"; + regulator-name =3D "NVCC_SD (LDO5)"; regulator-min-microvolt =3D <1800000>; regulator-max-microvolt =3D <3300000>; }; --=20 2.37.1 From nobody Sun Apr 12 02:46:49 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8A814C00144 for ; Mon, 1 Aug 2022 13:16:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230203AbiHANQo (ORCPT ); Mon, 1 Aug 2022 09:16:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48418 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232428AbiHANQW (ORCPT ); Mon, 1 Aug 2022 09:16:22 -0400 Received: from mail.fris.de (mail.fris.de [IPv6:2a01:4f8:c2c:390b::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 085992FFC5; Mon, 1 Aug 2022 06:16:17 -0700 (PDT) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 6800CC01CB; Mon, 1 Aug 2022 15:16:13 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fris.de; s=dkim; t=1659359773; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=oa9sycEErUOj2Oq3kpiFHxM6XsttM4oiFCIw5P8CBXE=; b=Nu9+dDEj0erdR9PyNkcR7Lyrp/6Pc4rqngUdwrFEL3CH0dBOZfzCyaDdtLEy7K928YqPs5 JAia4T5t+89crAwuVkgzhVPZCDOTczaSFFOiJZIh7hvc3DDMbY5Tmk9WJ8/NiN4sgDL45C ykyW5cYngwVo14OGrnK7saVn46TIiiH0Red+4WxZW0Ke38m41NiU7zsAM5IloBDkXnARLZ WaSaSW0dlu4juoRK2j1u21SPzYoIJBlS0IhWO9UQmnj80ZznkFeWrYoQ9R89MDutXa1Ic0 M5kITVGYwfLvOk1SK66mT9nhwRHMEYJIDF+Tgp4jHaIDpzAAhgn7ilHh2OZHjQ== From: Frieder Schrempf To: devicetree@vger.kernel.org, Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rob Herring , Sascha Hauer , Shawn Guo Cc: Fabio Estevam , Frieder Schrempf , Heiko Thiery , Krzysztof Kozlowski , NXP Linux Team , Pengutronix Kernel Team Subject: [PATCH v2 7/8] arm64: dts: imx8mm-kontron: Add SPI NOR partition layout Date: Mon, 1 Aug 2022 15:15:51 +0200 Message-Id: <20220801131554.116795-8-frieder@fris.de> In-Reply-To: <20220801131554.116795-1-frieder@fris.de> References: <20220801131554.116795-1-frieder@fris.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Frieder Schrempf This is the layout used by the bootloader. Add it to the kernel devicetree to make the same layout available in Linux and have the devicetrees synced. Signed-off-by: Frieder Schrempf --- Changes in v2: * new patch --- .../freescale/imx8mm-kontron-n801x-som.dtsi | 21 +++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi b/= arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi index c995592981c2..bb87e8b166bf 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi @@ -66,6 +66,27 @@ flash@0 { compatible =3D "mxicy,mx25r1635f", "jedec,spi-nor"; spi-max-frequency =3D <80000000>; reg =3D <0>; + + partitions { + compatible =3D "fixed-partitions"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + partition@0 { + label =3D "u-boot"; + reg =3D <0x0 0x1E0000>; + }; + + partition@1 { + label =3D "env"; + reg =3D <0x1E0000 0x10000>; + }; + + partition@2 { + label =3D "env_redundant"; + reg =3D <0x1F0000 0x10000>; + }; + }; }; }; =20 --=20 2.37.1 From nobody Sun Apr 12 02:46:49 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1B85DC19F2A for ; Mon, 1 Aug 2022 13:16:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232155AbiHANQ4 (ORCPT ); Mon, 1 Aug 2022 09:16:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49306 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232660AbiHANQm (ORCPT ); Mon, 1 Aug 2022 09:16:42 -0400 Received: from mail.fris.de (mail.fris.de [IPv6:2a01:4f8:c2c:390b::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 10E233123F; Mon, 1 Aug 2022 06:16:25 -0700 (PDT) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 52C02BFBC6; Mon, 1 Aug 2022 15:16:22 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fris.de; s=dkim; t=1659359783; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=AdOd6hCJJfT4+a+FZWfdVtDgMgpS6KdkZFqreBclcz0=; b=h6CXYAI2mAKlR6/Q/54MjWPfK5rCTSb/ik2utaxDMSsJSBujkDSBm5bt0SGWGK/Hgkt0UA 7f0FjNKaBFT5VOQMDy438sJgrXIWDpgmoYRX15epceSBpuPvwv0CJEdPHq2/bhaJFkNNJV Q/4A4mb4EfvsXQigidTgTEf3iWG/UJjZZxh1C9AJKrJPufsHrezDUNzsYF1yjR1ezpp1HB GHBj8/XiQkEtQuDp3uaUVWXV52+irgkvi2aAUd9ZmgNHPtwznsotVKsyFBaGASlh5ygjSM SZhGg//vjgN/oBAUsNVJWG1fpKy83SsIB0WlJVBc8l6fFgVOREK7vr2jA+0yjw== From: Frieder Schrempf To: devicetree@vger.kernel.org, Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rob Herring , Sascha Hauer , Shawn Guo Cc: Fabio Estevam , Frieder Schrempf , Alexander Stein , Alex Marginean , Heiko Thiery , Krzysztof Kozlowski , Marcel Ziswiler , Marek Vasut , NXP Linux Team , Oleksij Rempel , Pengutronix Kernel Team , Reinhold Mueller , Tim Harvey , Vladimir Oltean Subject: [PATCH v2 8/8] arm64: dts: Add support for Kontron SL/BL i.MX8MM OSM-S Date: Mon, 1 Aug 2022 15:15:52 +0200 Message-Id: <20220801131554.116795-9-frieder@fris.de> In-Reply-To: <20220801131554.116795-1-frieder@fris.de> References: <20220801131554.116795-1-frieder@fris.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Frieder Schrempf This adds support for the Kontron Electronics SL i.MX8MM OSM-S SoM and the matching baseboard BL i.MX8MM OSM-S. The SoM hardware complies to the Open Standard Module (OSM) 1.0 specification, size S (https://sget.org/standards/osm). Signed-off-by: Frieder Schrempf --- Changes in v2: * add SPI NOR partitions * use voltage rail names for PMIC regulator-name * drop unused header include --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../dts/freescale/imx8mm-kontron-n802x-s.dts | 376 ++++++++++++++++++ .../freescale/imx8mm-kontron-n802x-som.dtsi | 330 +++++++++++++++ 3 files changed, 707 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-kontron-n802x-s.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-kontron-n802x-som.= dtsi diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/f= reescale/Makefile index 238a83e5b8c6..87d1c66c6060 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -56,6 +56,7 @@ dtb-$(CONFIG_ARCH_MXC) +=3D imx8mm-evk.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mm-icore-mx8mm-ctouch2.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mm-icore-mx8mm-edimm2.2.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mm-kontron-n801x-s.dtb +dtb-$(CONFIG_ARCH_MXC) +=3D imx8mm-kontron-n802x-s.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mm-mx8menlo.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mm-nitrogen-r2.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mm-tqma8mqml-mba8mx.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-n802x-s.dts b/arc= h/arm64/boot/dts/freescale/imx8mm-kontron-n802x-s.dts new file mode 100644 index 000000000000..3d66506f7484 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n802x-s.dts @@ -0,0 +1,376 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2022 Kontron Electronics GmbH + */ + +/dts-v1/; + +#include "imx8mm-kontron-n802x-som.dtsi" + +/ { + model =3D "Kontron BL i.MX8MM OSM-S (N802X)"; + compatible =3D "kontron,imx8mm-n802x-s", "kontron,imx8mm-n802x-som", "fsl= ,imx8mm"; + + aliases { + ethernet1 =3D &usbnet; + }; + + /* fixed crystal dedicated to mcp2542fd */ + osc_can: clock-osc-can { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <40000000>; + clock-output-names =3D "osc-can"; + }; + + leds { + compatible =3D "gpio-leds"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_gpio_led>; + + led1 { + label =3D "led1"; + gpios =3D <&gpio1 12 GPIO_ACTIVE_LOW>; + linux,default-trigger =3D "heartbeat"; + }; + + led2 { + label =3D "led2"; + gpios =3D <&gpio1 13 GPIO_ACTIVE_LOW>; + }; + + led3 { + label =3D "led3"; + gpios =3D <&gpio1 14 GPIO_ACTIVE_LOW>; + }; + }; + + pwm-beeper { + compatible =3D "pwm-beeper"; + pwms =3D <&pwm2 0 5000 0>; + }; + + reg_rst_eth2: regulator-rst-eth2 { + compatible =3D "regulator-fixed"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_usb_eth2>; + gpio =3D <&gpio3 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + regulator-name =3D "rst-usb-eth2"; + }; + + reg_usb1_vbus: regulator-usb1-vbus { + compatible =3D "regulator-fixed"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_reg_usb1_vbus>; + gpio =3D <&gpio3 25 GPIO_ACTIVE_LOW>; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + regulator-name =3D "usb1-vbus"; + }; + + reg_vdd_5v: regulator-5v { + compatible =3D "regulator-fixed"; + regulator-always-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + regulator-name =3D "vdd-5v"; + }; +}; + +&ecspi2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_ecspi2>; + cs-gpios =3D <&gpio5 13 GPIO_ACTIVE_LOW>; + status =3D "okay"; + + can@0 { + compatible =3D "microchip,mcp251xfd"; + reg =3D <0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_can>; + clocks =3D <&osc_can>; + interrupts-extended =3D <&gpio4 28 IRQ_TYPE_LEVEL_LOW>; + /* + * Limit the SPI clock to 15 MHz to prevent issues + * with corrupted data due to chip errata. + */ + spi-max-frequency =3D <15000000>; + vdd-supply =3D <®_vdd_3v3>; + xceiver-supply =3D <®_vdd_5v>; + }; +}; + +&ecspi3 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_ecspi3>; + cs-gpios =3D <&gpio5 25 GPIO_ACTIVE_LOW>; + status =3D "okay"; + + eeram@0 { + compatible =3D "microchip,48l640"; + reg =3D <0>; + spi-max-frequency =3D <20000000>; + }; +}; + +&fec1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_enet>; + phy-connection-type =3D "rgmii-rxid"; + phy-handle =3D <ðphy>; + status =3D "okay"; + + mdio { + #address-cells =3D <1>; + #size-cells =3D <0>; + + ethphy: ethernet-phy@0 { + reg =3D <0>; + reset-assert-us =3D <1>; + reset-deassert-us =3D <15000>; + reset-gpios =3D <&gpio1 1 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&gpio1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_gpio1>; + gpio-line-names =3D "", "", "", "dio1-out", "", "", "dio1-in", "dio2-out", + "dio2-in", "dio3-out", "dio3-in", "dio4-out", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio5 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_gpio5>; + gpio-line-names =3D "", "", "dio4-in", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&i2c4 { + clock-frequency =3D <100000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_i2c4>; + status =3D "okay"; +}; + +&pwm2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_pwm2>; + status =3D "okay"; +}; + +&uart1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_uart1>; + uart-has-rtscts; + status =3D "okay"; +}; + +&uart2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_uart2>; + linux,rs485-enabled-at-boot-time; + uart-has-rtscts; + status =3D "okay"; +}; + +&usbotg1 { + dr_mode =3D "otg"; + disable-over-current; + vbus-supply =3D <®_usb1_vbus>; + status =3D "okay"; +}; + +&usbotg2 { + dr_mode =3D "host"; + disable-over-current; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "okay"; + + usb1@1 { + compatible =3D "usb424,9514"; + reg =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + usbnet: ethernet@1 { + compatible =3D "usb424,ec00"; + reg =3D <1>; + local-mac-address =3D [ 00 00 00 00 00 00 ]; + }; + }; +}; + +&usdhc2 { + pinctrl-names =3D "default", "state_100mhz", "state_200mhz"; + pinctrl-0 =3D <&pinctrl_usdhc2>; + pinctrl-1 =3D <&pinctrl_usdhc2_100mhz>; + pinctrl-2 =3D <&pinctrl_usdhc2_200mhz>; + vmmc-supply =3D <®_vdd_3v3>; + vqmmc-supply =3D <®_nvcc_sd>; + cd-gpios =3D <&gpio2 12 GPIO_ACTIVE_LOW>; + status =3D "okay"; +}; + +&iomuxc { + pinctrl_can: cangrp { + fsl,pins =3D < + MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x19 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins =3D < + MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82 + MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82 + MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82 + MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x19 + >; + }; + + pinctrl_ecspi3: ecspi3grp { + fsl,pins =3D < + MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x82 + MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x82 + MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x82 + MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x19 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins =3D < + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 + MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x19 /* PHY RST */ + MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19 /* ETH IRQ */ + >; + }; + + pinctrl_gpio_led: gpioledgrp { + fsl,pins =3D < + MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x19 + MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x19 + MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x19 + >; + }; + + pinctrl_gpio1: gpio1grp { + fsl,pins =3D < + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x19 + MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 + MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 + MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19 + MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19 + MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x19 + MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 + >; + }; + + pinctrl_gpio5: gpio5grp { + fsl,pins =3D < + MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x19 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins =3D < + MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 + MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins =3D < + MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x19 + >; + }; + + pinctrl_reg_usb1_vbus: regusb1vbusgrp { + fsl,pins =3D < + MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x19 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins =3D < + MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x140 + MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x140 + MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x140 + MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x140 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins =3D < + MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x140 + MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x140 + MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x140 + MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x140 + >; + }; + + pinctrl_usb_eth2: usbeth2grp { + fsl,pins =3D < + MX8MM_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x19 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins =3D < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins =3D < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins =3D < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-n802x-som.dtsi b/= arch/arm64/boot/dts/freescale/imx8mm-kontron-n802x-som.dtsi new file mode 100644 index 000000000000..812dabecec86 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n802x-som.dtsi @@ -0,0 +1,330 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2022 Kontron Electronics GmbH + */ + +#include +#include "imx8mm.dtsi" + +/ { + model =3D "Kontron SL i.MX8MM OSM-S (N802X)"; + compatible =3D "kontron,imx8mm-n802x-som", "fsl,imx8mm"; + + memory@40000000 { + device_type =3D "memory"; + /* + * There are multiple SoM flavors with different DDR sizes. + * The smallest is 1GB. For larger sizes the bootloader will + * update the reg property. + */ + reg =3D <0x0 0x40000000 0 0x80000000>; + }; + + chosen { + stdout-path =3D &uart3; + }; +}; + +&A53_0 { + cpu-supply =3D <®_vdd_arm>; +}; + +&A53_1 { + cpu-supply =3D <®_vdd_arm>; +}; + +&A53_2 { + cpu-supply =3D <®_vdd_arm>; +}; + +&A53_3 { + cpu-supply =3D <®_vdd_arm>; +}; + +&ddrc { + operating-points-v2 =3D <&ddrc_opp_table>; + + ddrc_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-100M { + opp-hz =3D /bits/ 64 <100000000>; + }; + + opp-750M { + opp-hz =3D /bits/ 64 <750000000>; + }; + }; +}; + +&ecspi1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_ecspi1>; + cs-gpios =3D <&gpio5 9 GPIO_ACTIVE_LOW>; + status =3D "okay"; + + flash@0 { + compatible =3D "mxicy,mx25r1635f", "jedec,spi-nor"; + spi-max-frequency =3D <80000000>; + reg =3D <0>; + + partitions { + compatible =3D "fixed-partitions"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + partition@0 { + label =3D "u-boot"; + reg =3D <0x0 0x1E0000>; + }; + + partition@1 { + label =3D "env"; + reg =3D <0x1E0000 0x10000>; + }; + + partition@2 { + label =3D "env_redundant"; + reg =3D <0x1F0000 0x10000>; + }; + }; + }; +}; + +&i2c1 { + clock-frequency =3D <400000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_i2c1>; + status =3D "okay"; + + pca9450: pmic@25 { + compatible =3D "nxp,pca9450a"; + reg =3D <0x25>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_pmic>; + interrupt-parent =3D <&gpio1>; + interrupts =3D <0 IRQ_TYPE_LEVEL_LOW>; + + regulators { + reg_vdd_soc: BUCK1 { + regulator-name =3D "+0V8_VDD_SOC (BUCK1)"; + regulator-min-microvolt =3D <800000>; + regulator-max-microvolt =3D <850000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay =3D <3125>; + nxp,dvs-run-voltage =3D <850000>; + nxp,dvs-standby-voltage =3D <800000>; + }; + + reg_vdd_arm: BUCK2 { + regulator-name =3D "+0V9_VDD_ARM (BUCK2)"; + regulator-min-microvolt =3D <850000>; + regulator-max-microvolt =3D <950000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay =3D <3125>; + nxp,dvs-run-voltage =3D <950000>; + nxp,dvs-standby-voltage =3D <850000>; + }; + + reg_vdd_dram: BUCK3 { + regulator-name =3D "+0V9_VDD_DRAM&PU (BUCK3)"; + regulator-min-microvolt =3D <850000>; + regulator-max-microvolt =3D <950000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_vdd_3v3: BUCK4 { + regulator-name =3D "+3V3 (BUCK4)"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_vdd_1v8: BUCK5 { + regulator-name =3D "+1V8 (BUCK5)"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_nvcc_dram: BUCK6 { + regulator-name =3D "+1V1_NVCC_DRAM (BUCK6)"; + regulator-min-microvolt =3D <1100000>; + regulator-max-microvolt =3D <1100000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_nvcc_snvs: LDO1 { + regulator-name =3D "+1V8_NVCC_SNVS (LDO1)"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_vdd_snvs: LDO2 { + regulator-name =3D "+0V8_VDD_SNVS (LDO2)"; + regulator-min-microvolt =3D <800000>; + regulator-max-microvolt =3D <900000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_vdda: LDO3 { + regulator-name =3D "+1V8_VDDA (LDO3)"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_vdd_phy: LDO4 { + regulator-name =3D "+0V9_VDD_PHY (LDO4)"; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <900000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_nvcc_sd: LDO5 { + regulator-name =3D "NVCC_SD (LDO5)"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + }; + }; + }; + + rtc@52 { + compatible =3D "microcrystal,rv3028"; + reg =3D <0x52>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_rtc>; + interrupts-extended =3D <&gpio4 1 IRQ_TYPE_LEVEL_HIGH>; + trickle-diode-disable; + }; +}; + +&uart3 { /* console */ + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_uart3>; + status =3D "okay"; +}; + +&usdhc1 { + pinctrl-names =3D "default", "state_100mhz", "state_200mhz"; + pinctrl-0 =3D <&pinctrl_usdhc1>; + pinctrl-1 =3D <&pinctrl_usdhc1_100mhz>; + pinctrl-2 =3D <&pinctrl_usdhc1_200mhz>; + vmmc-supply =3D <®_vdd_3v3>; + vqmmc-supply =3D <®_vdd_1v8>; + bus-width =3D <8>; + non-removable; + status =3D "okay"; +}; + +&wdog1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_wdog>; + fsl,ext-reset-output; + status =3D "okay"; +}; + +&iomuxc { + pinctrl_ecspi1: ecspi1grp { + fsl,pins =3D < + MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82 + MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82 + MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82 + MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x19 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins =3D < + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 + MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins =3D < + MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x141 + >; + }; + + pinctrl_rtc: rtcgrp { + fsl,pins =3D < + MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x19 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins =3D < + MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 + MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins =3D < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 + MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d0 + MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d0 + MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d0 + MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d0 + MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x019 + MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x190 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins =3D < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 + MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d4 + MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d4 + MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d4 + MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d4 + MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x019 + MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x194 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins =3D < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 + MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d6 + MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d6 + MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d6 + MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d6 + MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x019 + MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x196 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins =3D < + MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + >; + }; +}; --=20 2.37.1