From nobody Sat Sep 21 20:20:38 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AD32DC00144 for ; Mon, 1 Aug 2022 12:49:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235065AbiHAMtm (ORCPT ); Mon, 1 Aug 2022 08:49:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49520 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235030AbiHAMtR (ORCPT ); Mon, 1 Aug 2022 08:49:17 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C5F35491FB; Mon, 1 Aug 2022 05:41:18 -0700 (PDT) X-UUID: 83f615bc9bd0405792f573f74fbdfc32-20220801 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.8,REQID:ea18557d-d2e9-44d0-b949-ffca6781760b,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACTI ON:release,TS:0 X-CID-META: VersionHash:0f94e32,CLOUDID:c5e1e8d0-841b-4e95-ad42-8f86e18f54fc,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil ,QS:nil,BEC:nil,COL:0 X-UUID: 83f615bc9bd0405792f573f74fbdfc32-20220801 Received: from mtkmbs11n1.mediatek.inc [(172.21.101.185)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 344372877; Mon, 01 Aug 2022 20:41:11 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Mon, 1 Aug 2022 20:39:56 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Mon, 1 Aug 2022 20:39:56 +0800 From: Allen-KH Cheng To: Matthias Brugger , Rob Herring , Krzysztof Kozlowski CC: , , , , , Chen-Yu Tsai , , Allen-KH Cheng , Allen-KH Cheng Subject: [PATCH v12 1/1] arm64: dts: Add MediaTek MT8186 dts and evaluation board and Makefile Date: Mon, 1 Aug 2022 20:39:52 +0800 Message-ID: <20220801123952.18932-2-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220801123952.18932-1-allen-kh.cheng@mediatek.com> References: <20220801123952.18932-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add basic chip support for MediaTek MT8186. Signed-off-by: Allen-KH Cheng --- arch/arm64/boot/dts/mediatek/Makefile | 1 + arch/arm64/boot/dts/mediatek/mt8186-evb.dts | 238 ++++++ arch/arm64/boot/dts/mediatek/mt8186.dtsi | 874 ++++++++++++++++++++ 3 files changed, 1113 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt8186-evb.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt8186.dtsi diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/me= diatek/Makefile index af362a085a02..0ec90cb3ef28 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -37,6 +37,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8183-kukui-kodama-sku3= 2.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8183-kukui-krane-sku0.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8183-kukui-krane-sku176.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8183-pumpkin.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8186-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8192-asurada-hayato-r1.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8192-asurada-spherion-r0.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8192-evb.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt8186-evb.dts b/arch/arm64/boot/= dts/mediatek/mt8186-evb.dts new file mode 100644 index 000000000000..7d4a64ab95e4 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8186-evb.dts @@ -0,0 +1,238 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Copyright (C) 2022 MediaTek Inc. + */ +/dts-v1/; +#include "mt8186.dtsi" + +/ { + model =3D "MediaTek MT8186 evaluation board"; + compatible =3D "mediatek,mt8186-evb", "mediatek,mt8186"; + + aliases { + serial0 =3D &uart0; + }; + + chosen { + stdout-path =3D "serial0:921600n8"; + }; + + memory@40000000 { + device_type =3D "memory"; + reg =3D <0 0x40000000 0 0x80000000>; + }; +}; + +&i2c0 { + status =3D "okay"; + + clock-frequency =3D <400000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c0_pins>; +}; + +&i2c1 { + status =3D "okay"; + + clock-frequency =3D <400000>; + i2c-scl-internal-delay-ns =3D <8000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c1_pins>; +}; + +&i2c2 { + status =3D "okay"; + + clock-frequency =3D <400000>; + i2c-scl-internal-delay-ns =3D <10000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c2_pins>; +}; + +&i2c3 { + status =3D "okay"; + + clock-frequency =3D <400000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c3_pins>; +}; + +&i2c4 { + status =3D "okay"; + + clock-frequency =3D <400000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c4_pins>; +}; + +&i2c5 { + status =3D "okay"; + + clock-frequency =3D <400000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c5_pins>; +}; + +&i2c6 { + status =3D "okay"; + + clock-frequency =3D <400000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c6_pins>; +}; + +&i2c7 { + status =3D "okay"; + + clock-frequency =3D <400000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c7_pins>; +}; + +&i2c8 { + status =3D "okay"; + + clock-frequency =3D <400000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c8_pins>; +}; + +&i2c9 { + status =3D "okay"; + + clock-frequency =3D <400000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c9_pins>; +}; + +&pio { + i2c0_pins: i2c0-default-pins { + pins-bus { + pinmux =3D , + ; + bias-disable; + drive-strength-microamp =3D <1000>; + drive-strength =3D <4>; + input-enable; + }; + }; + + i2c1_pins: i2c1-default-pins { + pins-bus { + pinmux =3D , + ; + bias-disable; + drive-strength-microamp =3D <1000>; + drive-strength =3D <4>; + input-enable; + }; + }; + + i2c2_pins: i2c2-default-pins { + pins-bus { + pinmux =3D , + ; + bias-disable; + drive-strength-microamp =3D <1000>; + drive-strength =3D <4>; + input-enable; + }; + }; + + i2c3_pins: i2c3-default-pins { + pins-bus { + pinmux =3D , + ; + bias-disable; + drive-strength-microamp =3D <1000>; + drive-strength =3D <4>; + input-enable; + }; + }; + + i2c4_pins: i2c4-default-pins { + pins-bus { + pinmux =3D , + ; + bias-disable; + drive-strength-microamp =3D <1000>; + drive-strength =3D <4>; + input-enable; + }; + }; + + i2c5_pins: i2c5-default-pins { + pins-bus { + pinmux =3D , + ; + bias-disable; + drive-strength-microamp =3D <1000>; + drive-strength =3D <4>; + input-enable; + }; + }; + + i2c6_pins: i2c6-default-pins { + pins-bus { + pinmux =3D , + ; + bias-pull-up =3D ; + drive-strength-microamp =3D <1000>; + drive-strength =3D <4>; + input-enable; + }; + }; + + i2c7_pins: i2c7-default-pins { + pins-bus { + pinmux =3D , + ; + bias-disable; + drive-strength-microamp =3D <1000>; + drive-strength =3D <4>; + input-enable; + }; + }; + + i2c8_pins: i2c8-default-pins { + pins-bus { + pinmux =3D , + ; + bias-disable; + drive-strength-microamp =3D <1000>; + drive-strength =3D <4>; + input-enable; + }; + }; + + i2c9_pins: i2c9-default-pins { + pins-bus { + pinmux =3D , + ; + bias-pull-up =3D ; + drive-strength-microamp =3D <1000>; + drive-strength =3D <4>; + input-enable; + }; + }; +}; + +&u3phy0 { + status =3D "okay"; +}; + +&u3phy1 { + status =3D "okay"; +}; + +&uart0 { + status =3D "okay"; +}; + +&xhci0 { + status =3D "okay"; +}; + +&xhci1 { + status =3D "okay"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts= /mediatek/mt8186.dtsi new file mode 100644 index 000000000000..38f9466eea42 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi @@ -0,0 +1,874 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Copyright (C) 2022 MediaTek Inc. + * Author: Allen-KH Cheng + */ +/dts-v1/; +#include +#include +#include +#include +#include +#include +#include + +/ { + compatible =3D "mediatek,mt8186"; + interrupt-parent =3D <&gic>; + #address-cells =3D <2>; + #size-cells =3D <2>; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu-map { + cluster0 { + core0 { + cpu =3D <&cpu0>; + }; + + core1 { + cpu =3D <&cpu1>; + }; + + core2 { + cpu =3D <&cpu2>; + }; + + core3 { + cpu =3D <&cpu3>; + }; + + core4 { + cpu =3D <&cpu4>; + }; + + core5 { + cpu =3D <&cpu5>; + }; + }; + + cluster1 { + core0 { + cpu =3D <&cpu6>; + }; + + core1 { + cpu =3D <&cpu7>; + }; + }; + }; + + cpu0: cpu@0 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x000>; + enable-method =3D "psci"; + clock-frequency =3D <2000000000>; + capacity-dmips-mhz =3D <382>; + cpu-idle-states =3D <&cpu_off_l &cluster_off_l>; + next-level-cache =3D <&l2_0>; + #cooling-cells =3D <2>; + }; + + cpu1: cpu@100 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x100>; + enable-method =3D "psci"; + clock-frequency =3D <2000000000>; + capacity-dmips-mhz =3D <382>; + cpu-idle-states =3D <&cpu_off_l &cluster_off_l>; + next-level-cache =3D <&l2_0>; + #cooling-cells =3D <2>; + }; + + cpu2: cpu@200 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x200>; + enable-method =3D "psci"; + clock-frequency =3D <2000000000>; + capacity-dmips-mhz =3D <382>; + cpu-idle-states =3D <&cpu_off_l &cluster_off_l>; + next-level-cache =3D <&l2_0>; + #cooling-cells =3D <2>; + }; + + cpu3: cpu@300 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x300>; + enable-method =3D "psci"; + clock-frequency =3D <2000000000>; + capacity-dmips-mhz =3D <382>; + cpu-idle-states =3D <&cpu_off_l &cluster_off_l>; + next-level-cache =3D <&l2_0>; + #cooling-cells =3D <2>; + }; + + cpu4: cpu@400 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x400>; + enable-method =3D "psci"; + clock-frequency =3D <2000000000>; + capacity-dmips-mhz =3D <382>; + cpu-idle-states =3D <&cpu_off_l &cluster_off_l>; + next-level-cache =3D <&l2_0>; + #cooling-cells =3D <2>; + }; + + cpu5: cpu@500 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x500>; + enable-method =3D "psci"; + clock-frequency =3D <2000000000>; + capacity-dmips-mhz =3D <382>; + cpu-idle-states =3D <&cpu_off_l &cluster_off_l>; + next-level-cache =3D <&l2_0>; + #cooling-cells =3D <2>; + }; + + cpu6: cpu@600 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a76"; + reg =3D <0x600>; + enable-method =3D "psci"; + clock-frequency =3D <2050000000>; + capacity-dmips-mhz =3D <1024>; + cpu-idle-states =3D <&cpu_off_b &cluster_off_b>; + next-level-cache =3D <&l2_1>; + #cooling-cells =3D <2>; + }; + + cpu7: cpu@700 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a76"; + reg =3D <0x700>; + enable-method =3D "psci"; + clock-frequency =3D <2050000000>; + capacity-dmips-mhz =3D <1024>; + cpu-idle-states =3D <&cpu_off_b &cluster_off_b>; + next-level-cache =3D <&l2_1>; + #cooling-cells =3D <2>; + }; + + idle-states { + entry-method =3D "psci"; + + cpu_off_l: cpu-off-l { + compatible =3D "arm,idle-state"; + arm,psci-suspend-param =3D <0x00010001>; + local-timer-stop; + entry-latency-us =3D <50>; + exit-latency-us =3D <100>; + min-residency-us =3D <1600>; + }; + + cpu_off_b: cpu-off-b { + compatible =3D "arm,idle-state"; + arm,psci-suspend-param =3D <0x00010001>; + local-timer-stop; + entry-latency-us =3D <50>; + exit-latency-us =3D <100>; + min-residency-us =3D <1400>; + }; + + cluster_off_l: cluster-off-l { + compatible =3D "arm,idle-state"; + arm,psci-suspend-param =3D <0x01010001>; + local-timer-stop; + entry-latency-us =3D <100>; + exit-latency-us =3D <250>; + min-residency-us =3D <2100>; + }; + + cluster_off_b: cluster-off-b { + compatible =3D "arm,idle-state"; + arm,psci-suspend-param =3D <0x01010001>; + local-timer-stop; + entry-latency-us =3D <100>; + exit-latency-us =3D <250>; + min-residency-us =3D <1900>; + }; + }; + + l2_0: l2-cache0 { + compatible =3D "cache"; + next-level-cache =3D <&l3_0>; + }; + + l2_1: l2-cache1 { + compatible =3D "cache"; + next-level-cache =3D <&l3_0>; + }; + + l3_0: l3-cache { + compatible =3D "cache"; + }; + }; + + clk13m: oscillator-13m { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <13000000>; + clock-output-names =3D "clk13m"; + }; + + clk26m: oscillator-26m { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <26000000>; + clock-output-names =3D "clk26m"; + }; + + clk32k: oscillator-32k { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <32768>; + clock-output-names =3D "clk32k"; + }; + + pmu-a55 { + compatible =3D "arm,cortex-a55-pmu"; + interrupt-parent =3D <&gic>; + interrupts =3D ; + }; + + pmu-a76 { + compatible =3D "arm,cortex-a76-pmu"; + interrupt-parent =3D <&gic>; + interrupts =3D ; + }; + + psci { + compatible =3D "arm,psci-1.0"; + method =3D "smc"; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupt-parent =3D <&gic>; + interrupts =3D , + , + , + ; + }; + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + compatible =3D "simple-bus"; + ranges; + + gic: interrupt-controller@c000000 { + compatible =3D "arm,gic-v3"; + #interrupt-cells =3D <4>; + #redistributor-regions =3D <1>; + interrupt-parent =3D <&gic>; + interrupt-controller; + reg =3D <0 0x0c000000 0 0x40000>, + <0 0x0c040000 0 0x200000>; + interrupts =3D ; + + ppi-partitions { + ppi_cluster0: interrupt-partition-0 { + affinity =3D <&cpu0 &cpu1 &cpu2 &cpu3 &cpu4 &cpu5>; + }; + + ppi_cluster1: interrupt-partition-1 { + affinity =3D <&cpu6 &cpu7>; + }; + }; + }; + + mcusys: syscon@c53a000 { + compatible =3D "mediatek,mt8186-mcusys", "syscon"; + reg =3D <0 0xc53a000 0 0x1000>; + #clock-cells =3D <1>; + }; + + topckgen: syscon@10000000 { + compatible =3D "mediatek,mt8186-topckgen", "syscon"; + reg =3D <0 0x10000000 0 0x1000>; + #clock-cells =3D <1>; + }; + + infracfg_ao: syscon@10001000 { + compatible =3D "mediatek,mt8186-infracfg_ao", "syscon"; + reg =3D <0 0x10001000 0 0x1000>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; + + pericfg: syscon@10003000 { + compatible =3D "mediatek,mt8186-pericfg", "syscon"; + reg =3D <0 0x10003000 0 0x1000>; + }; + + pio: pinctrl@10005000 { + compatible =3D "mediatek,mt8186-pinctrl"; + reg =3D <0 0x10005000 0 0x1000>, + <0 0x10002000 0 0x0200>, + <0 0x10002200 0 0x0200>, + <0 0x10002400 0 0x0200>, + <0 0x10002600 0 0x0200>, + <0 0x10002A00 0 0x0200>, + <0 0x10002C00 0 0x0200>, + <0 0x1000B000 0 0x1000>; + reg-names =3D "iocfg0", "iocfg_bm", "iocfg_bl", "iocfg_br", + "iocfg_lm", "iocfg_rb", "iocfg_tl", "eint"; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&pio 0 0 185>; + interrupt-controller; + interrupts =3D ; + #interrupt-cells =3D <2>; + }; + + watchdog: watchdog@10007000 { + compatible =3D "mediatek,mt8186-wdt"; + mediatek,disable-extrst; + reg =3D <0 0x10007000 0 0x1000>; + #reset-cells =3D <1>; + }; + + apmixedsys: syscon@1000c000 { + compatible =3D "mediatek,mt8186-apmixedsys", "syscon"; + reg =3D <0 0x1000c000 0 0x1000>; + #clock-cells =3D <1>; + }; + + pwrap: pwrap@1000d000 { + compatible =3D "mediatek,mt8186-pwrap", "syscon"; + reg =3D <0 0x1000d000 0 0x1000>; + reg-names =3D "pwrap"; + interrupts =3D ; + clocks =3D <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, + <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>; + clock-names =3D "spi", "wrap"; + }; + + systimer: timer@10017000 { + compatible =3D "mediatek,mt8186-timer", + "mediatek,mt6765-timer"; + reg =3D <0 0x10017000 0 0x1000>; + interrupts =3D ; + clocks =3D <&clk13m>; + }; + + scp: scp@10500000 { + compatible =3D "mediatek,mt8186-scp"; + reg =3D <0 0x10500000 0 0x40000>, + <0 0x105c0000 0 0x19080>; + reg-names =3D "sram", "cfg"; + interrupts =3D ; + }; + + nor_flash: spi@11000000 { + compatible =3D "mediatek,mt8186-nor"; + reg =3D <0 0x11000000 0 0x1000>; + clocks =3D <&topckgen CLK_TOP_SPINOR>, + <&infracfg_ao CLK_INFRA_AO_SPINOR>, + <&infracfg_ao CLK_INFRA_AO_FLASHIF_133M>, + <&infracfg_ao CLK_INFRA_AO_FLASHIF_66M>; + clock-names =3D "spi", "sf", "axi", "axi_s"; + assigned-clocks =3D <&topckgen CLK_TOP_SPINOR>; + assigned-clock-parents =3D <&topckgen CLK_TOP_UNIVPLL_D3_D8>; + interrupts =3D ; + status =3D "disabled"; + }; + + auxadc: adc@11001000 { + compatible =3D "mediatek,mt8186-auxadc", "mediatek,mt8173-auxadc"; + reg =3D <0 0x11001000 0 0x1000>; + #io-channel-cells =3D <1>; + clocks =3D <&infracfg_ao CLK_INFRA_AO_AUXADC>; + clock-names =3D "main"; + }; + + uart0: serial@11002000 { + compatible =3D "mediatek,mt8186-uart", + "mediatek,mt6577-uart"; + reg =3D <0 0x11002000 0 0x1000>; + interrupts =3D ; + clocks =3D <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART0>; + clock-names =3D "baud", "bus"; + status =3D "disabled"; + }; + + uart1: serial@11003000 { + compatible =3D "mediatek,mt8186-uart", + "mediatek,mt6577-uart"; + reg =3D <0 0x11003000 0 0x1000>; + interrupts =3D ; + clocks =3D <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART1>; + clock-names =3D "baud", "bus"; + status =3D "disabled"; + }; + + i2c0: i2c@11007000 { + compatible =3D "mediatek,mt8186-i2c"; + reg =3D <0 0x11007000 0 0x1000>, + <0 0x10200100 0 0x100>; + interrupts =3D ; + clocks =3D <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C0>, + <&infracfg_ao CLK_INFRA_AO_AP_DMA>; + clock-names =3D "main", "dma"; + clock-div =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c1: i2c@11008000 { + compatible =3D "mediatek,mt8186-i2c"; + reg =3D <0 0x11008000 0 0x1000>, + <0 0x10200200 0 0x100>; + interrupts =3D ; + clocks =3D <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C1>, + <&infracfg_ao CLK_INFRA_AO_AP_DMA>; + clock-names =3D "main", "dma"; + clock-div =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c2: i2c@11009000 { + compatible =3D "mediatek,mt8186-i2c"; + reg =3D <0 0x11009000 0 0x1000>, + <0 0x10200300 0 0x180>; + interrupts =3D ; + clocks =3D <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C2>, + <&infracfg_ao CLK_INFRA_AO_AP_DMA>; + clock-names =3D "main", "dma"; + clock-div =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c3: i2c@1100f000 { + compatible =3D "mediatek,mt8186-i2c"; + reg =3D <0 0x1100f000 0 0x1000>, + <0 0x10200480 0 0x100>; + interrupts =3D ; + clocks =3D <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C3>, + <&infracfg_ao CLK_INFRA_AO_AP_DMA>; + clock-names =3D "main", "dma"; + clock-div =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c4: i2c@11011000 { + compatible =3D "mediatek,mt8186-i2c"; + reg =3D <0 0x11011000 0 0x1000>, + <0 0x10200580 0 0x180>; + interrupts =3D ; + clocks =3D <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C4>, + <&infracfg_ao CLK_INFRA_AO_AP_DMA>; + clock-names =3D "main", "dma"; + clock-div =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c5: i2c@11016000 { + compatible =3D "mediatek,mt8186-i2c"; + reg =3D <0 0x11016000 0 0x1000>, + <0 0x10200700 0 0x100>; + interrupts =3D ; + clocks =3D <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C5>, + <&infracfg_ao CLK_INFRA_AO_AP_DMA>; + clock-names =3D "main", "dma"; + clock-div =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c6: i2c@1100d000 { + compatible =3D "mediatek,mt8186-i2c"; + reg =3D <0 0x1100d000 0 0x1000>, + <0 0x10200800 0 0x100>; + interrupts =3D ; + clocks =3D <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C6>, + <&infracfg_ao CLK_INFRA_AO_AP_DMA>; + clock-names =3D "main", "dma"; + clock-div =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c7: i2c@11004000 { + compatible =3D "mediatek,mt8186-i2c"; + reg =3D <0 0x11004000 0 0x1000>, + <0 0x10200900 0 0x180>; + interrupts =3D ; + clocks =3D <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C7>, + <&infracfg_ao CLK_INFRA_AO_AP_DMA>; + clock-names =3D "main", "dma"; + clock-div =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c8: i2c@11005000 { + compatible =3D "mediatek,mt8186-i2c"; + reg =3D <0 0x11005000 0 0x1000>, + <0 0x10200A80 0 0x180>; + interrupts =3D ; + clocks =3D <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C8>, + <&infracfg_ao CLK_INFRA_AO_AP_DMA>; + clock-names =3D "main", "dma"; + clock-div =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + spi0: spi@1100a000 { + compatible =3D "mediatek,mt8186-spi", "mediatek,mt6765-spi"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0 0x1100a000 0 0x1000>; + interrupts =3D ; + clocks =3D <&topckgen CLK_TOP_MAINPLL_D5>, + <&topckgen CLK_TOP_SPI>, + <&infracfg_ao CLK_INFRA_AO_SPI0>; + clock-names =3D "parent-clk", "sel-clk", "spi-clk"; + status =3D "disabled"; + }; + + pwm0: pwm@1100e000 { + compatible =3D "mediatek,mt8186-disp-pwm", "mediatek,mt8183-disp-pwm"; + reg =3D <0 0x1100e000 0 0x1000>; + interrupts =3D ; + #pwm-cells =3D <2>; + clocks =3D <&topckgen CLK_TOP_DISP_PWM>, + <&infracfg_ao CLK_INFRA_AO_DISP_PWM>; + clock-names =3D "main", "mm"; + status =3D "disabled"; + }; + + spi1: spi@11010000 { + compatible =3D "mediatek,mt8186-spi", "mediatek,mt6765-spi"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0 0x11010000 0 0x1000>; + interrupts =3D ; + clocks =3D <&topckgen CLK_TOP_MAINPLL_D5>, + <&topckgen CLK_TOP_SPI>, + <&infracfg_ao CLK_INFRA_AO_SPI1>; + clock-names =3D "parent-clk", "sel-clk", "spi-clk"; + status =3D "disabled"; + }; + + spi2: spi@11012000 { + compatible =3D "mediatek,mt8186-spi", "mediatek,mt6765-spi"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0 0x11012000 0 0x1000>; + interrupts =3D ; + clocks =3D <&topckgen CLK_TOP_MAINPLL_D5>, + <&topckgen CLK_TOP_SPI>, + <&infracfg_ao CLK_INFRA_AO_SPI2>; + clock-names =3D "parent-clk", "sel-clk", "spi-clk"; + status =3D "disabled"; + }; + + spi3: spi@11013000 { + compatible =3D "mediatek,mt8186-spi", "mediatek,mt6765-spi"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0 0x11013000 0 0x1000>; + interrupts =3D ; + clocks =3D <&topckgen CLK_TOP_MAINPLL_D5>, + <&topckgen CLK_TOP_SPI>, + <&infracfg_ao CLK_INFRA_AO_SPI3>; + clock-names =3D "parent-clk", "sel-clk", "spi-clk"; + status =3D "disabled"; + }; + + spi4: spi@11014000 { + compatible =3D "mediatek,mt8186-spi", "mediatek,mt6765-spi"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0 0x11014000 0 0x1000>; + interrupts =3D ; + clocks =3D <&topckgen CLK_TOP_MAINPLL_D5>, + <&topckgen CLK_TOP_SPI>, + <&infracfg_ao CLK_INFRA_AO_SPI4>; + clock-names =3D "parent-clk", "sel-clk", "spi-clk"; + status =3D "disabled"; + }; + + spi5: spi@11015000 { + compatible =3D "mediatek,mt8186-spi", "mediatek,mt6765-spi"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0 0x11015000 0 0x1000>; + interrupts =3D ; + clocks =3D <&topckgen CLK_TOP_MAINPLL_D5>, + <&topckgen CLK_TOP_SPI>, + <&infracfg_ao CLK_INFRA_AO_SPI5>; + clock-names =3D "parent-clk", "sel-clk", "spi-clk"; + status =3D "disabled"; + }; + + imp_iic_wrap: clock-controller@11017000 { + compatible =3D "mediatek,mt8186-imp_iic_wrap"; + reg =3D <0 0x11017000 0 0x1000>; + #clock-cells =3D <1>; + }; + + uart2: serial@11018000 { + compatible =3D "mediatek,mt8186-uart", + "mediatek,mt6577-uart"; + reg =3D <0 0x11018000 0 0x1000>; + interrupts =3D ; + clocks =3D <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART2>; + clock-names =3D "baud", "bus"; + status =3D "disabled"; + }; + + i2c9: i2c@11019000 { + compatible =3D "mediatek,mt8186-i2c"; + reg =3D <0 0x11019000 0 0x1000>, + <0 0x10200c00 0 0x180>; + interrupts =3D ; + clocks =3D <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C9>, + <&infracfg_ao CLK_INFRA_AO_AP_DMA>; + clock-names =3D "main", "dma"; + clock-div =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + xhci0: usb@11200000 { + compatible =3D "mediatek,mt8186-xhci", + "mediatek,mtk-xhci"; + reg =3D <0 0x11200000 0 0x1000>, + <0 0x11203e00 0 0x0100>; + reg-names =3D "mac", "ippc"; + interrupts =3D ; + phys =3D <&u2port0 PHY_TYPE_USB2>; + clocks =3D <&topckgen CLK_TOP_USB_TOP>, + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_XHCI>, + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_HCLK>, + <&infracfg_ao CLK_INFRA_AO_ICUSB>, + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_REF>; + clock-names =3D "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck"; + mediatek,syscon-wakeup =3D <&pericfg 0x420 2>; + wakeup-source; + status =3D "disabled"; + }; + + mmc0: mmc@11230000 { + compatible =3D "mediatek,mt8186-mmc", + "mediatek,mt8183-mmc"; + reg =3D <0 0x11230000 0 0x1000>, + <0 0x11cd0000 0 0x1000>; + clocks =3D <&topckgen CLK_TOP_MSDC50_0>, + <&infracfg_ao CLK_INFRA_AO_MSDC0>, + <&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>; + clock-names =3D "source", "hclk", "source_cg"; + interrupts =3D ; + assigned-clocks =3D <&topckgen CLK_TOP_MSDC50_0>; + assigned-clock-parents =3D <&apmixedsys CLK_APMIXED_MSDCPLL>; + status =3D "disabled"; + }; + + mmc1: mmc@11240000 { + compatible =3D "mediatek,mt8186-mmc", + "mediatek,mt8183-mmc"; + reg =3D <0 0x11240000 0 0x1000>, + <0 0x11c90000 0 0x1000>; + clocks =3D <&topckgen CLK_TOP_MSDC30_1>, + <&infracfg_ao CLK_INFRA_AO_MSDC1>, + <&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>; + clock-names =3D "source", "hclk", "source_cg"; + interrupts =3D ; + assigned-clocks =3D <&topckgen CLK_TOP_MSDC30_1>; + assigned-clock-parents =3D <&topckgen CLK_TOP_MSDCPLL_D2>; + status =3D "disabled"; + }; + + xhci1: usb@11280000 { + compatible =3D "mediatek,mt8186-xhci", + "mediatek,mtk-xhci"; + reg =3D <0 0x11280000 0 0x1000>, + <0 0x11283e00 0 0x0100>; + reg-names =3D "mac", "ippc"; + interrupts =3D ; + phys =3D <&u2port1 PHY_TYPE_USB2>, + <&u3port1 PHY_TYPE_USB3>; + clocks =3D <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_SYS>, + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_XHCI>, + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_HCLK>, + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_REF>; + clock-names =3D "sys_ck", "ref_ck", "mcu_ck", "xhci_ck"; + mediatek,syscon-wakeup =3D <&pericfg 0x424 2>; + wakeup-source; + status =3D "disabled"; + }; + + u3phy0: t-phy@11c80000 { + compatible =3D "mediatek,mt8186-tphy", + "mediatek,generic-tphy-v2"; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x0 0x0 0x11c80000 0x1000>; + status =3D "disabled"; + + u2port1: usb-phy@0 { + reg =3D <0x0 0x700>; + clocks =3D <&clk26m>; + clock-names =3D "ref"; + #phy-cells =3D <1>; + }; + + u3port1: usb-phy@700 { + reg =3D <0x700 0x900>; + clocks =3D <&clk26m>; + clock-names =3D "ref"; + #phy-cells =3D <1>; + }; + }; + + u3phy1: t-phy@11ca0000 { + compatible =3D "mediatek,mt8186-tphy", + "mediatek,generic-tphy-v2"; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x0 0x0 0x11ca0000 0x1000>; + status =3D "disabled"; + + u2port0: usb-phy@0 { + reg =3D <0x0 0x700>; + clocks =3D <&clk26m>; + clock-names =3D "ref"; + #phy-cells =3D <1>; + mediatek,discth =3D <0x8>; + }; + }; + + efuse: efuse@11cb0000 { + compatible =3D "mediatek,mt8186-efuse", "mediatek,efuse"; + reg =3D <0 0x11cb0000 0 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + }; + + mipi_tx0: dsi-phy@11cc0000 { + compatible =3D "mediatek,mt8183-mipi-tx"; + reg =3D <0 0x11cc0000 0 0x1000>; + clocks =3D <&clk26m>; + #clock-cells =3D <0>; + #phy-cells =3D <0>; + clock-output-names =3D "mipi_tx0_pll"; + status =3D "disabled"; + }; + + mfgsys: clock-controller@13000000 { + compatible =3D "mediatek,mt8186-mfgsys"; + reg =3D <0 0x13000000 0 0x1000>; + #clock-cells =3D <1>; + }; + + mmsys: syscon@14000000 { + compatible =3D "mediatek,mt8186-mmsys", "syscon"; + reg =3D <0 0x14000000 0 0x1000>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; + + dsi0: dsi@14013000 { + compatible =3D "mediatek,mt8186-dsi"; + reg =3D <0 0x14013000 0 0x1000>; + interrupts =3D ; + clocks =3D <&mmsys CLK_MM_DSI0>, + <&mmsys CLK_MM_DSI0_DSI_CK_DOMAIN>, + <&mipi_tx0>; + clock-names =3D "engine", "digital", "hs"; + resets =3D <&mmsys MT8186_MMSYS_SW0_RST_B_DISP_DSI0>; + phys =3D <&mipi_tx0>; + phy-names =3D "dphy"; + status =3D "disabled"; + + port { + dsi_out: endpoint { }; + }; + }; + + wpesys: clock-controller@14020000 { + compatible =3D "mediatek,mt8186-wpesys"; + reg =3D <0 0x14020000 0 0x1000>; + #clock-cells =3D <1>; + }; + + imgsys1: clock-controller@15020000 { + compatible =3D "mediatek,mt8186-imgsys1"; + reg =3D <0 0x15020000 0 0x1000>; + #clock-cells =3D <1>; + }; + + imgsys2: clock-controller@15820000 { + compatible =3D "mediatek,mt8186-imgsys2"; + reg =3D <0 0x15820000 0 0x1000>; + #clock-cells =3D <1>; + }; + + vdecsys: clock-controller@1602f000 { + compatible =3D "mediatek,mt8186-vdecsys"; + reg =3D <0 0x1602f000 0 0x1000>; + #clock-cells =3D <1>; + }; + + vencsys: clock-controller@17000000 { + compatible =3D "mediatek,mt8186-vencsys"; + reg =3D <0 0x17000000 0 0x1000>; + #clock-cells =3D <1>; + }; + + camsys: clock-controller@1a000000 { + compatible =3D "mediatek,mt8186-camsys"; + reg =3D <0 0x1a000000 0 0x1000>; + #clock-cells =3D <1>; + }; + + camsys_rawa: clock-controller@1a04f000 { + compatible =3D "mediatek,mt8186-camsys_rawa"; + reg =3D <0 0x1a04f000 0 0x1000>; + #clock-cells =3D <1>; + }; + + camsys_rawb: clock-controller@1a06f000 { + compatible =3D "mediatek,mt8186-camsys_rawb"; + reg =3D <0 0x1a06f000 0 0x1000>; + #clock-cells =3D <1>; + }; + + mdpsys: clock-controller@1b000000 { + compatible =3D "mediatek,mt8186-mdpsys"; + reg =3D <0 0x1b000000 0 0x1000>; + #clock-cells =3D <1>; + }; + + ipesys: clock-controller@1c000000 { + compatible =3D "mediatek,mt8186-ipesys"; + reg =3D <0 0x1c000000 0 0x1000>; + #clock-cells =3D <1>; + }; + }; +}; --=20 2.18.0