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[122.107.196.14]) by smtp.gmail.com with ESMTPSA id y124-20020a62ce82000000b005258df7615bsm1571901pfg.0.2022.07.28.19.05.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Jul 2022 19:05:29 -0700 (PDT) From: Daniil Lunev To: Adrian Hunter , Bart Van Assche , Greg Kroah-Hartman Cc: Daniil Lunev , Alim Akhtar , Andy Gross , Avri Altman , Bean Huo , Bjorn Andersson , Daejun Park , Eric Biggers , "James E.J. Bottomley" , Konrad Dybcio , "Martin K. Petersen" , Matthias Brugger , Mike Snitzer , Stanley Chu , Ulf Hansson , linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-scsi@vger.kernel.org Subject: [PATCH v3 1/2] ufs: add function to check CRYPTO capability Date: Fri, 29 Jul 2022 12:05:07 +1000 Message-Id: <20220729120216.v3.1.I6b7934b96fff0d5ea22531e57c0a11f0ccd1acd8@changeid> X-Mailer: git-send-email 2.31.0 In-Reply-To: <20220729020508.4147751-1-dlunev@chromium.org> References: <20220729020508.4147751-1-dlunev@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" To align with other capability check functions. Signed-off-by: Daniil Lunev drivers/ufs/core/ufshcd-crypto.c | 8 ++++---- drivers/ufs/host/ufs-mediatek.c | 2 +- drivers/ufs/host/ufs-qcom-ice.c | 4 ++-- drivers/ufs/host/ufshcd-pci.c | 2 +- include/ufs/ufshcd.h | 5 +++++ 5 files changed, 13 insertions(+), 8 deletions(-) diff --git a/drivers/ufs/core/ufshcd-crypto.c b/drivers/ufs/core/ufshcd-cry= pto.c index 198360fe5e8e1..f819488bbde14 100644 --- a/drivers/ufs/core/ufshcd-crypto.c +++ b/drivers/ufs/core/ufshcd-crypto.c @@ -118,7 +118,7 @@ static int ufshcd_crypto_keyslot_evict(struct blk_crypt= o_profile *profile, =20 bool ufshcd_crypto_enable(struct ufs_hba *hba) { - if (!(hba->caps & UFSHCD_CAP_CRYPTO)) + if (!ufshcd_is_crypto_supported(hba)) return false; =20 /* Reset might clear all keys, so reprogram all the keys. */ @@ -165,7 +165,7 @@ int ufshcd_hba_init_crypto_capabilities(struct ufs_hba = *hba) * hasn't advertised that crypto is supported. */ if (!(hba->capabilities & MASK_CRYPTO_SUPPORT) || - !(hba->caps & UFSHCD_CAP_CRYPTO)) + !ufshcd_is_crypto_supported(hba)) goto out; =20 hba->crypto_capabilities.reg_val =3D @@ -225,7 +225,7 @@ void ufshcd_init_crypto(struct ufs_hba *hba) { int slot; =20 - if (!(hba->caps & UFSHCD_CAP_CRYPTO)) + if (!ufshcd_is_crypto_supported(hba)) return; =20 /* Clear all keyslots - the number of keyslots is (CFGC + 1) */ @@ -235,6 +235,6 @@ void ufshcd_init_crypto(struct ufs_hba *hba) =20 void ufshcd_crypto_register(struct ufs_hba *hba, struct request_queue *q) { - if (hba->caps & UFSHCD_CAP_CRYPTO) + if (ufshcd_is_crypto_supported(hba)) blk_crypto_register(&hba->crypto_profile, q); } diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediate= k.c index beabc3ccd30b3..4bdf6a709126d 100644 --- a/drivers/ufs/host/ufs-mediatek.c +++ b/drivers/ufs/host/ufs-mediatek.c @@ -182,7 +182,7 @@ static int ufs_mtk_hce_enable_notify(struct ufs_hba *hb= a, ufs_mtk_host_reset(hba); } =20 - if (hba->caps & UFSHCD_CAP_CRYPTO) + if (ufshcd_is_crypto_supported(hba)) ufs_mtk_crypto_enable(hba); =20 if (host->caps & UFS_MTK_CAP_DISABLE_AH8) { diff --git a/drivers/ufs/host/ufs-qcom-ice.c b/drivers/ufs/host/ufs-qcom-ic= e.c index 745e48ec598f8..180a015b6973d 100644 --- a/drivers/ufs/host/ufs-qcom-ice.c +++ b/drivers/ufs/host/ufs-qcom-ice.c @@ -161,7 +161,7 @@ static void qcom_ice_optimization_enable(struct ufs_qco= m_host *host) =20 int ufs_qcom_ice_enable(struct ufs_qcom_host *host) { - if (!(host->hba->caps & UFSHCD_CAP_CRYPTO)) + if (!ufshcd_is_crypto_supported(host->hba)) return 0; qcom_ice_low_power_mode_enable(host); qcom_ice_optimization_enable(host); @@ -189,7 +189,7 @@ int ufs_qcom_ice_resume(struct ufs_qcom_host *host) { int err; =20 - if (!(host->hba->caps & UFSHCD_CAP_CRYPTO)) + if (!ufshcd_is_crypto_supported(host->hba)) return 0; =20 err =3D qcom_ice_wait_bist_status(host); diff --git a/drivers/ufs/host/ufshcd-pci.c b/drivers/ufs/host/ufshcd-pci.c index 04166bda41daa..c06ccef348065 100644 --- a/drivers/ufs/host/ufshcd-pci.c +++ b/drivers/ufs/host/ufshcd-pci.c @@ -89,7 +89,7 @@ static int ufs_intel_hce_enable_notify(struct ufs_hba *hb= a, enum ufs_notify_change_status status) { /* Cannot enable ICE until after HC enable */ - if (status =3D=3D POST_CHANGE && hba->caps & UFSHCD_CAP_CRYPTO) { + if (status =3D=3D POST_CHANGE && ufshcd_is_crypto_supported(hba)) { u32 hce =3D ufshcd_readl(hba, REG_CONTROLLER_ENABLE); =20 hce |=3D CRYPTO_GENERAL_ENABLE; diff --git a/include/ufs/ufshcd.h b/include/ufs/ufshcd.h index a92271421718e..ddbf470f8f455 100644 --- a/include/ufs/ufshcd.h +++ b/include/ufs/ufshcd.h @@ -1005,6 +1005,11 @@ static inline bool ufshcd_is_wb_allowed(struct ufs_h= ba *hba) return hba->caps & UFSHCD_CAP_WB_EN; } =20 +static inline bool ufshcd_is_crypto_supported(struct ufs_hba *hba) +{ + return hba->caps & UFSHCD_CAP_CRYPTO; +} + #define ufshcd_writel(hba, val, reg) \ writel((val), (hba)->mmio_base + (reg)) #define ufshcd_readl(hba, reg) \ --=20 2.31.0 From nobody Sat Sep 21 20:00:36 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8EB14C19F29 for ; Fri, 29 Jul 2022 02:05:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233916AbiG2CFn (ORCPT ); Thu, 28 Jul 2022 22:05:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59592 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233915AbiG2CFk (ORCPT ); Thu, 28 Jul 2022 22:05:40 -0400 Received: from mail-pl1-x62e.google.com (mail-pl1-x62e.google.com [IPv6:2607:f8b0:4864:20::62e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4B26479EDB for ; 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[122.107.196.14]) by smtp.gmail.com with ESMTPSA id y124-20020a62ce82000000b005258df7615bsm1571901pfg.0.2022.07.28.19.05.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Jul 2022 19:05:35 -0700 (PDT) From: Daniil Lunev To: Adrian Hunter , Bart Van Assche , Greg Kroah-Hartman Cc: Daniil Lunev , Alim Akhtar , Avri Altman , Bean Huo , Can Guo , Daejun Park , "James E.J. Bottomley" , "Martin K. Petersen" , Mauro Carvalho Chehab , Sohaib Mohamed , linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org Subject: [PATCH v3 2/2] ufs: core: print UFSHCD capabilities in controller's sysfs node Date: Fri, 29 Jul 2022 12:05:08 +1000 Message-Id: <20220729120216.v3.2.Ibf9efc9be50783eeee55befa2270b7d38552354c@changeid> X-Mailer: git-send-email 2.31.0 In-Reply-To: <20220729020508.4147751-1-dlunev@chromium.org> References: <20220729020508.4147751-1-dlunev@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Allows userspace to check if Clock Scaling, Write Booster and Inline Crypto Engine functionality can be enabled. Signed-off-by: Daniil Lunev --- Changes in v3: * Expose each capability individually. * Update documentation to represent new scheme. Changes in v2: * Add documentation entry for the new sysfs node. Documentation/ABI/testing/sysfs-driver-ufs | 39 ++++++++++++++++++++ drivers/ufs/core/ufs-sysfs.c | 41 ++++++++++++++++++++++ 2 files changed, 80 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-driver-ufs b/Documentation/ABI= /testing/sysfs-driver-ufs index 6b248abb1bd71..805d76f7d7aef 100644 --- a/Documentation/ABI/testing/sysfs-driver-ufs +++ b/Documentation/ABI/testing/sysfs-driver-ufs @@ -1591,6 +1591,45 @@ Description: This entry shows the status of HPB. =20 The file is read only. =20 +What: /sys/bus/platform/drivers/ufshcd/*/capabilities/clock_scaling +What: /sys/bus/platform/devices/*.ufs/capabilities/clock_scaling +Date: July 2022 +Contact: Daniil Lunev +Description: Indicates status of clock scaling. + + =3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D + 0 Clock scaling is not enabled. + 1 Clock scaling is enabled. + =3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D + + The file is read only. + +What: /sys/bus/platform/drivers/ufshcd/*/capabilities/write_booster +What: /sys/bus/platform/devices/*.ufs/capabilities/write_booster +Date: July 2022 +Contact: Daniil Lunev +Description: Indicates status of Write Booster. + + =3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D + 0 Write Booster can not be enabled. + 1 Write Booster can be enabled. + =3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D + + The file is read only. + +What: /sys/bus/platform/drivers/ufshcd/*/capabilities/crypto +What: /sys/bus/platform/devices/*.ufs/capabilities/crypto +Date: July 2022 +Contact: Daniil Lunev +Description: Indicates status of Inline Crypto Engine support. + + =3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D + 0 Inline Crypto Engine can not be used. + 1 Inline Crypto Engine can be used. + =3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D + + The file is read only. + What: /sys/class/scsi_device/*/device/hpb_param_sysfs/activation_thld Date: February 2021 Contact: Avri Altman diff --git a/drivers/ufs/core/ufs-sysfs.c b/drivers/ufs/core/ufs-sysfs.c index 0a088b47d5570..4a3e58d545fe5 100644 --- a/drivers/ufs/core/ufs-sysfs.c +++ b/drivers/ufs/core/ufs-sysfs.c @@ -279,6 +279,46 @@ static const struct attribute_group ufs_sysfs_default_= group =3D { .attrs =3D ufs_sysfs_ufshcd_attrs, }; =20 +static ssize_t clock_scaling_show(struct device *dev, struct device_attrib= ute *attr, + char *buf) +{ + struct ufs_hba *hba =3D dev_get_drvdata(dev); + + return sysfs_emit(buf, "%d\n", ufshcd_is_clkscaling_supported(hba)); +} + +static ssize_t write_booster_show(struct device *dev, struct device_attrib= ute *attr, + char *buf) +{ + struct ufs_hba *hba =3D dev_get_drvdata(dev); + + return sysfs_emit(buf, "%d\n", ufshcd_is_wb_allowed(hba)); +} + +static ssize_t crypto_show(struct device *dev, struct device_attribute *at= tr, + char *buf) +{ + struct ufs_hba *hba =3D dev_get_drvdata(dev); + + return sysfs_emit(buf, "%d\n", ufshcd_is_crypto_supported(hba)); +} + +static DEVICE_ATTR_RO(clock_scaling); +static DEVICE_ATTR_RO(write_booster); +static DEVICE_ATTR_RO(crypto); + +static struct attribute *ufs_sysfs_capabilities_attrs[] =3D { + &dev_attr_clock_scaling.attr, + &dev_attr_write_booster.attr, + &dev_attr_crypto.attr, + NULL +}; + +static const struct attribute_group ufs_sysfs_capabilities_group =3D { + .name =3D "capabilities", + .attrs =3D ufs_sysfs_capabilities_attrs, +}; + static ssize_t monitor_enable_show(struct device *dev, struct device_attribute *attr, char *buf) { @@ -1134,6 +1174,7 @@ static const struct attribute_group ufs_sysfs_attribu= tes_group =3D { =20 static const struct attribute_group *ufs_sysfs_groups[] =3D { &ufs_sysfs_default_group, + &ufs_sysfs_capabilities_group, &ufs_sysfs_monitor_group, &ufs_sysfs_device_descriptor_group, &ufs_sysfs_interconnect_descriptor_group, --=20 2.31.0