From nobody Wed Apr 15 00:20:29 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 887E0C19F2B for ; Thu, 28 Jul 2022 18:21:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232689AbiG1SVr (ORCPT ); Thu, 28 Jul 2022 14:21:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51838 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232392AbiG1SVo (ORCPT ); Thu, 28 Jul 2022 14:21:44 -0400 Received: from mx0.riseup.net (mx0.riseup.net [198.252.153.6]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 10CE95A8B3 for ; Thu, 28 Jul 2022 11:21:44 -0700 (PDT) Received: from fews1.riseup.net (fews1-pn.riseup.net [10.0.1.83]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256 client-signature RSA-PSS (2048 bits) client-digest SHA256) (Client CN "mail.riseup.net", Issuer "R3" (not verified)) by mx0.riseup.net (Postfix) with ESMTPS id 4LtzWC2zrqz9spX; Thu, 28 Jul 2022 18:21:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=riseup.net; s=squak; t=1659032503; bh=jaNzaNvCEhS2AXkA7K80CoMdT/QIxgViEtzB1k8nm5g=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=p+4XtFahyDtTKE3LGYXkAiHihWm/wNd22PbpsULP1ZyPzLnxUdKy7CeX6r9JDkKeE n+FD6m2ca5/z1y01UA71w0bZKTDAKe5WKygOQ8XtR1L+/GCfMxUuFjCQeLghKJvI05 zGYgXbEkCNhUQflwg5/eqH14ObCKotV2BCmJBtLQ= X-Riseup-User-ID: 7085B217FDD4BF70B4736E5A2DFB7BA16FA17F0EC436EF3BDB26F2BC14E00E67 Received: from [127.0.0.1] (localhost [127.0.0.1]) by fews1.riseup.net (Postfix) with ESMTPSA id 4LtzW61d0Hz5vMX; Thu, 28 Jul 2022 18:21:37 +0000 (UTC) From: =?UTF-8?q?Ma=C3=ADra=20Canal?= To: Harry Wentland , Leo Li , Rodrigo Siqueira , Alex Deucher , christian.koenig@amd.com, Xinhui.Pan@amd.com, David Airlie , Daniel Vetter Cc: amd-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, mwen@igalia.com, andrealmeid@riseup.net, Isabella Basso , magalilemes00@gmail.com, tales.aparecida@gmail.com, =?UTF-8?q?Ma=C3=ADra=20Canal?= Subject: [PATCH 01/16] drm/amd/display: Remove NonUrgentLatencyTolerance VBA variable Date: Thu, 28 Jul 2022 15:20:33 -0300 Message-Id: <20220728182047.264825-2-mairacanal@riseup.net> In-Reply-To: <20220728182047.264825-1-mairacanal@riseup.net> References: <20220728182047.264825-1-mairacanal@riseup.net> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The NonUrgentLatencyTolerance variable from the struct vba_vars_st is only used on assignments, so its value is not used on code. Moreover, its getter function is not used also. So, remove the NonUrgentLatencyTolerance entry from the struct vba_vars_st. Signed-off-by: Ma=C3=ADra Canal --- .../gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c | 4 ---- .../gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c | 4 ---- drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c | 1 - drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h | 2 -- 4 files changed, 11 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c= b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c index d3b5b6fedf04..8a499f8066b7 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c @@ -1768,10 +1768,6 @@ static void dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefet= chParametersWatermarksAndPer mode_lib->vba.UrgentLatencySupportUs[k]); } =20 - // Non-Urgent Latency Tolerance - mode_lib->vba.NonUrgentLatencyTolerance =3D mode_lib->vba.MinUrgentLatenc= ySupportUs - - mode_lib->vba.UrgentWatermark; - // DSCCLK for (k =3D 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { if ((mode_lib->vba.BlendingAndTiming[k] !=3D k) || !mode_lib->vba.DSCEna= bled[k]) { diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2= .c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c index 63bbdf8b8678..ef7f0b8ed2d5 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c @@ -1804,10 +1804,6 @@ static void dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPref= etchParametersWatermarksAndP mode_lib->vba.UrgentLatencySupportUs[k]); } =20 - // Non-Urgent Latency Tolerance - mode_lib->vba.NonUrgentLatencyTolerance =3D mode_lib->vba.MinUrgentLatenc= ySupportUs - - mode_lib->vba.UrgentWatermark; - // DSCCLK for (k =3D 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { if ((mode_lib->vba.BlendingAndTiming[k] !=3D k) || !mode_lib->vba.DSCEna= bled[k]) { diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c b/driver= s/gpu/drm/amd/display/dc/dml/display_mode_vba.c index 503e7d984ff0..5dc2f52165fb 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c +++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c @@ -102,7 +102,6 @@ dml_get_attr_func(stutter_efficiency_no_vblank, mode_li= b->vba.StutterEfficiencyN dml_get_attr_func(stutter_period, mode_lib->vba.StutterPeriod); dml_get_attr_func(urgent_latency, mode_lib->vba.UrgentLatency); dml_get_attr_func(urgent_extra_latency, mode_lib->vba.UrgentExtraLatency); -dml_get_attr_func(nonurgent_latency, mode_lib->vba.NonUrgentLatencyToleran= ce); dml_get_attr_func(dram_clock_change_latency, mode_lib->vba.MinActiveDRAMCl= ockChangeLatencySupported); dml_get_attr_func(dispclk_calculated, mode_lib->vba.DISPCLK_calculated); dml_get_attr_func(total_data_read_bw, mode_lib->vba.TotalDataReadBandwidth= ); diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h b/driver= s/gpu/drm/amd/display/dc/dml/display_mode_vba.h index 8460aefe7b6d..cb125f7d0814 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h +++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h @@ -50,7 +50,6 @@ dml_get_attr_decl(stutter_efficiency); dml_get_attr_decl(stutter_period); dml_get_attr_decl(urgent_latency); dml_get_attr_decl(urgent_extra_latency); -dml_get_attr_decl(nonurgent_latency); dml_get_attr_decl(dram_clock_change_latency); dml_get_attr_decl(dispclk_calculated); dml_get_attr_decl(total_data_read_bw); @@ -648,7 +647,6 @@ struct vba_vars_st { double WritebackDRAMClockChangeWatermark; double StutterEfficiency; double StutterEfficiencyNotIncludingVBlank; - double NonUrgentLatencyTolerance; double MinActiveDRAMClockChangeLatencySupported; double Z8StutterEfficiencyBestCase; unsigned int Z8NumberOfStutterBurstsPerFrameBestCase; --=20 2.37.1 From nobody Wed Apr 15 00:20:29 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 231B1C04A68 for ; Thu, 28 Jul 2022 18:22:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232839AbiG1SWC (ORCPT ); Thu, 28 Jul 2022 14:22:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52204 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232392AbiG1SV5 (ORCPT ); Thu, 28 Jul 2022 14:21:57 -0400 Received: from mx1.riseup.net (mx1.riseup.net [198.252.153.129]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3B3F574DE0 for ; Thu, 28 Jul 2022 11:21:51 -0700 (PDT) Received: from fews1.riseup.net (fews1-pn.riseup.net [10.0.1.83]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256 client-signature RSA-PSS (2048 bits) client-digest SHA256) (Client CN "mail.riseup.net", Issuer "R3" (not verified)) by mx1.riseup.net (Postfix) with ESMTPS id 4LtzWL4g4NzDryt; Thu, 28 Jul 2022 18:21:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=riseup.net; s=squak; t=1659032510; bh=dOc0h9A9+TLSSc0lCI/yNseuodcICoVaSAtd2WgMo0w=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=tO0UfFSsv6mnmmzOZaOJ6Dr/G614Ee99NzciEXbTQ9u8mp1/LKL1ccVDpPZP0nzTZ NLWbktGbSJkq7k9BBMs0vrJUw8fQptPWirTf0r8/UPptVKdG9cHLub55g2eu3NgaBz +VC24M3OkFakTqDHIyQjvbQBKOkSdodNI0Rr3/hk= X-Riseup-User-ID: 4D0DE29A87800F0FBEFA4C6F967DE3A6FA7B671924CE920BA49D2ED64E91A686 Received: from [127.0.0.1] (localhost [127.0.0.1]) by fews1.riseup.net (Postfix) with ESMTPSA id 4LtzWF275dz5vMX; Thu, 28 Jul 2022 18:21:45 +0000 (UTC) From: =?UTF-8?q?Ma=C3=ADra=20Canal?= To: Harry Wentland , Leo Li , Rodrigo Siqueira , Alex Deucher , christian.koenig@amd.com, Xinhui.Pan@amd.com, David Airlie , Daniel Vetter Cc: amd-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, mwen@igalia.com, andrealmeid@riseup.net, Isabella Basso , magalilemes00@gmail.com, tales.aparecida@gmail.com, =?UTF-8?q?Ma=C3=ADra=20Canal?= Subject: [PATCH 02/16] drm/amd/display: Remove CompBufReservedSpace* VBA variable Date: Thu, 28 Jul 2022 15:20:34 -0300 Message-Id: <20220728182047.264825-3-mairacanal@riseup.net> In-Reply-To: <20220728182047.264825-1-mairacanal@riseup.net> References: <20220728182047.264825-1-mairacanal@riseup.net> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The variables CompBufReservedSpaceZs, CompBufReservedSpace64B and CompBufReservedSpaceNeedAdjustment from the struct vba_vars_st are only used on assignments, so their values are not used on code. Moreover, their getter functions are not used also. So, remove the variables entries from the struct vba_vars_st. Signed-off-by: Ma=C3=ADra Canal --- .../gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c | 3 --- drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c | 2 -- drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h | 5 ----- 3 files changed, 10 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c= b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c index 573504de1789..a1fb2d1d1cdb 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c @@ -307,9 +307,6 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParamet= ersWatermarksAndPerforman .dummy_boolean); /* bool *ViewportSizeSupport */ } =20 - v->CompBufReservedSpaceZs =3D v->CompBufReservedSpaceKBytes * 1024.0 = / 256.0; - v->CompBufReservedSpace64B =3D v->CompBufReservedSpaceKBytes * 1024.0 = / 64.0; - // DCFCLK Deep Sleep dml32_CalculateDCFCLKDeepSleep( mode_lib->vba.NumberOfActiveSurfaces, diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c b/driver= s/gpu/drm/amd/display/dc/dml/display_mode_vba.c index 5dc2f52165fb..d1c720b48b0c 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c +++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c @@ -122,8 +122,6 @@ dml_get_attr_func(fclk_watermark, mode_lib->vba.Waterma= rk.FCLKChangeWatermark); dml_get_attr_func(usr_retraining_watermark, mode_lib->vba.Watermark.USRRet= rainingWatermark); =20 dml_get_attr_func(comp_buffer_reserved_space_kbytes, mode_lib->vba.CompBuf= ReservedSpaceKBytes); -dml_get_attr_func(comp_buffer_reserved_space_64bytes, mode_lib->vba.CompBu= fReservedSpace64B); -dml_get_attr_func(comp_buffer_reserved_space_zs, mode_lib->vba.CompBufRese= rvedSpaceZs); dml_get_attr_func(unbounded_request_enabled, mode_lib->vba.UnboundedReques= tEnabled); =20 #define dml_get_pipe_attr_func(attr, var) double get_##attr(struct displa= y_mode_lib *mode_lib, const display_e2e_pipe_params_st *pipes, unsigned int= num_pipes, unsigned int which_pipe) \ diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h b/driver= s/gpu/drm/amd/display/dc/dml/display_mode_vba.h index cb125f7d0814..632041cf49bb 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h +++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h @@ -67,8 +67,6 @@ dml_get_attr_decl(min_meta_chunk_size_in_byte); dml_get_attr_decl(fclk_watermark); dml_get_attr_decl(usr_retraining_watermark); dml_get_attr_decl(comp_buffer_reserved_space_kbytes); -dml_get_attr_decl(comp_buffer_reserved_space_64bytes); -dml_get_attr_decl(comp_buffer_reserved_space_zs); dml_get_attr_decl(unbounded_request_enabled); =20 #define dml_get_pipe_attr_decl(attr) double get_##attr(struct display_mode= _lib *mode_lib, const display_e2e_pipe_params_st *pipes, unsigned int num_p= ipes, unsigned int which_pipe) @@ -655,9 +653,6 @@ struct vba_vars_st { Watermarks Watermark; bool DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE; unsigned int CompBufReservedSpaceKBytes; - unsigned int CompBufReservedSpace64B; - unsigned int CompBufReservedSpaceZs; - bool CompBufReservedSpaceNeedAdjustment; =20 // These are the clocks calcuated by the library but they are not actually // used explicitly. They are fetched by tests and then possibly used. The --=20 2.37.1 From nobody Wed Apr 15 00:20:29 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 94F43C04A68 for ; Thu, 28 Jul 2022 18:22:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232874AbiG1SWZ (ORCPT ); Thu, 28 Jul 2022 14:22:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52670 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232873AbiG1SWR (ORCPT ); Thu, 28 Jul 2022 14:22:17 -0400 Received: from mx1.riseup.net (mx1.riseup.net [198.252.153.129]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7265974DD7 for ; Thu, 28 Jul 2022 11:22:00 -0700 (PDT) Received: from fews1.riseup.net (fews1-pn.riseup.net [10.0.1.83]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256 client-signature RSA-PSS (2048 bits) client-digest SHA256) (Client CN "mail.riseup.net", Issuer "R3" (not verified)) by mx1.riseup.net (Postfix) with ESMTPS id 4LtzWW5pclzDrsv; Thu, 28 Jul 2022 18:21:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=riseup.net; s=squak; t=1659032520; bh=QMtsyfZF/nIiDPU4bNM66nWjTtCfP/1/QyZw8VmKob0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=flS4PEKCoHxOXfKzsPHe4Rx8oNXoEkGVEoRjJsq43FQuWL/22vb3QWDCrWQEJZ3uz WA8q9QpAilrDO1kIEy+8Bd70WURJ/aKVzoYrLtkHebEkXH+HEtG4gzbHlJc8975iuv RT6GcZl3UdkhD5t5bmkPCpG0+cPStQKvOMqD0Row= X-Riseup-User-ID: FFDC12B4A70B55D8FB8484FF0FF883B8DE66B3BF7FB6F1F1EF61AB0337F6FFBC Received: from [127.0.0.1] (localhost [127.0.0.1]) by fews1.riseup.net (Postfix) with ESMTPSA id 4LtzWQ3hBpz5vMX; Thu, 28 Jul 2022 18:21:54 +0000 (UTC) From: =?UTF-8?q?Ma=C3=ADra=20Canal?= To: Harry Wentland , Leo Li , Rodrigo Siqueira , Alex Deucher , christian.koenig@amd.com, Xinhui.Pan@amd.com, David Airlie , Daniel Vetter Cc: amd-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, mwen@igalia.com, andrealmeid@riseup.net, Isabella Basso , magalilemes00@gmail.com, tales.aparecida@gmail.com, =?UTF-8?q?Ma=C3=ADra=20Canal?= Subject: [PATCH 03/16] drm/amd/display: Remove DSCCLK_calculated VBA variable Date: Thu, 28 Jul 2022 15:20:35 -0300 Message-Id: <20220728182047.264825-4-mairacanal@riseup.net> In-Reply-To: <20220728182047.264825-1-mairacanal@riseup.net> References: <20220728182047.264825-1-mairacanal@riseup.net> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The DSCCLK_calculated variable from the struct vba_vars_st is only used on assignments, so its value is not used on code. Moreover, its getter function is not used also. So, remove the DSCCLK_calculated entry from the struct vba_vars_st. Signed-off-by: Ma=C3=ADra Canal --- .../dc/dml/dcn20/display_mode_vba_20.c | 21 ++---------------- .../dc/dml/dcn20/display_mode_vba_20v2.c | 21 ++---------------- .../dc/dml/dcn21/display_mode_vba_21.c | 18 +-------------- .../dc/dml/dcn30/display_mode_vba_30.c | 19 ++-------------- .../dc/dml/dcn31/display_mode_vba_31.c | 19 ++-------------- .../dc/dml/dcn314/display_mode_vba_314.c | 19 ++-------------- .../dc/dml/dcn32/display_mode_vba_32.c | 22 ++----------------- .../drm/amd/display/dc/dml/display_mode_vba.c | 1 - .../drm/amd/display/dc/dml/display_mode_vba.h | 2 -- 9 files changed, 13 insertions(+), 129 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c= b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c index 8a499f8066b7..37a8b418a24d 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c @@ -1770,28 +1770,11 @@ static void dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefe= tchParametersWatermarksAndPer =20 // DSCCLK for (k =3D 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { - if ((mode_lib->vba.BlendingAndTiming[k] !=3D k) || !mode_lib->vba.DSCEna= bled[k]) { - mode_lib->vba.DSCCLK_calculated[k] =3D 0.0; - } else { - if (mode_lib->vba.OutputFormat[k] =3D=3D dm_420 - || mode_lib->vba.OutputFormat[k] =3D=3D dm_n422) + if ((mode_lib->vba.BlendingAndTiming[k] =3D=3D k) || mode_lib->vba.DSCEn= abled[k]) { + if (mode_lib->vba.OutputFormat[k] =3D=3D dm_420 || mode_lib->vba.Output= Format[k] =3D=3D dm_n422) mode_lib->vba.DSCFormatFactor =3D 2; else mode_lib->vba.DSCFormatFactor =3D 1; - if (mode_lib->vba.ODMCombineEnabled[k]) - mode_lib->vba.DSCCLK_calculated[k] =3D - mode_lib->vba.PixelClockBackEnd[k] / 6 - / mode_lib->vba.DSCFormatFactor - / (1 - - mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading - / 100); - else - mode_lib->vba.DSCCLK_calculated[k] =3D - mode_lib->vba.PixelClockBackEnd[k] / 3 - / mode_lib->vba.DSCFormatFactor - / (1 - - mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading - / 100); } } =20 diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2= .c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c index ef7f0b8ed2d5..0e0697326717 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c @@ -1806,28 +1806,11 @@ static void dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPre= fetchParametersWatermarksAndP =20 // DSCCLK for (k =3D 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { - if ((mode_lib->vba.BlendingAndTiming[k] !=3D k) || !mode_lib->vba.DSCEna= bled[k]) { - mode_lib->vba.DSCCLK_calculated[k] =3D 0.0; - } else { - if (mode_lib->vba.OutputFormat[k] =3D=3D dm_420 - || mode_lib->vba.OutputFormat[k] =3D=3D dm_n422) + if ((mode_lib->vba.BlendingAndTiming[k] =3D=3D k) || mode_lib->vba.DSCEn= abled[k]) { + if (mode_lib->vba.OutputFormat[k] =3D=3D dm_420 || mode_lib->vba.Output= Format[k] =3D=3D dm_n422) mode_lib->vba.DSCFormatFactor =3D 2; else mode_lib->vba.DSCFormatFactor =3D 1; - if (mode_lib->vba.ODMCombineEnabled[k]) - mode_lib->vba.DSCCLK_calculated[k] =3D - mode_lib->vba.PixelClockBackEnd[k] / 6 - / mode_lib->vba.DSCFormatFactor - / (1 - - mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading - / 100); - else - mode_lib->vba.DSCCLK_calculated[k] =3D - mode_lib->vba.PixelClockBackEnd[k] / 3 - / mode_lib->vba.DSCFormatFactor - / (1 - - mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading - / 100); } } =20 diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c= b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c index 8a7485e21d53..aa752d78308f 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c @@ -1764,28 +1764,12 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchPar= ametersWatermarksAndPerforman =20 // DSCCLK for (k =3D 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { - if ((mode_lib->vba.BlendingAndTiming[k] !=3D k) || !mode_lib->vba.DSCEna= bled[k]) { - locals->DSCCLK_calculated[k] =3D 0.0; - } else { + if ((mode_lib->vba.BlendingAndTiming[k] =3D=3D k) || mode_lib->vba.DSCEn= abled[k]) { if (mode_lib->vba.OutputFormat[k] =3D=3D dm_420 || mode_lib->vba.OutputFormat[k] =3D=3D dm_n422) mode_lib->vba.DSCFormatFactor =3D 2; else mode_lib->vba.DSCFormatFactor =3D 1; - if (mode_lib->vba.ODMCombineEnabled[k]) - locals->DSCCLK_calculated[k] =3D - mode_lib->vba.PixelClockBackEnd[k] / 6 - / mode_lib->vba.DSCFormatFactor - / (1 - - mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading - / 100); - else - locals->DSCCLK_calculated[k] =3D - mode_lib->vba.PixelClockBackEnd[k] / 3 - / mode_lib->vba.DSCFormatFactor - / (1 - - mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading - / 100); } } =20 diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c= b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c index 876b321b30ca..cc9b6497b287 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c @@ -2159,26 +2159,11 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchPar= ametersWatermarksAndPerforman =20 // DSCCLK for (k =3D 0; k < v->NumberOfActivePlanes; ++k) { - if ((v->BlendingAndTiming[k] !=3D k) || !v->DSCEnabled[k]) { - v->DSCCLK_calculated[k] =3D 0.0; - } else { - if (v->OutputFormat[k] =3D=3D dm_420) - v->DSCFormatFactor =3D 2; - else if (v->OutputFormat[k] =3D=3D dm_444) - v->DSCFormatFactor =3D 1; - else if (v->OutputFormat[k] =3D=3D dm_n422) + if ((v->BlendingAndTiming[k] =3D=3D k) || v->DSCEnabled[k]) { + if (v->OutputFormat[k] =3D=3D dm_420 || v->OutputFormat[k] =3D=3D dm_n4= 22) v->DSCFormatFactor =3D 2; else v->DSCFormatFactor =3D 1; - if (v->ODMCombineEnabled[k] =3D=3D dm_odm_combine_mode_4to1) - v->DSCCLK_calculated[k] =3D v->PixelClockBackEnd[k] / 12 - / v->DSCFormatFactor / (1 - v->DISPCLKDPPCLKDSCCLKDownSpreading / 100= ); - else if (v->ODMCombineEnabled[k] =3D=3D dm_odm_combine_mode_2to1) - v->DSCCLK_calculated[k] =3D v->PixelClockBackEnd[k] / 6 - / v->DSCFormatFactor / (1 - v->DISPCLKDPPCLKDSCCLKDownSpreading / 100= ); - else - v->DSCCLK_calculated[k] =3D v->PixelClockBackEnd[k] / 3 - / v->DSCFormatFactor / (1 - v->DISPCLKDPPCLKDSCCLKDownSpreading / 100= ); } } =20 diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c= b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c index 3fab19134480..55ab4ec8b8fa 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c @@ -2286,26 +2286,11 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchPar= ametersWatermarksAndPerforman =20 // DSCCLK for (k =3D 0; k < v->NumberOfActivePlanes; ++k) { - if ((v->BlendingAndTiming[k] !=3D k) || !v->DSCEnabled[k]) { - v->DSCCLK_calculated[k] =3D 0.0; - } else { - if (v->OutputFormat[k] =3D=3D dm_420) - v->DSCFormatFactor =3D 2; - else if (v->OutputFormat[k] =3D=3D dm_444) - v->DSCFormatFactor =3D 1; - else if (v->OutputFormat[k] =3D=3D dm_n422) + if ((v->BlendingAndTiming[k] =3D=3D k) || v->DSCEnabled[k]) { + if (v->OutputFormat[k] =3D=3D dm_420 || v->OutputFormat[k] =3D=3D dm_n4= 22) v->DSCFormatFactor =3D 2; else v->DSCFormatFactor =3D 1; - if (v->ODMCombineEnabled[k] =3D=3D dm_odm_combine_mode_4to1) - v->DSCCLK_calculated[k] =3D v->PixelClockBackEnd[k] / 12 / v->DSCForma= tFactor - / (1 - v->DISPCLKDPPCLKDSCCLKDownSpreading / 100); - else if (v->ODMCombineEnabled[k] =3D=3D dm_odm_combine_mode_2to1) - v->DSCCLK_calculated[k] =3D v->PixelClockBackEnd[k] / 6 / v->DSCFormat= Factor - / (1 - v->DISPCLKDPPCLKDSCCLKDownSpreading / 100); - else - v->DSCCLK_calculated[k] =3D v->PixelClockBackEnd[k] / 3 / v->DSCFormat= Factor - / (1 - v->DISPCLKDPPCLKDSCCLKDownSpreading / 100); } } =20 diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314= .c b/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c index fc4d7474c111..279ed038a359 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c @@ -2310,26 +2310,11 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchPar= ametersWatermarksAndPerforman =20 // DSCCLK for (k =3D 0; k < v->NumberOfActivePlanes; ++k) { - if ((v->BlendingAndTiming[k] !=3D k) || !v->DSCEnabled[k]) { - v->DSCCLK_calculated[k] =3D 0.0; - } else { - if (v->OutputFormat[k] =3D=3D dm_420) - v->DSCFormatFactor =3D 2; - else if (v->OutputFormat[k] =3D=3D dm_444) - v->DSCFormatFactor =3D 1; - else if (v->OutputFormat[k] =3D=3D dm_n422) + if ((v->BlendingAndTiming[k] =3D=3D k) || v->DSCEnabled[k]) { + if (v->OutputFormat[k] =3D=3D dm_420 || v->OutputFormat[k] =3D=3D dm_n4= 22) v->DSCFormatFactor =3D 2; else v->DSCFormatFactor =3D 1; - if (v->ODMCombineEnabled[k] =3D=3D dm_odm_combine_mode_4to1) - v->DSCCLK_calculated[k] =3D v->PixelClockBackEnd[k] / 12 / v->DSCForma= tFactor - / (1 - v->DISPCLKDPPCLKDSCCLKDownSpreading / 100); - else if (v->ODMCombineEnabled[k] =3D=3D dm_odm_combine_mode_2to1) - v->DSCCLK_calculated[k] =3D v->PixelClockBackEnd[k] / 6 / v->DSCFormat= Factor - / (1 - v->DISPCLKDPPCLKDSCCLKDownSpreading / 100); - else - v->DSCCLK_calculated[k] =3D v->PixelClockBackEnd[k] / 3 / v->DSCFormat= Factor - / (1 - v->DISPCLKDPPCLKDSCCLKDownSpreading / 100); } } =20 diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c= b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c index a1fb2d1d1cdb..f199ef475ed0 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c @@ -332,29 +332,11 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParam= etersWatermarksAndPerforman =20 // DSCCLK for (k =3D 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) { - if ((mode_lib->vba.BlendingAndTiming[k] !=3D k) || !mode_lib->vba.DSCEna= bled[k]) { - v->DSCCLK_calculated[k] =3D 0.0; - } else { - if (mode_lib->vba.OutputFormat[k] =3D=3D dm_420) - mode_lib->vba.DSCFormatFactor =3D 2; - else if (mode_lib->vba.OutputFormat[k] =3D=3D dm_444) - mode_lib->vba.DSCFormatFactor =3D 1; - else if (mode_lib->vba.OutputFormat[k] =3D=3D dm_n422) + if ((mode_lib->vba.BlendingAndTiming[k] =3D=3D k) || mode_lib->vba.DSCEn= abled[k]) { + if (mode_lib->vba.OutputFormat[k] =3D=3D dm_420 || mode_lib->vba.Output= Format[k] =3D=3D dm_n422) mode_lib->vba.DSCFormatFactor =3D 2; else mode_lib->vba.DSCFormatFactor =3D 1; - if (mode_lib->vba.ODMCombineEnabled[k] =3D=3D dm_odm_combine_mode_4to1) - v->DSCCLK_calculated[k] =3D mode_lib->vba.PixelClockBackEnd[k] / 12 - / mode_lib->vba.DSCFormatFactor - / (1 - mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100); - else if (mode_lib->vba.ODMCombineEnabled[k] =3D=3D dm_odm_combine_mode_= 2to1) - v->DSCCLK_calculated[k] =3D mode_lib->vba.PixelClockBackEnd[k] / 6 - / mode_lib->vba.DSCFormatFactor - / (1 - mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100); - else - v->DSCCLK_calculated[k] =3D mode_lib->vba.PixelClockBackEnd[k] / 3 - / mode_lib->vba.DSCFormatFactor - / (1 - mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100); } } =20 diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c b/driver= s/gpu/drm/amd/display/dc/dml/display_mode_vba.c index d1c720b48b0c..316153ece160 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c +++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c @@ -134,7 +134,6 @@ dml_get_attr_func(unbounded_request_enabled, mode_lib->= vba.UnboundedRequestEnabl =20 dml_get_pipe_attr_func(dsc_delay, mode_lib->vba.DSCDelay); dml_get_pipe_attr_func(dppclk_calculated, mode_lib->vba.DPPCLK_calculated); -dml_get_pipe_attr_func(dscclk_calculated, mode_lib->vba.DSCCLK_calculated); dml_get_pipe_attr_func(min_ttu_vblank, mode_lib->vba.MinTTUVBlank); dml_get_pipe_attr_func(min_ttu_vblank_in_us, mode_lib->vba.MinTTUVBlank); dml_get_pipe_attr_func(vratio_prefetch_l, mode_lib->vba.VRatioPrefetchY); diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h b/driver= s/gpu/drm/amd/display/dc/dml/display_mode_vba.h index 632041cf49bb..1b037e74bfc3 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h +++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h @@ -73,7 +73,6 @@ dml_get_attr_decl(unbounded_request_enabled); =20 dml_get_pipe_attr_decl(dsc_delay); dml_get_pipe_attr_decl(dppclk_calculated); -dml_get_pipe_attr_decl(dscclk_calculated); dml_get_pipe_attr_decl(min_ttu_vblank); dml_get_pipe_attr_decl(min_ttu_vblank_in_us); dml_get_pipe_attr_decl(vratio_prefetch_l); @@ -1033,7 +1032,6 @@ struct vba_vars_st { double PrefetchSourceLinesC[DC__NUM_DPP__MAX]; double PSCL_THROUGHPUT_LUMA[DC__NUM_DPP__MAX]; double PSCL_THROUGHPUT_CHROMA[DC__NUM_DPP__MAX]; - double DSCCLK_calculated[DC__NUM_DPP__MAX]; unsigned int DSCDelay[DC__NUM_DPP__MAX]; unsigned int MaxVStartupLines[DC__NUM_DPP__MAX]; double DPPCLKUsingSingleDPP[DC__NUM_DPP__MAX]; --=20 2.37.1 From nobody Wed Apr 15 00:20:29 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 28094C04A68 for ; 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a=rsa-sha256; c=relaxed/simple; d=riseup.net; s=squak; t=1659032527; bh=ULERFfGstbxBtAQTaHKUQLYZrmxPNfaIEUIUPJBi/EA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=BnprqY2GqInUKuGFUyQz5yKDJtZ9J9FMJaVkfgUHT0qxvII12biE4v/Uh1N+iF8WK MpwHKrkiwUTQOvA8B1oKrbsflhb8NDqqI8g7b7uCyDORXH76UCWnJwqnxYMfD35pvt 0mJUkRgq0zfMe7Eiq2+F+IYZOwegVxx8mRvzTX6c= X-Riseup-User-ID: FEA7B59F18588383CE8C6A0F199851147A55A7DCC6FDE9E800C802F57078A87B Received: from [127.0.0.1] (localhost [127.0.0.1]) by fews1.riseup.net (Postfix) with ESMTPSA id 4LtzWZ28syz5vMX; Thu, 28 Jul 2022 18:22:02 +0000 (UTC) From: =?UTF-8?q?Ma=C3=ADra=20Canal?= To: Harry Wentland , Leo Li , Rodrigo Siqueira , Alex Deucher , christian.koenig@amd.com, Xinhui.Pan@amd.com, David Airlie , Daniel Vetter Cc: amd-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, mwen@igalia.com, andrealmeid@riseup.net, Isabella Basso , magalilemes00@gmail.com, tales.aparecida@gmail.com, =?UTF-8?q?Ma=C3=ADra=20Canal?= Subject: [PATCH 04/16] drm/amd/display: Remove AllowDRAMSelfRefreshDuringVBlank VBA variable Date: Thu, 28 Jul 2022 15:20:36 -0300 Message-Id: <20220728182047.264825-5-mairacanal@riseup.net> In-Reply-To: <20220728182047.264825-1-mairacanal@riseup.net> References: <20220728182047.264825-1-mairacanal@riseup.net> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The AllowDRAMSelfRefreshDuringVBlank variable from the struct vba_vars_st is only used on assignments, so its value is not used on code. So, remove it the AllowDRAMSelfRefreshDuringVBlank entry from the struct vba_vars_st. Signed-off-by: Ma=C3=ADra Canal --- drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c | 3 --- .../gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c | 3 --- drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c | 3 --- drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c | 3 --- drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c | 3 --- .../gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c | 3 --- drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h | 1 - 7 files changed, 19 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c= b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c index 37a8b418a24d..d86d5c346e42 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c @@ -2350,7 +2350,6 @@ static void dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetc= hParametersWatermarksAndPer for (k =3D 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { if (mode_lib->vba.PrefetchMode[mode_lib->vba.VoltageLevel][mode_lib->vba= .maxMpcComb] =3D=3D 0) { mode_lib->vba.AllowDRAMClockChangeDuringVBlank[k] =3D true; - mode_lib->vba.AllowDRAMSelfRefreshDuringVBlank[k] =3D true; mode_lib->vba.MinTTUVBlank[k] =3D dml_max( mode_lib->vba.DRAMClockChangeWatermark, dml_max( @@ -2358,13 +2357,11 @@ static void dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefe= tchParametersWatermarksAndPer mode_lib->vba.UrgentWatermark)); } else if (mode_lib->vba.PrefetchMode[mode_lib->vba.VoltageLevel][mode_l= ib->vba.maxMpcComb] =3D=3D 1) { mode_lib->vba.AllowDRAMClockChangeDuringVBlank[k] =3D false; - mode_lib->vba.AllowDRAMSelfRefreshDuringVBlank[k] =3D true; mode_lib->vba.MinTTUVBlank[k] =3D dml_max( mode_lib->vba.StutterEnterPlusExitWatermark, mode_lib->vba.UrgentWatermark); } else { mode_lib->vba.AllowDRAMClockChangeDuringVBlank[k] =3D false; - mode_lib->vba.AllowDRAMSelfRefreshDuringVBlank[k] =3D false; mode_lib->vba.MinTTUVBlank[k] =3D mode_lib->vba.UrgentWatermark; } if (!mode_lib->vba.DynamicMetadataEnable[k]) diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2= .c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c index 0e0697326717..effd02574a0e 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c @@ -2384,7 +2384,6 @@ static void dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefe= tchParametersWatermarksAndP for (k =3D 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { if (mode_lib->vba.PrefetchMode[mode_lib->vba.VoltageLevel][mode_lib->vba= .maxMpcComb] =3D=3D 0) { mode_lib->vba.AllowDRAMClockChangeDuringVBlank[k] =3D true; - mode_lib->vba.AllowDRAMSelfRefreshDuringVBlank[k] =3D true; mode_lib->vba.MinTTUVBlank[k] =3D dml_max( mode_lib->vba.DRAMClockChangeWatermark, dml_max( @@ -2392,13 +2391,11 @@ static void dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPre= fetchParametersWatermarksAndP mode_lib->vba.UrgentWatermark)); } else if (mode_lib->vba.PrefetchMode[mode_lib->vba.VoltageLevel][mode_l= ib->vba.maxMpcComb] =3D=3D 1) { mode_lib->vba.AllowDRAMClockChangeDuringVBlank[k] =3D false; - mode_lib->vba.AllowDRAMSelfRefreshDuringVBlank[k] =3D true; mode_lib->vba.MinTTUVBlank[k] =3D dml_max( mode_lib->vba.StutterEnterPlusExitWatermark, mode_lib->vba.UrgentWatermark); } else { mode_lib->vba.AllowDRAMClockChangeDuringVBlank[k] =3D false; - mode_lib->vba.AllowDRAMSelfRefreshDuringVBlank[k] =3D false; mode_lib->vba.MinTTUVBlank[k] =3D mode_lib->vba.UrgentWatermark; } if (!mode_lib->vba.DynamicMetadataEnable[k]) diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c= b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c index aa752d78308f..ae03f1a3c9f0 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c @@ -2546,7 +2546,6 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParam= etersWatermarksAndPerforman for (k =3D 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { if (mode_lib->vba.PrefetchMode[mode_lib->vba.VoltageLevel][mode_lib->vba= .maxMpcComb] =3D=3D 0) { locals->AllowDRAMClockChangeDuringVBlank[k] =3D true; - locals->AllowDRAMSelfRefreshDuringVBlank[k] =3D true; locals->MinTTUVBlank[k] =3D dml_max( mode_lib->vba.DRAMClockChangeWatermark, dml_max( @@ -2554,13 +2553,11 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchPar= ametersWatermarksAndPerforman mode_lib->vba.UrgentWatermark)); } else if (mode_lib->vba.PrefetchMode[mode_lib->vba.VoltageLevel][mode_l= ib->vba.maxMpcComb] =3D=3D 1) { locals->AllowDRAMClockChangeDuringVBlank[k] =3D false; - locals->AllowDRAMSelfRefreshDuringVBlank[k] =3D true; locals->MinTTUVBlank[k] =3D dml_max( mode_lib->vba.StutterEnterPlusExitWatermark, mode_lib->vba.UrgentWatermark); } else { locals->AllowDRAMClockChangeDuringVBlank[k] =3D false; - locals->AllowDRAMSelfRefreshDuringVBlank[k] =3D false; locals->MinTTUVBlank[k] =3D mode_lib->vba.UrgentWatermark; } if (!mode_lib->vba.DynamicMetadataEnable[k]) diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c= b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c index cc9b6497b287..fe7fcb0d7b1f 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c @@ -2972,7 +2972,6 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParam= etersWatermarksAndPerforman for (k =3D 0; k < v->NumberOfActivePlanes; ++k) { if (PrefetchMode =3D=3D 0) { v->AllowDRAMClockChangeDuringVBlank[k] =3D true; - v->AllowDRAMSelfRefreshDuringVBlank[k] =3D true; v->MinTTUVBlank[k] =3D dml_max( v->DRAMClockChangeWatermark, dml_max( @@ -2980,13 +2979,11 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchPar= ametersWatermarksAndPerforman v->UrgentWatermark)); } else if (PrefetchMode =3D=3D 1) { v->AllowDRAMClockChangeDuringVBlank[k] =3D false; - v->AllowDRAMSelfRefreshDuringVBlank[k] =3D true; v->MinTTUVBlank[k] =3D dml_max( v->StutterEnterPlusExitWatermark, v->UrgentWatermark); } else { v->AllowDRAMClockChangeDuringVBlank[k] =3D false; - v->AllowDRAMSelfRefreshDuringVBlank[k] =3D false; v->MinTTUVBlank[k] =3D v->UrgentWatermark; } if (!v->DynamicMetadataEnable[k]) diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c= b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c index 55ab4ec8b8fa..eca05bbc0fb5 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c @@ -3185,17 +3185,14 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchPar= ametersWatermarksAndPerforman for (k =3D 0; k < v->NumberOfActivePlanes; ++k) { if (PrefetchMode =3D=3D 0) { v->AllowDRAMClockChangeDuringVBlank[k] =3D true; - v->AllowDRAMSelfRefreshDuringVBlank[k] =3D true; v->MinTTUVBlank[k] =3D dml_max( v->DRAMClockChangeWatermark, dml_max(v->StutterEnterPlusExitWatermark, v->UrgentWatermark)); } else if (PrefetchMode =3D=3D 1) { v->AllowDRAMClockChangeDuringVBlank[k] =3D false; - v->AllowDRAMSelfRefreshDuringVBlank[k] =3D true; v->MinTTUVBlank[k] =3D dml_max(v->StutterEnterPlusExitWatermark, v->Urg= entWatermark); } else { v->AllowDRAMClockChangeDuringVBlank[k] =3D false; - v->AllowDRAMSelfRefreshDuringVBlank[k] =3D false; v->MinTTUVBlank[k] =3D v->UrgentWatermark; } if (!v->DynamicMetadataEnable[k]) diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314= .c b/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c index 279ed038a359..acb47cdaaa05 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c @@ -3209,17 +3209,14 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchPar= ametersWatermarksAndPerforman for (k =3D 0; k < v->NumberOfActivePlanes; ++k) { if (PrefetchMode =3D=3D 0) { v->AllowDRAMClockChangeDuringVBlank[k] =3D true; - v->AllowDRAMSelfRefreshDuringVBlank[k] =3D true; v->MinTTUVBlank[k] =3D dml_max( v->DRAMClockChangeWatermark, dml_max(v->StutterEnterPlusExitWatermark, v->UrgentWatermark)); } else if (PrefetchMode =3D=3D 1) { v->AllowDRAMClockChangeDuringVBlank[k] =3D false; - v->AllowDRAMSelfRefreshDuringVBlank[k] =3D true; v->MinTTUVBlank[k] =3D dml_max(v->StutterEnterPlusExitWatermark, v->Urg= entWatermark); } else { v->AllowDRAMClockChangeDuringVBlank[k] =3D false; - v->AllowDRAMSelfRefreshDuringVBlank[k] =3D false; v->MinTTUVBlank[k] =3D v->UrgentWatermark; } if (!v->DynamicMetadataEnable[k]) diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h b/driver= s/gpu/drm/amd/display/dc/dml/display_mode_vba.h index 1b037e74bfc3..f03cf9cf9096 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h +++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h @@ -1004,7 +1004,6 @@ struct vba_vars_st { double DSTYAfterScaler[DC__NUM_DPP__MAX]; double DSTXAfterScaler[DC__NUM_DPP__MAX]; bool AllowDRAMClockChangeDuringVBlank[DC__NUM_DPP__MAX]; - bool AllowDRAMSelfRefreshDuringVBlank[DC__NUM_DPP__MAX]; double VRatioPrefetchY[DC__NUM_DPP__MAX]; double VRatioPrefetchC[DC__NUM_DPP__MAX]; double DestinationLinesForPrefetch[DC__NUM_DPP__MAX]; --=20 2.37.1 From nobody Wed Apr 15 00:20:29 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 089E9C04A68 for ; Thu, 28 Jul 2022 18:22:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231728AbiG1SWe (ORCPT ); Thu, 28 Jul 2022 14:22:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52810 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232464AbiG1SWV (ORCPT ); Thu, 28 Jul 2022 14:22:21 -0400 Received: from mx1.riseup.net (mx1.riseup.net [198.252.153.129]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5815B74E2E for ; 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Thu, 28 Jul 2022 18:22:09 +0000 (UTC) From: =?UTF-8?q?Ma=C3=ADra=20Canal?= To: Harry Wentland , Leo Li , Rodrigo Siqueira , Alex Deucher , christian.koenig@amd.com, Xinhui.Pan@amd.com, David Airlie , Daniel Vetter Cc: amd-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, mwen@igalia.com, andrealmeid@riseup.net, Isabella Basso , magalilemes00@gmail.com, tales.aparecida@gmail.com, =?UTF-8?q?Ma=C3=ADra=20Canal?= Subject: [PATCH 05/16] drm/amd/display: Remove VStartupMargin and FirstMainPlane VBA variables Date: Thu, 28 Jul 2022 15:20:37 -0300 Message-Id: <20220728182047.264825-6-mairacanal@riseup.net> In-Reply-To: <20220728182047.264825-1-mairacanal@riseup.net> References: <20220728182047.264825-1-mairacanal@riseup.net> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The variables VStartupMargin and FirstMainPlane from the struct vba_vars_st are only used on assignments, so there values are not used on code. So, remove the variables entries from the struct vba_vars_st. Signed-off-by: Ma=C3=ADra Canal --- .../display/dc/dml/dcn20/display_mode_vba_20.c | 14 +++----------- .../dc/dml/dcn20/display_mode_vba_20v2.c | 14 +++----------- .../display/dc/dml/dcn30/display_mode_vba_30.c | 17 ++++++----------- .../drm/amd/display/dc/dml/display_mode_vba.h | 2 -- 4 files changed, 12 insertions(+), 35 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c= b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c index d86d5c346e42..1424aa7a5018 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c @@ -2662,19 +2662,12 @@ static void dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefe= tchParametersWatermarksAndPer } } { - unsigned int VStartupMargin =3D 0; bool FirstMainPlane =3D true; =20 for (k =3D 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { - if (mode_lib->vba.BlendingAndTiming[k] =3D=3D k) { - unsigned int Margin =3D (mode_lib->vba.MaxVStartupLines[k] - mode_lib-= >vba.VStartup[k]) - * mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]; - - if (FirstMainPlane) { - VStartupMargin =3D Margin; - FirstMainPlane =3D false; - } else - VStartupMargin =3D dml_min(VStartupMargin, Margin); + if (mode_lib->vba.BlendingAndTiming[k] =3D=3D k && FirstMainPlane) { + FirstMainPlane =3D false; + } } =20 if (mode_lib->vba.UseMaximumVStartup) { @@ -2685,7 +2678,6 @@ static void dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetc= hParametersWatermarksAndPer } } } -} =20 static void dml20_DisplayPipeConfiguration(struct display_mode_lib *mode_l= ib) { diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2= .c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c index effd02574a0e..03613dbb3e61 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c @@ -2735,19 +2735,12 @@ static void dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPre= fetchParametersWatermarksAndP } } { - unsigned int VStartupMargin =3D 0; bool FirstMainPlane =3D true; =20 for (k =3D 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { - if (mode_lib->vba.BlendingAndTiming[k] =3D=3D k) { - unsigned int Margin =3D (mode_lib->vba.MaxVStartupLines[k] - mode_lib-= >vba.VStartup[k]) - * mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]; - - if (FirstMainPlane) { - VStartupMargin =3D Margin; - FirstMainPlane =3D false; - } else - VStartupMargin =3D dml_min(VStartupMargin, Margin); + if (mode_lib->vba.BlendingAndTiming[k] =3D=3D k && FirstMainPlane) { + FirstMainPlane =3D false; + } } =20 if (mode_lib->vba.UseMaximumVStartup) { @@ -2758,7 +2751,6 @@ static void dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefe= tchParametersWatermarksAndP } } } -} =20 static void dml20v2_DisplayPipeConfiguration(struct display_mode_lib *mode= _lib) { diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c= b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c index fe7fcb0d7b1f..caa3a9c598ce 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c @@ -3028,17 +3028,12 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchPar= ametersWatermarksAndPerforman } =20 // VStartup Margin - v->VStartupMargin =3D 0; - v->FirstMainPlane =3D true; - for (k =3D 0; k < v->NumberOfActivePlanes; ++k) { - if (v->BlendingAndTiming[k] =3D=3D k) { - double margin =3D (v->MaxVStartupLines[k] - v->VStartup[k]) * v->HTotal= [k] - / v->PixelClock[k]; - if (v->FirstMainPlane =3D=3D true) { - v->VStartupMargin =3D margin; - v->FirstMainPlane =3D false; - } else { - v->VStartupMargin =3D dml_min(v->VStartupMargin, margin); + { + bool FirstMainPlane =3D true; + + for (k =3D 0; k < v->NumberOfActivePlanes; ++k) { + if (v->BlendingAndTiming[k] =3D=3D k && FirstMainPlane) { + FirstMainPlane =3D false; } } } diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h b/driver= s/gpu/drm/amd/display/dc/dml/display_mode_vba.h index f03cf9cf9096..841a05bea57e 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h +++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h @@ -1106,7 +1106,6 @@ struct vba_vars_st { double TimePerChromaMetaChunkFlip[DC__NUM_DPP__MAX]; unsigned int DCCCMaxUncompressedBlock[DC__NUM_DPP__MAX]; unsigned int DCCCMaxCompressedBlock[DC__NUM_DPP__MAX]; - double VStartupMargin; bool NotEnoughTimeForDynamicMetadata[DC__NUM_DPP__MAX]; =20 /* Missing from VBA */ @@ -1137,7 +1136,6 @@ struct vba_vars_st { double MinUrgentLatencySupportUs; double MinFullDETBufferingTime; double AverageReadBandwidthGBytePerSecond; - bool FirstMainPlane; =20 unsigned int ViewportWidthChroma[DC__NUM_DPP__MAX]; unsigned int ViewportHeightChroma[DC__NUM_DPP__MAX]; --=20 2.37.1 From nobody Wed Apr 15 00:20:29 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9F4E9C04A68 for ; Thu, 28 Jul 2022 18:22:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232153AbiG1SWs (ORCPT ); Thu, 28 Jul 2022 14:22:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52202 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232622AbiG1SWX (ORCPT ); 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Thu, 28 Jul 2022 18:22:16 +0000 (UTC) From: =?UTF-8?q?Ma=C3=ADra=20Canal?= To: Harry Wentland , Leo Li , Rodrigo Siqueira , Alex Deucher , christian.koenig@amd.com, Xinhui.Pan@amd.com, David Airlie , Daniel Vetter Cc: amd-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, mwen@igalia.com, andrealmeid@riseup.net, Isabella Basso , magalilemes00@gmail.com, tales.aparecida@gmail.com, =?UTF-8?q?Ma=C3=ADra=20Canal?= Subject: [PATCH 06/16] drm/amd/display: Remove ImmediateFlipSupportedSurface VBA variable Date: Thu, 28 Jul 2022 15:20:38 -0300 Message-Id: <20220728182047.264825-7-mairacanal@riseup.net> In-Reply-To: <20220728182047.264825-1-mairacanal@riseup.net> References: <20220728182047.264825-1-mairacanal@riseup.net> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The ImmediateFlipSupportedSurface variable from the struct vba_vars_st is only used on assignments, so its value is not used on code. So, remove the ImmediateFlipSupportedSurface entry from the struct vba_vars_st. Signed-off-by: Ma=C3=ADra Canal --- .../gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c | 6 ------ drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h | 2 -- 2 files changed, 8 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c= b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c index f199ef475ed0..e2e1d6e77902 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c @@ -355,12 +355,6 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParame= tersWatermarksAndPerforman if (j !=3D k && mode_lib->vba.BlendingAndTiming[k] =3D=3D j && mode_lib= ->vba.DSCEnabled[j]) v->DSCDelay[k] =3D v->DSCDelay[j]; =20 - //Immediate Flip - for (k =3D 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) { - v->ImmediateFlipSupportedSurface[k] =3D mode_lib->vba.ImmediateFlipSuppo= rt - && (mode_lib->vba.ImmediateFlipRequirement[k] !=3D dm_immediate_flip_n= ot_required); - } - // Prefetch dml32_CalculateSurfaceSizeInMall( mode_lib->vba.NumberOfActiveSurfaces, diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h b/driver= s/gpu/drm/amd/display/dc/dml/display_mode_vba.h index 841a05bea57e..76cba5d7ac10 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h +++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h @@ -659,8 +659,6 @@ struct vba_vars_st { double DISPCLK_calculated; double DPPCLK_calculated[DC__NUM_DPP__MAX]; =20 - bool ImmediateFlipSupportedSurface[DC__NUM_DPP__MAX]; - bool Use_One_Row_For_Frame[DC__NUM_DPP__MAX]; bool Use_One_Row_For_Frame_Flip[DC__NUM_DPP__MAX]; unsigned int VUpdateOffsetPix[DC__NUM_DPP__MAX]; --=20 2.37.1 From nobody Wed Apr 15 00:20:29 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B5D8FC04A68 for ; Thu, 28 Jul 2022 18:22:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231674AbiG1SWy (ORCPT ); Thu, 28 Jul 2022 14:22:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52784 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232925AbiG1SW2 (ORCPT ); Thu, 28 Jul 2022 14:22:28 -0400 Received: from mx1.riseup.net (mx1.riseup.net [198.252.153.129]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 570E674DE0 for ; Thu, 28 Jul 2022 11:22:27 -0700 (PDT) Received: from fews1.riseup.net (fews1-pn.riseup.net [10.0.1.83]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256 client-signature RSA-PSS (2048 bits) client-digest SHA256) (Client CN "mail.riseup.net", Issuer "R3" (not verified)) by mx1.riseup.net (Postfix) with ESMTPS id 4LtzX26j2MzDrsv; Thu, 28 Jul 2022 18:22:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=riseup.net; s=squak; t=1659032547; bh=KxvoCK+77gkilpIyGMLDeI1tnqCfaC+2xs0CoAX0DNo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=c+ZbGIIaaEs2IB114VFnSeu7cc9eBsmrgthyIzjrFX5xO1hZ/3aOUMGjza3+I1Fc6 m+qRAM40Q7/BVek4wypIiUT4In18hQWbtH+oowbfS4dVtPk3wr6v8rAgASjpztCST1 oLTv8FMJ1uLzDIYTg345MBA+7s1HshPvLiHlrdqQ= X-Riseup-User-ID: 26566C790EE104442A012390CD0FCC02310DDFB0C32058388C28B4ADFA6B79E4 Received: from [127.0.0.1] (localhost [127.0.0.1]) by fews1.riseup.net (Postfix) with ESMTPSA id 4LtzWy4qZ8z5vMX; Thu, 28 Jul 2022 18:22:22 +0000 (UTC) From: =?UTF-8?q?Ma=C3=ADra=20Canal?= To: Harry Wentland , Leo Li , Rodrigo Siqueira , Alex Deucher , christian.koenig@amd.com, Xinhui.Pan@amd.com, David Airlie , Daniel Vetter Cc: amd-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, mwen@igalia.com, andrealmeid@riseup.net, Isabella Basso , magalilemes00@gmail.com, tales.aparecida@gmail.com, =?UTF-8?q?Ma=C3=ADra=20Canal?= Subject: [PATCH 07/16] drm/amd/display: Remove WritebackAllowFCLKChangeEndPosition VBA variable Date: Thu, 28 Jul 2022 15:20:39 -0300 Message-Id: <20220728182047.264825-8-mairacanal@riseup.net> In-Reply-To: <20220728182047.264825-1-mairacanal@riseup.net> References: <20220728182047.264825-1-mairacanal@riseup.net> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The WritebackAllowFCLKChangeEndPosition variable from the struct vba_vars_st is only used on assignments, so its value is not used on code. So, remove the WritebackAllowFCLKChangeEndPosition entry from the struct vba_vars_st. Signed-off-by: Ma=C3=ADra Canal --- .../gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c | 4 ---- drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h | 1 - 2 files changed, 5 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c= b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c index e2e1d6e77902..756a55f69799 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c @@ -1219,12 +1219,8 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchPara= metersWatermarksAndPerforman v->WritebackAllowDRAMClockChangeEndPosition[k] =3D dml_max(0, v->VStartup[k] * mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[= k] - v->Watermark.WritebackDRAMClockChangeWatermark); - v->WritebackAllowFCLKChangeEndPosition[k] =3D dml_max(0, - v->VStartup[k] * mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[= k] - - v->Watermark.WritebackFCLKChangeWatermark); } else { v->WritebackAllowDRAMClockChangeEndPosition[k] =3D 0; - v->WritebackAllowFCLKChangeEndPosition[k] =3D 0; } } } diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h b/driver= s/gpu/drm/amd/display/dc/dml/display_mode_vba.h index 76cba5d7ac10..518e599d74e2 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h +++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h @@ -1303,7 +1303,6 @@ struct vba_vars_st { bool OutputMultistreamEn[DC__NUM_DPP__MAX]; bool UsesMALLForStaticScreen[DC__NUM_DPP__MAX]; double MaxActiveDRAMClockChangeLatencySupported[DC__NUM_DPP__MAX]; - double WritebackAllowFCLKChangeEndPosition[DC__NUM_DPP__MAX]; bool PTEBufferSizeNotExceededPerState[DC__NUM_DPP__MAX]; // new in DML32 bool DCCMetaBufferSizeNotExceededPerState[DC__NUM_DPP__MAX]; // new in DM= L32 bool NotEnoughDSCSlices[DC__VOLTAGE_STATES]; --=20 2.37.1 From nobody Wed Apr 15 00:20:29 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 37D1CC04A68 for ; Thu, 28 Jul 2022 18:22:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229545AbiG1SW6 (ORCPT ); Thu, 28 Jul 2022 14:22:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53184 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232976AbiG1SWg (ORCPT ); Thu, 28 Jul 2022 14:22:36 -0400 Received: from mx1.riseup.net (mx1.riseup.net [198.252.153.129]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 634E774E0B for ; Thu, 28 Jul 2022 11:22:34 -0700 (PDT) Received: from fews1.riseup.net (fews1-pn.riseup.net [10.0.1.83]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256 client-signature RSA-PSS (2048 bits) client-digest SHA256) (Client CN "mail.riseup.net", Issuer "R3" (not verified)) by mx1.riseup.net (Postfix) with ESMTPS id 4LtzX94vkSzDryt; Thu, 28 Jul 2022 18:22:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=riseup.net; s=squak; t=1659032553; bh=zE+o6ufPkkpuK2HCBtOVfWw99bIfiN4ZlL3ielUoD0o=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Ur3f9RtzAko6ST0qePBuaZMGUYhXFfNn9015p/5+EdOfGscQf5OKHaGqMnZ+aAAPS OntM82BJd0GVWEXgJ+iWe800uwvVBykfj3+BQunX2AwIL5H5b8Fs9lM++BccE9OiVq 64cz7aYD9EpJdKwkggu7XpLUjpQWKMwfpoPEPR0o= X-Riseup-User-ID: 0D1B0215170A3491065454787D6596993FB14755A662347E4A01025C16C63E5C Received: from [127.0.0.1] (localhost [127.0.0.1]) by fews1.riseup.net (Postfix) with ESMTPSA id 4LtzX46bQJz5vMX; Thu, 28 Jul 2022 18:22:28 +0000 (UTC) From: =?UTF-8?q?Ma=C3=ADra=20Canal?= To: Harry Wentland , Leo Li , Rodrigo Siqueira , Alex Deucher , christian.koenig@amd.com, Xinhui.Pan@amd.com, David Airlie , Daniel Vetter Cc: amd-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, mwen@igalia.com, andrealmeid@riseup.net, Isabella Basso , magalilemes00@gmail.com, tales.aparecida@gmail.com, =?UTF-8?q?Ma=C3=ADra=20Canal?= Subject: [PATCH 08/16] drm/amd/display: Remove some XFC variables from VBA Date: Thu, 28 Jul 2022 15:20:40 -0300 Message-Id: <20220728182047.264825-9-mairacanal@riseup.net> In-Reply-To: <20220728182047.264825-1-mairacanal@riseup.net> References: <20220728182047.264825-1-mairacanal@riseup.net> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The variables XFCSupported, XFCTSlvVupdateOffset, XFCSlaveVupdateWidth, XFCSlaveVReadyOffset, XFCTransferDelay, XFCPrechargeDelay, XFCRemoteSurfaceFlipLatency and XFCPrefetchMargin are are only used on assignments, so their values are not used on code. So, remove the variables entries from the struct vba_vars_st. Signed-off-by: Ma=C3=ADra Canal --- .../dc/dml/dcn20/display_mode_vba_20.c | 38 ------------------- .../dc/dml/dcn20/display_mode_vba_20v2.c | 38 ------------------- .../dc/dml/dcn21/display_mode_vba_21.c | 38 ------------------- .../drm/amd/display/dc/dml/display_mode_vba.c | 1 - .../drm/amd/display/dc/dml/display_mode_vba.h | 8 ---- 5 files changed, 123 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c= b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c index 1424aa7a5018..7effe4be61b2 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c @@ -2580,9 +2580,6 @@ static void dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetc= hParametersWatermarksAndPer if (mode_lib->vba.XFCEnabled[k] =3D=3D true) { double TWait; =20 - mode_lib->vba.XFCSlaveVUpdateOffset[k] =3D mode_lib->vba.XFCTSlvVupdate= Offset; - mode_lib->vba.XFCSlaveVupdateWidth[k] =3D mode_lib->vba.XFCTSlvVupdateW= idth; - mode_lib->vba.XFCSlaveVReadyOffset[k] =3D mode_lib->vba.XFCTSlvVreadyOf= fset; TWait =3D CalculateTWait( mode_lib->vba.PrefetchMode[mode_lib->vba.VoltageLevel][mode_lib->vba.= maxMpcComb], mode_lib->vba.DRAMClockChangeLatency, @@ -2606,26 +2603,6 @@ static void dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefet= chParametersWatermarksAndPer &mode_lib->vba.SrcActiveDrainRate, &mode_lib->vba.TInitXFill, &mode_lib->vba.TslvChk); - mode_lib->vba.XFCRemoteSurfaceFlipLatency[k] =3D - dml_floor( - mode_lib->vba.XFCRemoteSurfaceFlipDelay - / (mode_lib->vba.HTotal[k] - / mode_lib->vba.PixelClock[k]), - 1); - mode_lib->vba.XFCTransferDelay[k] =3D - dml_ceil( - mode_lib->vba.XFCBusTransportTime - / (mode_lib->vba.HTotal[k] - / mode_lib->vba.PixelClock[k]), - 1); - mode_lib->vba.XFCPrechargeDelay[k] =3D - dml_ceil( - (mode_lib->vba.XFCBusTransportTime - + mode_lib->vba.TInitXFill - + mode_lib->vba.TslvChk) - / (mode_lib->vba.HTotal[k] - / mode_lib->vba.PixelClock[k]), - 1); mode_lib->vba.InitFillLevel =3D mode_lib->vba.XFCXBUFLatencyTolerance * mode_lib->vba.SrcActiveDrainRate; mode_lib->vba.FinalFillMargin =3D @@ -2644,21 +2621,6 @@ static void dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefet= chParametersWatermarksAndPer mode_lib->vba.TFinalxFill =3D mode_lib->vba.RemainingFillLevel / (mode_lib->vba.SrcActiveDrainRate * mode_lib->vba.XFCFillBWOverhead / 100); - mode_lib->vba.XFCPrefetchMargin[k] =3D - mode_lib->vba.XFCRemoteSurfaceFlipDelay - + mode_lib->vba.TFinalxFill - + (mode_lib->vba.DestinationLinesToRequestVMInVBlank[k] - + mode_lib->vba.DestinationLinesToRequestRowInVBlank[k]) - * mode_lib->vba.HTotal[k] - / mode_lib->vba.PixelClock[k]; - } else { - mode_lib->vba.XFCSlaveVUpdateOffset[k] =3D 0; - mode_lib->vba.XFCSlaveVupdateWidth[k] =3D 0; - mode_lib->vba.XFCSlaveVReadyOffset[k] =3D 0; - mode_lib->vba.XFCRemoteSurfaceFlipLatency[k] =3D 0; - mode_lib->vba.XFCPrechargeDelay[k] =3D 0; - mode_lib->vba.XFCTransferDelay[k] =3D 0; - mode_lib->vba.XFCPrefetchMargin[k] =3D 0; } } { diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2= .c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c index 03613dbb3e61..a23b400f615b 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c @@ -2653,9 +2653,6 @@ static void dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefe= tchParametersWatermarksAndP if (mode_lib->vba.XFCEnabled[k] =3D=3D true) { double TWait; =20 - mode_lib->vba.XFCSlaveVUpdateOffset[k] =3D mode_lib->vba.XFCTSlvVupdate= Offset; - mode_lib->vba.XFCSlaveVupdateWidth[k] =3D mode_lib->vba.XFCTSlvVupdateW= idth; - mode_lib->vba.XFCSlaveVReadyOffset[k] =3D mode_lib->vba.XFCTSlvVreadyOf= fset; TWait =3D CalculateTWait( mode_lib->vba.PrefetchMode[mode_lib->vba.VoltageLevel][mode_lib->vba.= maxMpcComb], mode_lib->vba.DRAMClockChangeLatency, @@ -2679,26 +2676,6 @@ static void dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPref= etchParametersWatermarksAndP &mode_lib->vba.SrcActiveDrainRate, &mode_lib->vba.TInitXFill, &mode_lib->vba.TslvChk); - mode_lib->vba.XFCRemoteSurfaceFlipLatency[k] =3D - dml_floor( - mode_lib->vba.XFCRemoteSurfaceFlipDelay - / (mode_lib->vba.HTotal[k] - / mode_lib->vba.PixelClock[k]), - 1); - mode_lib->vba.XFCTransferDelay[k] =3D - dml_ceil( - mode_lib->vba.XFCBusTransportTime - / (mode_lib->vba.HTotal[k] - / mode_lib->vba.PixelClock[k]), - 1); - mode_lib->vba.XFCPrechargeDelay[k] =3D - dml_ceil( - (mode_lib->vba.XFCBusTransportTime - + mode_lib->vba.TInitXFill - + mode_lib->vba.TslvChk) - / (mode_lib->vba.HTotal[k] - / mode_lib->vba.PixelClock[k]), - 1); mode_lib->vba.InitFillLevel =3D mode_lib->vba.XFCXBUFLatencyTolerance * mode_lib->vba.SrcActiveDrainRate; mode_lib->vba.FinalFillMargin =3D @@ -2717,21 +2694,6 @@ static void dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPref= etchParametersWatermarksAndP mode_lib->vba.TFinalxFill =3D mode_lib->vba.RemainingFillLevel / (mode_lib->vba.SrcActiveDrainRate * mode_lib->vba.XFCFillBWOverhead / 100); - mode_lib->vba.XFCPrefetchMargin[k] =3D - mode_lib->vba.XFCRemoteSurfaceFlipDelay - + mode_lib->vba.TFinalxFill - + (mode_lib->vba.DestinationLinesToRequestVMInVBlank[k] - + mode_lib->vba.DestinationLinesToRequestRowInVBlank[k]) - * mode_lib->vba.HTotal[k] - / mode_lib->vba.PixelClock[k]; - } else { - mode_lib->vba.XFCSlaveVUpdateOffset[k] =3D 0; - mode_lib->vba.XFCSlaveVupdateWidth[k] =3D 0; - mode_lib->vba.XFCSlaveVReadyOffset[k] =3D 0; - mode_lib->vba.XFCRemoteSurfaceFlipLatency[k] =3D 0; - mode_lib->vba.XFCPrechargeDelay[k] =3D 0; - mode_lib->vba.XFCTransferDelay[k] =3D 0; - mode_lib->vba.XFCPrefetchMargin[k] =3D 0; } } { diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c= b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c index ae03f1a3c9f0..4ba9fa17ea39 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c @@ -2589,9 +2589,6 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParam= etersWatermarksAndPerforman if (mode_lib->vba.XFCEnabled[k] =3D=3D true) { double TWait; =20 - locals->XFCSlaveVUpdateOffset[k] =3D mode_lib->vba.XFCTSlvVupdateOffset; - locals->XFCSlaveVupdateWidth[k] =3D mode_lib->vba.XFCTSlvVupdateWidth; - locals->XFCSlaveVReadyOffset[k] =3D mode_lib->vba.XFCTSlvVreadyOffset; TWait =3D CalculateTWait( mode_lib->vba.PrefetchMode[mode_lib->vba.VoltageLevel][mode_lib->vba.= maxMpcComb], mode_lib->vba.DRAMClockChangeLatency, @@ -2615,26 +2612,6 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchPara= metersWatermarksAndPerforman &mode_lib->vba.SrcActiveDrainRate, &mode_lib->vba.TInitXFill, &mode_lib->vba.TslvChk); - locals->XFCRemoteSurfaceFlipLatency[k] =3D - dml_floor( - mode_lib->vba.XFCRemoteSurfaceFlipDelay - / (mode_lib->vba.HTotal[k] - / mode_lib->vba.PixelClock[k]), - 1); - locals->XFCTransferDelay[k] =3D - dml_ceil( - mode_lib->vba.XFCBusTransportTime - / (mode_lib->vba.HTotal[k] - / mode_lib->vba.PixelClock[k]), - 1); - locals->XFCPrechargeDelay[k] =3D - dml_ceil( - (mode_lib->vba.XFCBusTransportTime - + mode_lib->vba.TInitXFill - + mode_lib->vba.TslvChk) - / (mode_lib->vba.HTotal[k] - / mode_lib->vba.PixelClock[k]), - 1); mode_lib->vba.InitFillLevel =3D mode_lib->vba.XFCXBUFLatencyTolerance * mode_lib->vba.SrcActiveDrainRate; mode_lib->vba.FinalFillMargin =3D @@ -2653,21 +2630,6 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchPara= metersWatermarksAndPerforman mode_lib->vba.TFinalxFill =3D mode_lib->vba.RemainingFillLevel / (mode_lib->vba.SrcActiveDrainRate * mode_lib->vba.XFCFillBWOverhead / 100); - locals->XFCPrefetchMargin[k] =3D - mode_lib->vba.XFCRemoteSurfaceFlipDelay - + mode_lib->vba.TFinalxFill - + (locals->DestinationLinesToRequestVMInVBlank[k] - + locals->DestinationLinesToRequestRowInVBlank[k]) - * mode_lib->vba.HTotal[k] - / mode_lib->vba.PixelClock[k]; - } else { - locals->XFCSlaveVUpdateOffset[k] =3D 0; - locals->XFCSlaveVupdateWidth[k] =3D 0; - locals->XFCSlaveVReadyOffset[k] =3D 0; - locals->XFCRemoteSurfaceFlipLatency[k] =3D 0; - locals->XFCPrechargeDelay[k] =3D 0; - locals->XFCTransferDelay[k] =3D 0; - locals->XFCPrefetchMargin[k] =3D 0; } } =20 diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c b/driver= s/gpu/drm/amd/display/dc/dml/display_mode_vba.c index 316153ece160..7a4a013f195a 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c +++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c @@ -489,7 +489,6 @@ static void fetch_ip_params(struct display_mode_lib *mo= de_lib) mode_lib->vba.ODMCapability =3D ip->odm_capable; mode_lib->vba.DISPCLKRampingMargin =3D ip->dispclk_ramp_margin_percent; =20 - mode_lib->vba.XFCSupported =3D ip->xfc_supported; mode_lib->vba.XFCFillBWOverhead =3D ip->xfc_fill_bw_overhead_percent; mode_lib->vba.XFCFillConstant =3D ip->xfc_fill_constant_bytes; mode_lib->vba.DPPCLKDelaySubtotal =3D ip->dppclk_delay_subtotal; diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h b/driver= s/gpu/drm/amd/display/dc/dml/display_mode_vba.h index 518e599d74e2..91562c0d35f2 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h +++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h @@ -497,7 +497,6 @@ struct vba_vars_st { unsigned int PTEBufferSizeInRequestsChroma; double DISPCLKRampingMargin; unsigned int MaxInterDCNTileRepeaters; - bool XFCSupported; double XFCSlvChunkSize; double XFCFillBWOverhead; double XFCFillConstant; @@ -1041,13 +1040,6 @@ struct vba_vars_st { unsigned int BlockHeight256BytesC[DC__NUM_DPP__MAX]; unsigned int BlockWidth256BytesY[DC__NUM_DPP__MAX]; unsigned int BlockWidth256BytesC[DC__NUM_DPP__MAX]; - double XFCSlaveVUpdateOffset[DC__NUM_DPP__MAX]; - double XFCSlaveVupdateWidth[DC__NUM_DPP__MAX]; - double XFCSlaveVReadyOffset[DC__NUM_DPP__MAX]; - double XFCTransferDelay[DC__NUM_DPP__MAX]; - double XFCPrechargeDelay[DC__NUM_DPP__MAX]; - double XFCRemoteSurfaceFlipLatency[DC__NUM_DPP__MAX]; - double XFCPrefetchMargin[DC__NUM_DPP__MAX]; unsigned int dpte_row_width_luma_ub[DC__NUM_DPP__MAX]; unsigned int dpte_row_width_chroma_ub[DC__NUM_DPP__MAX]; double FullDETBufferingTimeY[DC__NUM_DPP__MAX]; // WM --=20 2.37.1 From nobody Wed Apr 15 00:20:29 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 84DC8C3F6B0 for ; Thu, 28 Jul 2022 18:23:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233143AbiG1SXN (ORCPT ); Thu, 28 Jul 2022 14:23:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53486 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233142AbiG1SWo (ORCPT ); Thu, 28 Jul 2022 14:22:44 -0400 Received: from mx1.riseup.net (mx1.riseup.net [198.252.153.129]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BAF7A7539C for ; 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Thu, 28 Jul 2022 18:22:35 +0000 (UTC) From: =?UTF-8?q?Ma=C3=ADra=20Canal?= To: Harry Wentland , Leo Li , Rodrigo Siqueira , Alex Deucher , christian.koenig@amd.com, Xinhui.Pan@amd.com, David Airlie , Daniel Vetter Cc: amd-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, mwen@igalia.com, andrealmeid@riseup.net, Isabella Basso , magalilemes00@gmail.com, tales.aparecida@gmail.com, =?UTF-8?q?Ma=C3=ADra=20Canal?= Subject: [PATCH 09/16] drm/amd/display: Remove SwathWidthCSingleDPP VBA variable Date: Thu, 28 Jul 2022 15:20:41 -0300 Message-Id: <20220728182047.264825-10-mairacanal@riseup.net> In-Reply-To: <20220728182047.264825-1-mairacanal@riseup.net> References: <20220728182047.264825-1-mairacanal@riseup.net> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The SwathWidthCSingleDPP variable from the struct vba_vars_st is only used on assignments, so its value is not used on code. So, remove the SwathWidthCSingleDPP entry from the struct vba_vars_st. Signed-off-by: Ma=C3=ADra Canal --- drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c | 2 -- drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c | 2 -- .../gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c | 2 -- drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c | 2 -- drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h | 1 - 5 files changed, 9 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c= b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c index caa3a9c598ce..4fac83c776ad 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c @@ -3660,10 +3660,8 @@ void dml30_ModeSupportAndSystemConfigurationFull(str= uct display_mode_lib *mode_l for (k =3D 0; k <=3D v->NumberOfActivePlanes - 1; k++) { if (v->SourceScan[k] !=3D dm_vert) { v->SwathWidthYSingleDPP[k] =3D v->ViewportWidth[k]; - v->SwathWidthCSingleDPP[k] =3D v->ViewportWidthChroma[k]; } else { v->SwathWidthYSingleDPP[k] =3D v->ViewportHeight[k]; - v->SwathWidthCSingleDPP[k] =3D v->ViewportHeightChroma[k]; } } for (k =3D 0; k <=3D v->NumberOfActivePlanes - 1; k++) { diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c= b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c index eca05bbc0fb5..9ea2d2fd56f1 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c @@ -3965,10 +3965,8 @@ void dml31_ModeSupportAndSystemConfigurationFull(str= uct display_mode_lib *mode_l for (k =3D 0; k < v->NumberOfActivePlanes; k++) { if (v->SourceScan[k] !=3D dm_vert) { v->SwathWidthYSingleDPP[k] =3D v->ViewportWidth[k]; - v->SwathWidthCSingleDPP[k] =3D v->ViewportWidthChroma[k]; } else { v->SwathWidthYSingleDPP[k] =3D v->ViewportHeight[k]; - v->SwathWidthCSingleDPP[k] =3D v->ViewportHeightChroma[k]; } } for (k =3D 0; k < v->NumberOfActivePlanes; k++) { diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314= .c b/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c index acb47cdaaa05..ae749d39db2a 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c @@ -4077,10 +4077,8 @@ void dml314_ModeSupportAndSystemConfigurationFull(st= ruct display_mode_lib *mode_ for (k =3D 0; k < v->NumberOfActivePlanes; k++) { if (v->SourceScan[k] !=3D dm_vert) { v->SwathWidthYSingleDPP[k] =3D v->ViewportWidth[k]; - v->SwathWidthCSingleDPP[k] =3D v->ViewportWidthChroma[k]; } else { v->SwathWidthYSingleDPP[k] =3D v->ViewportHeight[k]; - v->SwathWidthCSingleDPP[k] =3D v->ViewportHeightChroma[k]; } } for (k =3D 0; k < v->NumberOfActivePlanes; k++) { diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c= b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c index 756a55f69799..a88cfce3b771 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c @@ -1721,10 +1721,8 @@ void dml32_ModeSupportAndSystemConfigurationFull(str= uct display_mode_lib *mode_l for (k =3D 0; k <=3D mode_lib->vba.NumberOfActiveSurfaces - 1; k++) { if (!IsVertical(mode_lib->vba.SourceRotation[k])) { v->SwathWidthYSingleDPP[k] =3D mode_lib->vba.ViewportWidth[k]; - v->SwathWidthCSingleDPP[k] =3D mode_lib->vba.ViewportWidthChroma[k]; } else { v->SwathWidthYSingleDPP[k] =3D mode_lib->vba.ViewportHeight[k]; - v->SwathWidthCSingleDPP[k] =3D mode_lib->vba.ViewportHeightChroma[k]; } } for (k =3D 0; k <=3D mode_lib->vba.NumberOfActiveSurfaces - 1; k++) { diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h b/driver= s/gpu/drm/amd/display/dc/dml/display_mode_vba.h index 91562c0d35f2..ac8131b52b78 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h +++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h @@ -939,7 +939,6 @@ struct vba_vars_st { =20 =20 bool MPCCombine[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; - double SwathWidthCSingleDPP[DC__NUM_DPP__MAX]; double MaximumSwathWidthInLineBufferLuma; double MaximumSwathWidthInLineBufferChroma; double MaximumSwathWidthLuma[DC__NUM_DPP__MAX]; --=20 2.37.1 From nobody Wed Apr 15 00:20:29 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 19CEBC04A68 for ; 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a=rsa-sha256; c=relaxed/simple; d=riseup.net; s=squak; t=1659032568; bh=st9aPCSjCcU8sGTEUIKVJxFHPtEfVhpUBemleBVYzmc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=A7+i974rqBt7BvjPNhqVkHS7tFjI2yJNb5P8chFCMxnaVCEPyVEgYUMLOTDpbrNct dsk3lwMqssdX9HWY+1ha2E3/gBlYM2MX9A94rJ9pGiQFg+t9DdLS0627nVjjD0KNRH BPi1555a9Q91eRkn4RcJUucG3xFHkelfxCj1Fzck= X-Riseup-User-ID: 8AC2F3FC37DEDA158C3EB2EC2EDBF02A2D401933EFE23FD8C4A047370E2472FD Received: from [127.0.0.1] (localhost [127.0.0.1]) by fews1.riseup.net (Postfix) with ESMTPSA id 4LtzXL5N43z5vMX; Thu, 28 Jul 2022 18:22:42 +0000 (UTC) From: =?UTF-8?q?Ma=C3=ADra=20Canal?= To: Harry Wentland , Leo Li , Rodrigo Siqueira , Alex Deucher , christian.koenig@amd.com, Xinhui.Pan@amd.com, David Airlie , Daniel Vetter Cc: amd-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, mwen@igalia.com, andrealmeid@riseup.net, Isabella Basso , magalilemes00@gmail.com, tales.aparecida@gmail.com, =?UTF-8?q?Ma=C3=ADra=20Canal?= Subject: [PATCH 10/16] drm/amd/display: Remove ModeIsSupported VBA variable Date: Thu, 28 Jul 2022 15:20:42 -0300 Message-Id: <20220728182047.264825-11-mairacanal@riseup.net> In-Reply-To: <20220728182047.264825-1-mairacanal@riseup.net> References: <20220728182047.264825-1-mairacanal@riseup.net> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The ModeIsSupported variable from the struct vba_vars_st is only used on assignments, so its value is not used on code. So, remove the ModeIsSupported entry from the struct vba_vars_st. Signed-off-by: Ma=C3=ADra Canal --- drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c | 1 - drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c | 1 - .../gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c | 1 - drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c | 2 -- drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h | 1 - 5 files changed, 6 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c= b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c index 4fac83c776ad..b776a7940fac 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c @@ -5250,7 +5250,6 @@ void dml30_ModeSupportAndSystemConfigurationFull(stru= ct display_mode_lib *mode_l for (i =3D v->soc.num_states; i >=3D 0; i--) { if (i =3D=3D v->soc.num_states || v->ModeSupport[i][0] =3D=3D true || v= ->ModeSupport[i][1] =3D=3D true) { v->VoltageLevel =3D i; - v->ModeIsSupported =3D v->ModeSupport[i][0] =3D=3D true || v->ModeSupp= ort[i][1] =3D=3D true; if (v->ModeSupport[i][1] =3D=3D true) { MaximumMPCCombine =3D 1; } else { diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c= b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c index 9ea2d2fd56f1..b338e72d96d8 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c @@ -5521,7 +5521,6 @@ void dml31_ModeSupportAndSystemConfigurationFull(stru= ct display_mode_lib *mode_l for (i =3D v->soc.num_states; i >=3D 0; i--) { if (i =3D=3D v->soc.num_states || v->ModeSupport[i][0] =3D=3D true || v= ->ModeSupport[i][1] =3D=3D true) { v->VoltageLevel =3D i; - v->ModeIsSupported =3D v->ModeSupport[i][0] =3D=3D true || v->ModeSupp= ort[i][1] =3D=3D true; if (v->ModeSupport[i][0] =3D=3D true) { MaximumMPCCombine =3D 0; } else { diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314= .c b/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c index ae749d39db2a..6c60731687bf 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c @@ -5636,7 +5636,6 @@ void dml314_ModeSupportAndSystemConfigurationFull(str= uct display_mode_lib *mode_ for (i =3D v->soc.num_states; i >=3D 0; i--) { if (i =3D=3D v->soc.num_states || v->ModeSupport[i][0] =3D=3D true || v= ->ModeSupport[i][1] =3D=3D true) { v->VoltageLevel =3D i; - v->ModeIsSupported =3D v->ModeSupport[i][0] =3D=3D true || v->ModeSupp= ort[i][1] =3D=3D true; if (v->ModeSupport[i][0] =3D=3D true) { MaximumMPCCombine =3D 0; } else { diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c= b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c index a88cfce3b771..5fce4bbb4e85 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c @@ -3668,8 +3668,6 @@ void dml32_ModeSupportAndSystemConfigurationFull(stru= ct display_mode_lib *mode_l if (i =3D=3D v->soc.num_states || mode_lib->vba.ModeSupport[i][0] =3D=3D= true || mode_lib->vba.ModeSupport[i][1] =3D=3D true) { mode_lib->vba.VoltageLevel =3D i; - mode_lib->vba.ModeIsSupported =3D mode_lib->vba.ModeSupport[i][0] =3D= =3D true - || mode_lib->vba.ModeSupport[i][1] =3D=3D true; =20 if (mode_lib->vba.ModeSupport[i][0] =3D=3D true) { MaximumMPCCombine =3D 0; diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h b/driver= s/gpu/drm/amd/display/dc/dml/display_mode_vba.h index ac8131b52b78..f4d4bf7b6111 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h +++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h @@ -1132,7 +1132,6 @@ struct vba_vars_st { double VRatioChroma[DC__NUM_DPP__MAX]; int WritebackSourceWidth[DC__NUM_DPP__MAX]; =20 - bool ModeIsSupported; bool ODMCombine4To1Supported; =20 unsigned int SurfaceWidthY[DC__NUM_DPP__MAX]; --=20 2.37.1 From nobody Wed Apr 15 00:20:29 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BF4D9C19F29 for ; Thu, 28 Jul 2022 18:23:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233219AbiG1SX1 (ORCPT ); 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b=bqjanDXJZLjlDpmvBBX3SyLO7UsB4YrhGNK/CR66sVttAal1ngnK2toLfaWxziomK kJjmnEln7DIXPd4MBBk7dt7iJ1Y4htGBlcqhfgXKnaaLnpQjg6dPjX7GVJ9LBtK2ab qRiQY9T8DOP2Zd+h4QtFNyYBEFRpdkBkA/t2uaMM= X-Riseup-User-ID: 029433EB08767EF91F38D039897485939EFC26DE185FAD55DEA8F2F0E96F7E76 Received: from [127.0.0.1] (localhost [127.0.0.1]) by fews1.riseup.net (Postfix) with ESMTPSA id 4LtzXT3cgPz5vMX; Thu, 28 Jul 2022 18:22:49 +0000 (UTC) From: =?UTF-8?q?Ma=C3=ADra=20Canal?= To: Harry Wentland , Leo Li , Rodrigo Siqueira , Alex Deucher , christian.koenig@amd.com, Xinhui.Pan@amd.com, David Airlie , Daniel Vetter Cc: amd-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, mwen@igalia.com, andrealmeid@riseup.net, Isabella Basso , magalilemes00@gmail.com, tales.aparecida@gmail.com, =?UTF-8?q?Ma=C3=ADra=20Canal?= Subject: [PATCH 11/16] drm/amd/display: Remove MPCCombineEnable VBA variable Date: Thu, 28 Jul 2022 15:20:43 -0300 Message-Id: <20220728182047.264825-12-mairacanal@riseup.net> In-Reply-To: <20220728182047.264825-1-mairacanal@riseup.net> References: <20220728182047.264825-1-mairacanal@riseup.net> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The MPCCombineEnable variable from the struct vba_vars_st is only used on assignments, so its value is not used on code. So, remove the MPCCombineEnable entry from the struct vba_vars_st. Signed-off-by: Ma=C3=ADra Canal --- drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c | 1 - drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c | 1 - .../gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c | 1 - drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c | 2 -- drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h | 1 - 5 files changed, 6 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c= b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c index b776a7940fac..7dd51fe88d4f 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c @@ -5259,7 +5259,6 @@ void dml30_ModeSupportAndSystemConfigurationFull(stru= ct display_mode_lib *mode_l } v->ImmediateFlipSupport =3D v->ImmediateFlipSupportedForState[v->Voltage= Level][MaximumMPCCombine]; for (k =3D 0; k <=3D v->NumberOfActivePlanes - 1; k++) { - v->MPCCombineEnable[k] =3D v->MPCCombine[v->VoltageLevel][MaximumMPCCom= bine][k]; v->DPPPerPlane[k] =3D v->NoOfDPP[v->VoltageLevel][MaximumMPCCombine][k]; } v->DCFCLK =3D v->DCFCLKState[v->VoltageLevel][MaximumMPCCombine]; diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c= b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c index b338e72d96d8..2e906f01950b 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c @@ -5530,7 +5530,6 @@ void dml31_ModeSupportAndSystemConfigurationFull(stru= ct display_mode_lib *mode_l } v->ImmediateFlipSupport =3D v->ImmediateFlipSupportedForState[v->Voltage= Level][MaximumMPCCombine]; for (k =3D 0; k <=3D v->NumberOfActivePlanes - 1; k++) { - v->MPCCombineEnable[k] =3D v->MPCCombine[v->VoltageLevel][MaximumMPCCom= bine][k]; v->DPPPerPlane[k] =3D v->NoOfDPP[v->VoltageLevel][MaximumMPCCombine][k]; } v->DCFCLK =3D v->DCFCLKState[v->VoltageLevel][MaximumMPCCombine]; diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314= .c b/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c index 6c60731687bf..6a5b3c39ec60 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c @@ -5645,7 +5645,6 @@ void dml314_ModeSupportAndSystemConfigurationFull(str= uct display_mode_lib *mode_ } v->ImmediateFlipSupport =3D v->ImmediateFlipSupportedForState[v->Voltage= Level][MaximumMPCCombine]; for (k =3D 0; k <=3D v->NumberOfActivePlanes - 1; k++) { - v->MPCCombineEnable[k] =3D v->MPCCombine[v->VoltageLevel][MaximumMPCCom= bine][k]; v->DPPPerPlane[k] =3D v->NoOfDPP[v->VoltageLevel][MaximumMPCCombine][k]; } v->DCFCLK =3D v->DCFCLKState[v->VoltageLevel][MaximumMPCCombine]; diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c= b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c index 5fce4bbb4e85..6d4907656f9f 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c @@ -3685,8 +3685,6 @@ void dml32_ModeSupportAndSystemConfigurationFull(stru= ct display_mode_lib *mode_l mode_lib->vba.CompressedBufferSizeInkByteAllStates[mode_lib->vba.Voltag= eLevel][MaximumMPCCombine]; // Not used, informational =20 for (k =3D 0; k <=3D mode_lib->vba.NumberOfActiveSurfaces - 1; k++) { - mode_lib->vba.MPCCombineEnable[k] =3D - mode_lib->vba.MPCCombine[mode_lib->vba.VoltageLevel][MaximumMPCCombine= ][k]; mode_lib->vba.DPPPerPlane[k] =3D mode_lib->vba.NoOfDPP[mode_lib->vba.Vol= tageLevel][MaximumMPCCombine][k]; mode_lib->vba.SwathHeightY[k] =3D mode_lib->vba.SwathHeightYAllStates[mode_lib->vba.VoltageLevel][Maximu= mMPCCombine][k]; diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h b/driver= s/gpu/drm/amd/display/dc/dml/display_mode_vba.h index f4d4bf7b6111..31cf144860b9 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h +++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h @@ -1147,7 +1147,6 @@ struct vba_vars_st { double GPUVMMinPageSize; double HostVMMinPageSize; =20 - bool MPCCombineEnable[DC__NUM_DPP__MAX]; unsigned int HostVMMaxNonCachedPageTableLevels; bool DynamicMetadataVMEnabled; double WritebackInterfaceBufferSize; --=20 2.37.1 From nobody Wed Apr 15 00:20:29 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6645DC04A68 for ; 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a=rsa-sha256; c=relaxed/simple; d=riseup.net; s=squak; t=1659032582; bh=UINbQvXcI1FsUTHFriHZVm7J1aYZVSly8vzBah8t+ME=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=NTgXja8l8EkLnYiY4mTSFc7sq5jrX1rtY87BtaLZYeNO8SGrBLhtc+57UgzjicO0v eIj1Y9W3tqEDDVh7winLELMY8MvjT7RylNRzKNMrqbgIqcmog39sy0Xg9CN40etQKB 8xCTtBBEYROzrhN1QgrjMvVLept55Y9aWfJfpjLY= X-Riseup-User-ID: DC7D5CED6CB005C5FDCF5AB464E3A71DB77546D43C03F1E4122D7B0665C25759 Received: from [127.0.0.1] (localhost [127.0.0.1]) by fews1.riseup.net (Postfix) with ESMTPSA id 4LtzXd258tz5vTb; Thu, 28 Jul 2022 18:22:56 +0000 (UTC) From: =?UTF-8?q?Ma=C3=ADra=20Canal?= To: Harry Wentland , Leo Li , Rodrigo Siqueira , Alex Deucher , christian.koenig@amd.com, Xinhui.Pan@amd.com, David Airlie , Daniel Vetter Cc: amd-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, mwen@igalia.com, andrealmeid@riseup.net, Isabella Basso , magalilemes00@gmail.com, tales.aparecida@gmail.com, =?UTF-8?q?Ma=C3=ADra=20Canal?= Subject: [PATCH 12/16] drm/amd/display: Remove NumberOfDP2p0Support VBA variable Date: Thu, 28 Jul 2022 15:20:44 -0300 Message-Id: <20220728182047.264825-13-mairacanal@riseup.net> In-Reply-To: <20220728182047.264825-1-mairacanal@riseup.net> References: <20220728182047.264825-1-mairacanal@riseup.net> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The NumberOfDP2p0Support variable from the struct vba_vars_st is only used on assignments, so its value is not used on code. So, remove the NumberOfDP2p0Support entry from the struct vba_vars_st. Signed-off-by: Ma=C3=ADra Canal --- drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c | 2 -- drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h | 1 - 2 files changed, 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c= b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c index 6d4907656f9f..3c044549c95f 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c @@ -2186,8 +2186,6 @@ void dml32_ModeSupportAndSystemConfigurationFull(stru= ct display_mode_lib *mode_l =20 mode_lib->vba.NumberOfOTGSupport =3D (v->dummy_vars.dml32_ModeSupportAndS= ystemConfigurationFull.TotalNumberOfActiveOTG <=3D mode_lib->vba.MaxNumOTG); mode_lib->vba.NumberOfHDMIFRLSupport =3D (v->dummy_vars.dml32_ModeSupport= AndSystemConfigurationFull.TotalNumberOfActiveHDMIFRL <=3D mode_lib->vba.Ma= xNumHDMIFRLOutputs); - mode_lib->vba.NumberOfDP2p0Support =3D (v->dummy_vars.dml32_ModeSupportAn= dSystemConfigurationFull.TotalNumberOfActiveDP2p0 <=3D mode_lib->vba.MaxNum= DP2p0Streams - && v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.TotalNumbe= rOfActiveDP2p0Outputs <=3D mode_lib->vba.MaxNumDP2p0Outputs); =20 /* Display IO and DSC Support Check */ mode_lib->vba.NonsupportedDSCInputBPC =3D false; diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h b/driver= s/gpu/drm/amd/display/dc/dml/display_mode_vba.h index 31cf144860b9..f973d0ee82f9 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h +++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h @@ -754,7 +754,6 @@ struct vba_vars_st { bool DCCProgrammingAssumesScanDirectionUnknownFinal; bool EnoughWritebackUnits; bool ODMCombine2To1SupportCheckOK[DC__VOLTAGE_STATES]; - bool NumberOfDP2p0Support; unsigned int MaxNumDP2p0Streams; unsigned int MaxNumDP2p0Outputs; enum dm_output_type OutputTypePerState[DC__VOLTAGE_STATES][DC__NUM_DPP__M= AX]; --=20 2.37.1 From nobody Wed Apr 15 00:20:29 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CB043C04A68 for ; Thu, 28 Jul 2022 18:23:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232363AbiG1SXl (ORCPT ); Thu, 28 Jul 2022 14:23:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52752 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233235AbiG1SXL (ORCPT ); Thu, 28 Jul 2022 14:23:11 -0400 Received: from mx1.riseup.net (mx1.riseup.net [198.252.153.129]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A84A374E18 for ; Thu, 28 Jul 2022 11:23:09 -0700 (PDT) Received: from fews1.riseup.net (fews1-pn.riseup.net [10.0.1.83]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256 client-signature RSA-PSS (2048 bits) client-digest SHA256) (Client CN "mail.riseup.net", Issuer "R3" (not verified)) by mx1.riseup.net (Postfix) with ESMTPS id 4LtzXs1WM6zDs0w; Thu, 28 Jul 2022 18:23:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=riseup.net; s=squak; t=1659032589; bh=iaOHYVyM4X5RdBouq2ppOPj7dngg396FejPsdt4W6p8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=kFn3YO7ajpcW7WVzmdRRZT0sm9E6vs/T/vdqBJxE1ArCrcvU5Pd07RzvN8BScha23 a5iIulXfYOOXajapFZs06XmudcVhU063haMH3z13dv0jbi+SgUBWFva+gRfcBUKlIS 43wAMC3umwO78/jlbHadTH5+sXk1x6r1Mzw42IVU= X-Riseup-User-ID: FEFF0A5E1F2EA0E00D88335364463F13AD1802053B13777E155B7D8668B66B03 Received: from [127.0.0.1] (localhost [127.0.0.1]) by fews1.riseup.net (Postfix) with ESMTPSA id 4LtzXm0MM2z5vMX; Thu, 28 Jul 2022 18:23:03 +0000 (UTC) From: =?UTF-8?q?Ma=C3=ADra=20Canal?= To: Harry Wentland , Leo Li , Rodrigo Siqueira , Alex Deucher , christian.koenig@amd.com, Xinhui.Pan@amd.com, David Airlie , Daniel Vetter Cc: amd-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, mwen@igalia.com, andrealmeid@riseup.net, Isabella Basso , magalilemes00@gmail.com, tales.aparecida@gmail.com, =?UTF-8?q?Ma=C3=ADra=20Canal?= Subject: [PATCH 13/16] drm/amd/display: Remove TFinalxFill VBA variable Date: Thu, 28 Jul 2022 15:20:45 -0300 Message-Id: <20220728182047.264825-14-mairacanal@riseup.net> In-Reply-To: <20220728182047.264825-1-mairacanal@riseup.net> References: <20220728182047.264825-1-mairacanal@riseup.net> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The TFinalxFill variable from the struct vba_vars_st is only used on assignments, so its value is not used on code. So, remove the TFinalxFill entry from the struct vba_vars_st. Signed-off-by: Ma=C3=ADra Canal --- drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c | 3 --- .../gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c | 3 --- drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c | 3 --- drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h | 1 - 4 files changed, 10 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c= b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c index 7effe4be61b2..91e74c0f3c3c 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c @@ -2618,9 +2618,6 @@ static void dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetc= hParametersWatermarksAndPer mode_lib->vba.RemainingFillLevel =3D dml_max( 0.0, mode_lib->vba.FinalFillLevel - mode_lib->vba.InitFillLevel); - mode_lib->vba.TFinalxFill =3D mode_lib->vba.RemainingFillLevel - / (mode_lib->vba.SrcActiveDrainRate - * mode_lib->vba.XFCFillBWOverhead / 100); } } { diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2= .c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c index a23b400f615b..9b52f9f3e4a0 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c @@ -2691,9 +2691,6 @@ static void dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefe= tchParametersWatermarksAndP mode_lib->vba.RemainingFillLevel =3D dml_max( 0.0, mode_lib->vba.FinalFillLevel - mode_lib->vba.InitFillLevel); - mode_lib->vba.TFinalxFill =3D mode_lib->vba.RemainingFillLevel - / (mode_lib->vba.SrcActiveDrainRate - * mode_lib->vba.XFCFillBWOverhead / 100); } } { diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c= b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c index 4ba9fa17ea39..bc8cc21cf3f6 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c @@ -2627,9 +2627,6 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParam= etersWatermarksAndPerforman mode_lib->vba.RemainingFillLevel =3D dml_max( 0.0, mode_lib->vba.FinalFillLevel - mode_lib->vba.InitFillLevel); - mode_lib->vba.TFinalxFill =3D mode_lib->vba.RemainingFillLevel - / (mode_lib->vba.SrcActiveDrainRate - * mode_lib->vba.XFCFillBWOverhead / 100); } } =20 diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h b/driver= s/gpu/drm/amd/display/dc/dml/display_mode_vba.h index f973d0ee82f9..46e69f941bff 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h +++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h @@ -421,7 +421,6 @@ struct vba_vars_st { double FinalFillMargin; double FinalFillLevel; double RemainingFillLevel; - double TFinalxFill; =20 // // SOC Bounding Box Parameters --=20 2.37.1 From nobody Wed Apr 15 00:20:29 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4264CC04A68 for ; Thu, 28 Jul 2022 18:23:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232915AbiG1SXq (ORCPT ); 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b=IS7cW3mLiujda2mpl99ObsGOY+1kSIgWAD/8u6Qgq0S1oFjc5wAo66z70gfuQNzvy g2S72l5sDJzJqNxv5sqk9QOnm/NIwQ/oReT0q6npdG2QcIwtp2U/++8yYxnfOrxXs6 7eBlpJnjgFS27rKZwoeSnyKzhdrVwgHZIfDOx8bs= X-Riseup-User-ID: 785C277BFA268284350BCCF64E44C393D806A14C85E7B44A5EF3FAAAE016287F Received: from [127.0.0.1] (localhost [127.0.0.1]) by fews1.riseup.net (Postfix) with ESMTPSA id 4LtzXt2rL8z5vMX; Thu, 28 Jul 2022 18:23:10 +0000 (UTC) From: =?UTF-8?q?Ma=C3=ADra=20Canal?= To: Harry Wentland , Leo Li , Rodrigo Siqueira , Alex Deucher , christian.koenig@amd.com, Xinhui.Pan@amd.com, David Airlie , Daniel Vetter Cc: amd-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, mwen@igalia.com, andrealmeid@riseup.net, Isabella Basso , magalilemes00@gmail.com, tales.aparecida@gmail.com, =?UTF-8?q?Ma=C3=ADra=20Canal?= Subject: [PATCH 14/16] drm/amd/display: Remove MaximumDCCCompressionYSurface VBA variable Date: Thu, 28 Jul 2022 15:20:46 -0300 Message-Id: <20220728182047.264825-15-mairacanal@riseup.net> In-Reply-To: <20220728182047.264825-1-mairacanal@riseup.net> References: <20220728182047.264825-1-mairacanal@riseup.net> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The MaximumDCCCompressionYSurface variable from the struct vba_vars_st is only used on assignments, so its value is not used on code. So, remove the MaximumDCCCompressionYSurface entry from the struct vba_vars_st. Signed-off-by: Ma=C3=ADra Canal --- .../amd/display/dc/dml/dcn21/display_mode_vba_21.c | 13 +++---------- .../gpu/drm/amd/display/dc/dml/display_mode_vba.h | 1 - 2 files changed, 3 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c= b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c index bc8cc21cf3f6..7007b6e16e7d 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c @@ -143,7 +143,7 @@ static bool CalculatePrefetchSchedule( double *VReadyOffsetPix); static double RoundToDFSGranularityUp(double Clock, double VCOSpeed); static double RoundToDFSGranularityDown(double Clock, double VCOSpeed); -static double CalculateDCCConfiguration( +static void CalculateDCCConfiguration( bool DCCEnabled, bool DCCProgrammingAssumesScanDirectionUnknown, unsigned int ViewportWidth, @@ -1072,7 +1072,7 @@ static double RoundToDFSGranularityDown(double Clock,= double VCOSpeed) return VCOSpeed * 4 / dml_ceil(VCOSpeed * 4 / Clock, 1); } =20 -static double CalculateDCCConfiguration( +static void CalculateDCCConfiguration( bool DCCEnabled, bool DCCProgrammingAssumesScanDirectionUnknown, unsigned int ViewportWidth, @@ -1087,7 +1087,6 @@ static double CalculateDCCConfiguration( unsigned int *MaxCompressedBlock, unsigned int *Independent64ByteBlock) { - double MaximumDCCCompressionSurface =3D 0.0; enum { REQ_256Bytes, REQ_128BytesNonContiguous, @@ -1185,25 +1184,19 @@ static double CalculateDCCConfiguration( *MaxUncompressedBlock =3D 256; *MaxCompressedBlock =3D 256; *Independent64ByteBlock =3D false; - MaximumDCCCompressionSurface =3D 4.0; } else if (Request =3D=3D REQ_128BytesContiguous) { *MaxUncompressedBlock =3D 128; *MaxCompressedBlock =3D 128; *Independent64ByteBlock =3D false; - MaximumDCCCompressionSurface =3D 2.0; } else if (Request =3D=3D REQ_128BytesNonContiguous) { *MaxUncompressedBlock =3D 256; *MaxCompressedBlock =3D 64; *Independent64ByteBlock =3D true; - MaximumDCCCompressionSurface =3D 4.0; } else { *MaxUncompressedBlock =3D 0; *MaxCompressedBlock =3D 0; *Independent64ByteBlock =3D 0; - MaximumDCCCompressionSurface =3D 0.0; } - - return MaximumDCCCompressionSurface; } =20 static double CalculatePrefetchSourceLines( @@ -2568,7 +2561,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParam= etersWatermarksAndPerforman // DCC Configuration mode_lib->vba.ActiveDPPs =3D 0; for (k =3D 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { - locals->MaximumDCCCompressionYSurface[k] =3D CalculateDCCConfiguration( + CalculateDCCConfiguration( mode_lib->vba.DCCEnable[k], false, // We should always know the direction DCCProgrammingAssumesScan= DirectionUnknown, mode_lib->vba.ViewportWidth[k], diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h b/driver= s/gpu/drm/amd/display/dc/dml/display_mode_vba.h index 46e69f941bff..a07e97035dd1 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h +++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h @@ -1032,7 +1032,6 @@ struct vba_vars_st { unsigned int DCCYMaxUncompressedBlock[DC__NUM_DPP__MAX]; unsigned int DCCYMaxCompressedBlock[DC__NUM_DPP__MAX]; unsigned int DCCYIndependent64ByteBlock[DC__NUM_DPP__MAX]; - double MaximumDCCCompressionYSurface[DC__NUM_DPP__MAX]; unsigned int BlockHeight256BytesY[DC__NUM_DPP__MAX]; unsigned int BlockHeight256BytesC[DC__NUM_DPP__MAX]; unsigned int BlockWidth256BytesY[DC__NUM_DPP__MAX]; --=20 2.37.1 From nobody Wed Apr 15 00:20:29 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D10D6C04A68 for ; Thu, 28 Jul 2022 20:05:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230204AbiG1UFz (ORCPT ); Thu, 28 Jul 2022 16:05:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46648 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229456AbiG1UFy (ORCPT ); Thu, 28 Jul 2022 16:05:54 -0400 Received: from mx0.riseup.net (mx0.riseup.net [198.252.153.6]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CEE437538D for ; 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Thu, 28 Jul 2022 20:05:46 +0000 (UTC) From: =?UTF-8?q?Ma=C3=ADra=20Canal?= To: Harry Wentland , Leo Li , Rodrigo Siqueira , Alex Deucher , christian.koenig@amd.com, Xinhui.Pan@amd.com, David Airlie , Daniel Vetter Cc: magalilemes00@gmail.com, tales.aparecida@gmail.com, linux-kernel@vger.kernel.org, amd-gfx@lists.freedesktop.org, mwen@igalia.com, andrealmeid@riseup.net, =?UTF-8?q?Ma=C3=ADra=20Canal?= Subject: [PATCH 15/16] drm/amd/display: Remove only mencioned once VBA variables Date: Thu, 28 Jul 2022 17:05:41 -0300 Message-Id: <20220728200541.506842-1-mairacanal@riseup.net> In-Reply-To: <20220728182047.264825-1-mairacanal@riseup.net> References: <20220728182047.264825-1-mairacanal@riseup.net> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The variables PercentOfIdealDRAMBWReceivedAfterUrgLatencySTROBE, RefreshRate, FECEnable, ScalerRecoutWidth, MaxNumDP2p0Streams, and MaxNumDP2p0Outputs are only used on assignments, so there values are not used on code. So, remove the variables entries from the struct vba_vars_st. Signed-off-by: Ma=C3=ADra Canal --- .../amd/display/dc/dml/dcn32/display_mode_vba_32.c | 1 - .../gpu/drm/amd/display/dc/dml/display_mode_vba.c | 13 ++----------- .../gpu/drm/amd/display/dc/dml/display_mode_vba.h | 6 ------ 3 files changed, 2 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c= b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c index 3c044549c95f..e9c6cc45bfc3 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c @@ -3715,7 +3715,6 @@ void dml32_ModeSupportAndSystemConfigurationFull(stru= ct display_mode_lib *mode_l } =20 mode_lib->vba.DSCEnabled[k] =3D mode_lib->vba.RequiresDSC[mode_lib->vba.= VoltageLevel][k]; - mode_lib->vba.FECEnable[k] =3D mode_lib->vba.RequiresFEC[mode_lib->vba.V= oltageLevel][k]; mode_lib->vba.OutputBpp[k] =3D mode_lib->vba.OutputBppPerState[mode_lib-= >vba.VoltageLevel][k]; } =20 diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c b/driver= s/gpu/drm/amd/display/dc/dml/display_mode_vba.c index 7a4a013f195a..1176a73813aa 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c +++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c @@ -340,7 +340,6 @@ static void fetch_socbb_params(struct display_mode_lib = *mode_lib) mode_lib->vba.SMNLatency =3D soc->smn_latency_us; mode_lib->vba.MALLAllocatedForDCNFinal =3D soc->mall_allocated_for_dcn_mb= ytes; =20 - mode_lib->vba.PercentOfIdealDRAMBWReceivedAfterUrgLatencySTROBE =3D soc->= pct_ideal_dram_bw_after_urgent_strobe; mode_lib->vba.MaxAveragePercentOfIdealFabricBWDisplayCanUseInNormalSystem= Operation =3D soc->max_avg_fabric_bw_use_normal_percent; mode_lib->vba.MaxAveragePercentOfIdealDRAMBWDisplayCanUseInNormalSystemOp= erationSTROBE =3D @@ -441,11 +440,9 @@ static void fetch_ip_params(struct display_mode_lib *m= ode_lib) mode_lib->vba.CompbufReservedSpaceZs =3D ip->compbuf_reserved_space_zs; mode_lib->vba.CompressedBufferSegmentSizeInkByteFinal =3D ip->compressed_= buffer_segment_size_in_kbytes; mode_lib->vba.LineBufferSizeFinal =3D ip->line_buffer_size_bits; - mode_lib->vba.AlphaPixelChunkSizeInKByte =3D ip->alpha_pixel_chunk_size_k= bytes; // not ysed - mode_lib->vba.MinPixelChunkSizeBytes =3D ip->min_pixel_chunk_size_bytes; = // not used + mode_lib->vba.AlphaPixelChunkSizeInKByte =3D ip->alpha_pixel_chunk_size_k= bytes; + mode_lib->vba.MinPixelChunkSizeBytes =3D ip->min_pixel_chunk_size_bytes; mode_lib->vba.MaximumPixelsPerLinePerDSCUnit =3D ip->maximum_pixels_per_l= ine_per_dsc_unit; - mode_lib->vba.MaxNumDP2p0Outputs =3D ip->max_num_dp2p0_outputs; - mode_lib->vba.MaxNumDP2p0Streams =3D ip->max_num_dp2p0_streams; mode_lib->vba.DCCMetaBufferSizeBytes =3D ip->dcc_meta_buffer_size_bytes; =20 mode_lib->vba.PixelChunkSizeInKByte =3D ip->pixel_chunk_size_kbytes; @@ -560,7 +557,6 @@ static void fetch_pipe_params(struct display_mode_lib *= mode_lib) mode_lib->vba.UsesMALLForPStateChange[mode_lib->vba.NumberOfActivePlanes= ] =3D src->use_mall_for_pstate_change; mode_lib->vba.UseMALLForStaticScreen[mode_lib->vba.NumberOfActivePlanes]= =3D src->use_mall_for_static_screen; mode_lib->vba.GPUVMMinPageSizeKBytes[mode_lib->vba.NumberOfActivePlanes]= =3D src->gpuvm_min_page_size_kbytes; - mode_lib->vba.RefreshRate[mode_lib->vba.NumberOfActivePlanes] =3D dst->r= efresh_rate; //todo remove this mode_lib->vba.OutputLinkDPRate[mode_lib->vba.NumberOfActivePlanes] =3D d= out->dp_rate; mode_lib->vba.ODMUse[mode_lib->vba.NumberOfActivePlanes] =3D dst->odm_co= mbine_policy; mode_lib->vba.DETSizeOverride[mode_lib->vba.NumberOfActivePlanes] =3D sr= c->det_size_override; @@ -606,8 +602,6 @@ static void fetch_pipe_params(struct display_mode_lib *= mode_lib) mode_lib->vba.VActive[mode_lib->vba.NumberOfActivePlanes] =3D dst->vacti= ve; mode_lib->vba.SurfaceTiling[mode_lib->vba.NumberOfActivePlanes] =3D (enum dm_swizzle_mode) (src->sw_mode); - mode_lib->vba.ScalerRecoutWidth[mode_lib->vba.NumberOfActivePlanes] =3D - dst->recout_width; // TODO: or should this be full_recout_width???...m= aybe only when in hsplit mode? mode_lib->vba.ODMCombineEnabled[mode_lib->vba.NumberOfActivePlanes] =3D dst->odm_combine; mode_lib->vba.OutputFormat[mode_lib->vba.NumberOfActivePlanes] =3D @@ -770,7 +764,6 @@ static void fetch_pipe_params(struct display_mode_lib *= mode_lib) if (src->is_hsplit) { for (k =3D j + 1; k < mode_lib->vba.cache_num_pipes; ++k) { display_pipe_source_params_st *src_k =3D &pipes[k].pipe.src; - display_pipe_dest_params_st *dst_k =3D &pipes[k].pipe.dest; =20 if (src_k->is_hsplit && !visited[k] && src->hsplit_grp =3D=3D src_k->hsplit_grp) { @@ -783,8 +776,6 @@ static void fetch_pipe_params(struct display_mode_lib *= mode_lib) src_k->viewport_width; mode_lib->vba.ViewportWidthChroma[mode_lib->vba.NumberOfActivePlanes= ] +=3D src_k->viewport_width_c; - mode_lib->vba.ScalerRecoutWidth[mode_lib->vba.NumberOfActivePlanes] = +=3D - dst_k->recout_width; } else { mode_lib->vba.ViewportHeight[mode_lib->vba.NumberOfActivePlanes] += =3D src_k->viewport_height; diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h b/driver= s/gpu/drm/amd/display/dc/dml/display_mode_vba.h index a07e97035dd1..5eaedc3bf2c8 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h +++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h @@ -437,7 +437,6 @@ struct vba_vars_st { unsigned int MALLAllocatedForDCNFinal; double MaxAveragePercentOfIdealFabricBWDisplayCanUseInNormalSystemOperati= on; double MaxAveragePercentOfIdealDRAMBWDisplayCanUseInNormalSystemOperation= STROBE; - double PercentOfIdealDRAMBWReceivedAfterUrgLatencySTROBE; double WritebackLatency; double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelDa= taOnly; // Mode Support double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMi= xedWithVMData; // Mode Support @@ -528,7 +527,6 @@ struct vba_vars_st { unsigned int MinCompressedBufferSizeInKByte; unsigned int NumberOfActiveSurfaces; bool ViewportStationary[DC__NUM_DPP__MAX]; - unsigned int RefreshRate[DC__NUM_DPP__MAX]; double OutputBPP[DC__NUM_DPP__MAX]; unsigned int GPUVMMinPageSizeKBytes[DC__NUM_DPP__MAX]; bool SynchronizeTimingsFinal; @@ -564,7 +562,6 @@ struct vba_vars_st { double PixelClock[DC__NUM_DPP__MAX]; double PixelClockBackEnd[DC__NUM_DPP__MAX]; bool DCCEnable[DC__NUM_DPP__MAX]; - bool FECEnable[DC__NUM_DPP__MAX]; unsigned int DCCMetaPitchY[DC__NUM_DPP__MAX]; unsigned int DCCMetaPitchC[DC__NUM_DPP__MAX]; enum scan_direction_class SourceScan[DC__NUM_DPP__MAX]; @@ -585,7 +582,6 @@ struct vba_vars_st { unsigned int VActive[DC__NUM_DPP__MAX]; bool Interlace[DC__NUM_DPP__MAX]; enum dm_swizzle_mode SurfaceTiling[DC__NUM_DPP__MAX]; - unsigned int ScalerRecoutWidth[DC__NUM_DPP__MAX]; bool DynamicMetadataEnable[DC__NUM_DPP__MAX]; int DynamicMetadataLinesBeforeActiveRequired[DC__NUM_DPP__MAX]; unsigned int DynamicMetadataTransmittedBytes[DC__NUM_DPP__MAX]; @@ -753,8 +749,6 @@ struct vba_vars_st { bool DCCProgrammingAssumesScanDirectionUnknownFinal; bool EnoughWritebackUnits; bool ODMCombine2To1SupportCheckOK[DC__VOLTAGE_STATES]; - unsigned int MaxNumDP2p0Streams; - unsigned int MaxNumDP2p0Outputs; enum dm_output_type OutputTypePerState[DC__VOLTAGE_STATES][DC__NUM_DPP__M= AX]; enum dm_output_rate OutputRatePerState[DC__VOLTAGE_STATES][DC__NUM_DPP__M= AX]; double WritebackLineBufferLumaBufferSize; --=20 2.37.1 From nobody Wed Apr 15 00:20:29 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 514D9C19F2B for ; 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a=rsa-sha256; c=relaxed/simple; d=riseup.net; s=squak; t=1659038787; bh=qMkVhpHfimqGZ1UHe8cnMLY3YgQI8b39H7ayhDfdi6Y=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=KjxI3gik4u0EyftYF37MDXA2IlhpWeTCfn9LKSIq4qtJXUVUdBY2Mfoki7d6Nlsx9 qw4G8GIIqMWpOQHTJX5YCE7sgItB/Jk4o/Ii1RF2YsB4a0uUe5PZGVBXAjPkPepUKG e0/RklUyyBcKTyS0Njh1b6GVCW1aZiI9wLFewjJM= X-Riseup-User-ID: 951C84FCE757D20387021224588B25A3FBE76A1B970D0C2DC7BD085DD24D9ED8 Received: from [127.0.0.1] (localhost [127.0.0.1]) by fews1.riseup.net (Postfix) with ESMTPSA id 4Lv1qy64Mzz5vTb; Thu, 28 Jul 2022 20:06:22 +0000 (UTC) From: =?UTF-8?q?Ma=C3=ADra=20Canal?= To: Harry Wentland , Leo Li , Rodrigo Siqueira , Alex Deucher , christian.koenig@amd.com, Xinhui.Pan@amd.com, David Airlie , Daniel Vetter Cc: magalilemes00@gmail.com, tales.aparecida@gmail.com, linux-kernel@vger.kernel.org, amd-gfx@lists.freedesktop.org, mwen@igalia.com, andrealmeid@riseup.net, =?UTF-8?q?Ma=C3=ADra=20Canal?= Subject: [PATCH 16/16] drm/amd/display: Remove never used VBA variables Date: Thu, 28 Jul 2022 17:06:16 -0300 Message-Id: <20220728200616.514993-1-mairacanal@riseup.net> In-Reply-To: <20220728182047.264825-1-mairacanal@riseup.net> References: <20220728182047.264825-1-mairacanal@riseup.net> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The variables OutputBPP, VTotal_Min, TotalBandwidthConsumedGBytePerSecond, BandwidthSupport, dummy_integer_array, dummysinglestring, SurfaceRequiredDISPCLKWithoutODMCombine, SurfaceRequiredDISPCLK, MinVoltageLevel, and MaxVoltageLevel are never used. So, remove the variables entries from the struct vba_vars_st. Signed-off-by: Ma=C3=ADra Canal --- drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h b/driver= s/gpu/drm/amd/display/dc/dml/display_mode_vba.h index 5eaedc3bf2c8..839f8fde4b47 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h +++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h @@ -527,7 +527,6 @@ struct vba_vars_st { unsigned int MinCompressedBufferSizeInKByte; unsigned int NumberOfActiveSurfaces; bool ViewportStationary[DC__NUM_DPP__MAX]; - double OutputBPP[DC__NUM_DPP__MAX]; unsigned int GPUVMMinPageSizeKBytes[DC__NUM_DPP__MAX]; bool SynchronizeTimingsFinal; bool SynchronizeDRRDisplaysForUCLKPStateChangeFinal; @@ -557,7 +556,6 @@ struct vba_vars_st { unsigned int HTotal[DC__NUM_DPP__MAX]; unsigned int VTotal[DC__NUM_DPP__MAX]; unsigned int VTotal_Max[DC__NUM_DPP__MAX]; - unsigned int VTotal_Min[DC__NUM_DPP__MAX]; int DPPPerPlane[DC__NUM_DPP__MAX]; double PixelClock[DC__NUM_DPP__MAX]; double PixelClockBackEnd[DC__NUM_DPP__MAX]; @@ -690,12 +688,10 @@ struct vba_vars_st { /*outputs*/ bool ScaleRatioAndTapsSupport; bool SourceFormatPixelAndScanSupport; - double TotalBandwidthConsumedGBytePerSecond; bool DCCEnabledInAnyPlane; bool WritebackLatencySupport; bool WritebackModeSupport; bool Writeback10bpc420Supported; - bool BandwidthSupport[DC__VOLTAGE_STATES]; unsigned int TotalNumberOfActiveWriteback; double CriticalPoint; double ReturnBWToDCNPerState; @@ -955,9 +951,7 @@ struct vba_vars_st { unsigned int dummyinteger9; unsigned int dummyinteger10; unsigned int dummyinteger11; - unsigned int dummy_integer_array[8][DC__NUM_DPP__MAX]; =20 - bool dummysinglestring; bool SingleDPPViewportSizeSupportPerPlane[DC__NUM_DPP__MAX]; double PlaneRequiredDISPCLKWithODMCombine2To1; double PlaneRequiredDISPCLKWithODMCombine4To1; @@ -1248,11 +1242,7 @@ struct vba_vars_st { unsigned int NotEnoughUrgentLatencyHidingA[DC__VOLTAGE_STATES][2]; double ReadBandwidthSurfaceLuma[DC__NUM_DPP__MAX]; double ReadBandwidthSurfaceChroma[DC__NUM_DPP__MAX]; - double SurfaceRequiredDISPCLKWithoutODMCombine; - double SurfaceRequiredDISPCLK; double MinActiveFCLKChangeLatencySupported; - int MinVoltageLevel; - int MaxVoltageLevel; unsigned int TotalNumberOfSingleDPPSurfaces[DC__VOLTAGE_STATES][2]; unsigned int CompressedBufferSizeInkByteAllStates[DC__VOLTAGE_STATES][2]; unsigned int DETBufferSizeInKByteAllStates[DC__VOLTAGE_STATES][2][DC__NUM= _DPP__MAX]; --=20 2.37.1